luchianmihai/walnux
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

arch: armv7-a: Fix style warnings in arm_l2cc_pl310.c

Browse source 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
Masayuki Ishikawa 2020-11-16 13:31:36 +09:00 • committed by Xiang Xiao
parent 8d02bce8e5
commit 94b43b93e5
1 changed files with 23 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

37
arch/arm/src/armv7-a/arm_l2cc_pl310.c
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/chip/arm-l2cc_pl310.c
*
* Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
@ -36,7 +36,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Included Files
@ -59,7 +59,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***********************************************************/
/* Configuration ************************************************************/
/* Number of ways depends on ARM configuration */
#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
@ -315,18 +317,19 @@ void arm_l2ccinitialize(void)
/* Make sure that this is a PL310 cache, version r3p2.
*
* REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which is
* r3p2, but the chip that I have actually* reports 0x410000C9 which is some
* later revision.
* REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which
* is r3p2, but the chip that I have actually* reports 0x410000C9 which
* is some later revision.
*/
//DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2);
/* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) ==
* L2CC_IDR_REV_R3P2);
*/
/* Make sure that actual cache configuration agrees with the configured
* cache configuration.
*/
#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0);
#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
@ -336,17 +339,23 @@ void arm_l2ccinitialize(void)
#endif
#if defined(CONFIG_ARMV7A_WAYSIZE_16KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_16KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_32KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_32KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_64KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_64KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_128KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_128KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_256KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_256KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_512KB);
#else
# error No way size selected
#endif