From 95340ebfdae1642267795779a7c2fdcc1e1d2579 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Apr 2019 13:28:38 +0000 Subject: [PATCH] Merged in raiden00/nuttx_l0f0 (pull request #852) Support for STM32L071X and a few improvements for STM32F0L0 arch/arm/src/stm32f0l0: add peripherals configuration for STM32L0 arch/arm/src/stm32f0l0: a few fixes for USART arch/arm/include/stm32f0l0/stm32f0_irq.h: use names as in other STM32 arch/arm/include/stm32f0l0/chip.h: use names as in other STM32 Approved-by: Gregory Nutt --- arch/arm/include/stm32f0l0/chip.h | 173 +++++++++++------- arch/arm/include/stm32f0l0/stm32f0_irq.h | 63 ++++--- arch/arm/src/stm32f0l0/Kconfig | 148 +++++++++++++-- .../stm32f0l0/hardware/stm32l0_memorymap.h | 4 +- .../src/stm32f0l0/hardware/stm32l0_pinmap.h | 10 +- arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h | 12 +- .../arm/src/stm32f0l0/hardware/stm32l0_uart.h | 65 +++---- arch/arm/src/stm32f0l0/stm32_serial.c | 6 +- arch/arm/src/stm32f0l0/stm32l0_rcc.c | 8 +- 9 files changed, 330 insertions(+), 159 deletions(-) diff --git a/arch/arm/include/stm32f0l0/chip.h b/arch/arm/include/stm32f0l0/chip.h index f5d6c3b6c3..fa9446b728 100644 --- a/arch/arm/include/stm32f0l0/chip.h +++ b/arch/arm/include/stm32f0l0/chip.h @@ -61,8 +61,7 @@ # define STM32_NCAN 0 /* No CAN controllers */ # define STM32_NUSBDEV 1 /* One USB full-speed device controller */ # define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NDAC 1 /* One DAC module */ -# define STM32_NDACCHAN 1 /* One DAC channels */ +# define STM32_NDAC 1 /* One DAC channel */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */ # define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ @@ -88,11 +87,8 @@ # define STM32_NUSBDEV 1 /* One USB full-speed device controller */ # define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit module */ -# define STM32_NADCCHAN 10 /* Ten external channels */ -# define STM32_NADCINT 3 /* Three internal channels */ -# define STM32_NDAC 1 /* One DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCAP 17 /* Capacitive sensing channels */ # define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ @@ -118,11 +114,8 @@ # define STM32_NUSBDEV 1 /* One USB full-speed device controller */ # define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit module */ -# define STM32_NADCCHAN 16 /* 16 external channels */ -# define STM32_NADCINT 3 /* Three internal channels */ -# define STM32_NDAC 1 /* One DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCAP 18 /* Capacitive sensing channels */ # define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ @@ -148,11 +141,8 @@ # define STM32_NUSBDEV 1 /* One USB full-speed device controller */ # define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit module */ -# define STM32_NADCCHAN 16 /* 16 external channels */ -# define STM32_NADCINT 3 /* Three internal channels */ -# define STM32_NDAC 1 /* One DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCAP 24 /* Capacitive sensing channels */ # define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ @@ -178,11 +168,8 @@ # define STM32_NUSBDEV 0 /* No USB full-speed device controller */ # define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit module */ -# define STM32_NADCCHAN 10 /* 10 external channels */ -# define STM32_NADCINT 3 /* Three internal channels */ -# define STM32_NDAC 1 /* One DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCAP 17 /* Capacitive sensing channels */ # define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ @@ -209,11 +196,8 @@ # define STM32_NUSBDEV 0 /* No USB full-speed device controller */ # define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit module */ -# define STM32_NADCCHAN 16 /* 16 external channels */ -# define STM32_NADCINT 3 /* Three internal channels */ -# define STM32_NDAC 1 /* One DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) # define STM32_NCAP 24 /* Capacitive sensing channels */ @@ -223,9 +207,10 @@ # define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ /* STM32L EnergyLite Line ***********************************************************/ - -/* STM32L03XX - With LCD - * STM32L02XX - No LCD + +/* STM32L073XX - With LCD + * STM32L072XX - No LCD + * STM32L071XX - Access line, no LCD * * STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM * STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM @@ -236,6 +221,87 @@ * STM32L0XXVX - 100-pins */ +#elif defined(CONFIG_ARCH_CHIP_STM32L071K8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ +# define STM32_NI2S 0 /* 0 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \ + defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ) +# define STM32_NATIM 0 /* 0 advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 3 /* 3 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ) +# define STM32_NATIM 0 /* 0 advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ +# define STM32_NI2S 0 /* 0 I2S module */ +# define STM32_NI2C 3 /* 3 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + #elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \ defined(CONFIG_ARCH_CHIP_STM32L072VZ) # define STM32_NATIM 0 /* No advanced timers */ @@ -255,11 +321,8 @@ # define STM32_NUSBDEV 0 /* No USB full-speed device controller */ # define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit ADC module */ -# define STM32_NADCCHAN 14 /* 14 channels */ -# define STM32_NADCINT 0 /* ? internal channels vs external? */ -# define STM32_NDAC 2 /* Two DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCRC 1 /* One CRC module */ # define STM32_NRNG 1 /* One Random number generator (RNG) */ @@ -283,9 +346,8 @@ # define STM32_NUSBDEV 0 /* No USB full-speed device controller */ # define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 14-channels */ -# define STM32_NDAC 2 /* Two DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCRC 1 /* One CRC module */ # define STM32_NRNG 1 /* One Random number generator (RNG) */ @@ -310,11 +372,8 @@ # define STM32_NUSBDEV 0 /* No USB full-speed device controller */ # define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit ADC module */ -# define STM32_NADCCHAN 14 /* 14 channels */ -# define STM32_NADCINT 0 /* ? internal channels vs external? */ -# define STM32_NDAC 2 /* Two DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCRC 1 /* One CRC module */ # define STM32_NRNG 1 /* One Random number generator (RNG) */ @@ -339,11 +398,8 @@ # define STM32_NUSBDEV 0 /* No USB full-speed device controller */ # define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit ADC module */ -# define STM32_NADCCHAN 14 /* 14 channels */ -# define STM32_NADCINT 0 /* ? internal channels vs external? */ -# define STM32_NDAC 2 /* Two DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCRC 1 /* One CRC module */ # define STM32_NRNG 1 /* One Random number generator (RNG) */ @@ -369,11 +425,8 @@ # define STM32_NUSBDEV 0 /* No USB full-speed device controller */ # define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit ADC module */ -# define STM32_NADCCHAN 14 /* 14 channels */ -# define STM32_NADCINT 0 /* ? internal channels vs external? */ -# define STM32_NDAC 2 /* Two DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCRC 1 /* One CRC module */ # define STM32_NRNG 1 /* One Random number generator (RNG) */ @@ -398,11 +451,8 @@ # define STM32_NUSBDEV 0 /* No USB full-speed device controller */ # define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit ADC module */ -# define STM32_NADCCHAN 14 /* 14 channels */ -# define STM32_NADCINT 0 /* ? internal channels vs external? */ -# define STM32_NDAC 2 /* Two DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCRC 1 /* One CRC module */ # define STM32_NRNG 1 /* One Random number generator (RNG) */ @@ -427,11 +477,8 @@ # define STM32_NUSBDEV 0 /* No USB full-speed device controller */ # define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ # define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC12 1 /* One 12-bit ADC module */ -# define STM32_NADCCHAN 14 /* 14 channels */ -# define STM32_NADCINT 0 /* ? internal channels vs external? */ -# define STM32_NDAC 2 /* Two DAC module */ -# define STM32_NDACCHAN 2 /* Two DAC channels */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ # define STM32_NCOMP 2 /* Two Analog Comparators */ # define STM32_NCRC 1 /* One CRC module */ # define STM32_NRNG 1 /* One Random number generator (RNG) */ diff --git a/arch/arm/include/stm32f0l0/stm32f0_irq.h b/arch/arm/include/stm32f0l0/stm32f0_irq.h index 52ad609a93..f04da690a8 100644 --- a/arch/arm/include/stm32f0l0/stm32f0_irq.h +++ b/arch/arm/include/stm32f0l0/stm32f0_irq.h @@ -70,29 +70,46 @@ #define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */ #define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */ #define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC */ -#define STM32_IRQ_DMA_CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA_CH1 */ -#define STM32_IRQ_DMA_CH23 (STM32_IRQ_EXTINT + 10) /* 0: DMA_CH2_3 and DMA2_CH1_2 */ -#define STM32_IRQ_DMA_CH4567 (STM32_IRQ_EXTINT + 11) /* 1: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */ -#define STM32_IRQ_ADC_COMP (STM32_IRQ_EXTINT + 12) /* 2: ADC_COMP */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 3: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 4: TIM1_CC */ -#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 5: TIM2 */ -#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 6: TIM3 */ -#define STM32_IRQ_TIM6_DAC (STM32_IRQ_EXTINT + 17) /* 7: TIM6 and DAC */ -#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 8: TIM7 */ -#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 9: TIM14 */ -#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 0: TIM15 */ -#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 1: TIM16 */ -#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 2: TIM17 */ -#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 3: I2C1 */ -#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 4: I2C2 */ -#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 5: SPI1 */ -#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 6: SPI2 */ -#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 7: USART1 */ -#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 8: USART2 */ -#define STM32_IRQ_USART345678 (STM32_IRQ_EXTINT + 29) /* 9: USART3_4_5_6_7_8 */ -#define STM32_IRQ_CEC_CAN (STM32_IRQ_EXTINT + 30) /* 0: HDMI CEC and CAN */ -#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 1: USB */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH1 */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH2 */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ +#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ +#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ +#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ +#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ +#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ +#define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */ +#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */ +#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */ +#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */ +#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */ +#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */ +#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */ +#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */ +#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */ +#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */ +#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */ +#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */ +#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */ +#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */ +#define STM32_IRQ_USART5 (STM32_IRQ_EXTINT + 29) /* 29: USART5 */ +#define STM32_IRQ_USART6 (STM32_IRQ_EXTINT + 29) /* 29: USART6 */ +#define STM32_IRQ_USART7 (STM32_IRQ_EXTINT + 29) /* 29: USART7 */ +#define STM32_IRQ_USART8 (STM32_IRQ_EXTINT + 29) /* 29: USART8 */ +#define STM32_IRQ_CEC (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */ +#define STM32_IRQ_CAN (STM32_IRQ_EXTINT + 30) /* 30: HDMI CAN */ +#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB */ #define STM32_IRQ_NEXTINT (32) /* 32 external interrupts */ diff --git a/arch/arm/src/stm32f0l0/Kconfig b/arch/arm/src/stm32f0l0/Kconfig index 7343e27278..84574e753d 100644 --- a/arch/arm/src/stm32f0l0/Kconfig +++ b/arch/arm/src/stm32f0l0/Kconfig @@ -449,84 +449,177 @@ config ARCH_CHIP_STM32F098VC select STM32F0L0_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 +config ARCH_CHIP_STM32L071K8 + bool "STM32L071K8" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071KB + bool "STM32L071KB" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071KZ + bool "STM32L071KZ" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071C8 + bool "STM32L071C8" + select ARCH_CHIP_STM32L071XX + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071CB + bool "STM32L071CB" + select ARCH_CHIP_STM32L071XX + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071CZ + bool "STM32L071CZ" + select ARCH_CHIP_STM32L071XX + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071V8 + bool "STM32L071V8" + select ARCH_CHIP_STM32L071XX + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071VB + bool "STM32L071VB" + select ARCH_CHIP_STM32L071XX + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071VZ + bool "STM32L071VZ" + select ARCH_CHIP_STM32L071XX + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071RB + bool "STM32L071RB" + select ARCH_CHIP_STM32L071XX + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071RZ + bool "STM32L071RZ" + select ARCH_CHIP_STM32L071XX + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + config ARCH_CHIP_STM32L072V8 bool "STM32L072V8" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L072XX + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VB bool "STM32L072VB" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L072XX + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VZ bool "STM32L072VZ" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L072XX + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072KB bool "STM32L072KB" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L072XX depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072KZ bool "STM32L072KZ" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L072XX depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072CB bool "STM32L072CB" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L072XX + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072CZ bool "STM32L072CZ" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L072XX + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RB bool "STM32L072RB" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L072XX + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RZ bool "STM32L072RZ" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L072XX + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073V8 bool "STM32L073V8" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L073XX depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073VB bool "STM32L073VB" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L073XX depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073VZ bool "STM32L073VZ" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L073XX depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073CB bool "STM32L073CB" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L073XX depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073CZ bool "STM32L073CZ" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L073XX depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073RB bool "STM32L073RB" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L073XX depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073RZ bool "STM32L073RZ" - select STM32F0L0_STM32L0 + select ARCH_CHIP_STM32L073XX depends on ARCH_CHIP_STM32L0 endchoice # ST STM32F0/L0 Chip Selection @@ -719,6 +812,29 @@ config STM32F0L0_ENERGYLITE bool default n +config ARCH_CHIP_STM32L071XX + bool + select STM32F0L0_STM32L0 + select STM32F0L0_HAVE_USART4 + +config ARCH_CHIP_STM32L072XX + bool + select STM32F0L0_STM32L0 + select STM32F0L0_HAVE_USART4 + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_I2C2 + select STM32F0L0_HAVE_USBDEV + +config ARCH_CHIP_STM32L073XX + bool + select STM32F0L0_STM32L0 + select STM32F0L0_HAVE_USART4 + select STM32F0L0_HAVE_USART5 + select STM32F0L0_HAVE_SPI2 + select STM32F0L0_HAVE_I2C2 + select STM32F0L0_HAVE_I2C3 + select STM32F0L0_HAVE_USBDEV + config STM32F0L0_DFU bool "DFU bootloader" default n diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h b/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h index f6ac7a385c..16ec89f634 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h @@ -84,8 +84,8 @@ #define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2 */ #define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */ #define STM32_LPUART1_BASE 0x40004800 /* 0x40004800-0x40004bff LPUART1 */ -#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff UART4 */ -#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff UART5 */ +#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */ +#define STM32_USART5_BASE 0x40005000 /* 0x40005000-0x400053ff USART5 */ #define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */ #define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */ #define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h b/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h index fc2a6e3111..a35ae325c8 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h @@ -308,16 +308,20 @@ #define GPIO_USART2_RTS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN4) #define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3) #define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN6) +#define GPIO_USART2_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15) #define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2) #define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN5) +#define GPIO_USART2_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN14) -#define GPIO_USART2_CK (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN12) -#define GPIO_USART2_RTS (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN15) -#define GPIO_USART2_CTS (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_USART4_CK (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN12) +#define GPIO_USART4_RTS (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_USART4_CTS (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN7) #define GPIO_USART4_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN11) #define GPIO_USART4_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN9) +#define GPIO_USART4_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN1) #define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN10) #define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN8) +#define GPIO_USART4_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN0) #define GPIO_USART5_CK_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN5) #define GPIO_USART5_CK_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTE | GPIO_PIN7) diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h index 0b2736d183..f021edc850 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h @@ -318,8 +318,8 @@ /* Bits 15-16: Reserved */ #define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */ #define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */ -#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: UART 4 reset */ -#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: UART 5 reset */ +#define RCC_APB1RSTR_USART4RST (1 << 19) /* Bit 19: USART 4 reset */ +#define RCC_APB1RSTR_USART5RST (1 << 20) /* Bit 20: USART 5 reset */ #define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */ #define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */ @@ -388,8 +388,8 @@ /* Bits 15-16: Reserved */ #define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */ #define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */ -#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */ -#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */ +#define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART 4 clock enable */ +#define RCC_APB1ENR_USART5EN (1 << 20) /* Bit 20: USART 5 clock enable */ #define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */ #define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */ #define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */ @@ -458,8 +458,8 @@ /* Bits 15-16: Reserved */ #define RCC_APB1SMENR_USART2SMEN (1 << 17) /* Bit 17: USART 2 clock enable in Sleep mode */ #define RCC_APB1SMENR_USART3SMEN (1 << 18) /* Bit 18: USART 3 clock enable in Sleep mode */ -#define RCC_APB1SMENR_UART4SMEN (1 << 19) /* Bit 19: UART 4 clock enable in Sleep mode */ -#define RCC_APB1SMENR_UART5SMEN (1 << 20) /* Bit 20: UART 5 clock enable in Sleep mode */ +#define RCC_APB1SMENR_USART4SMEN (1 << 19) /* Bit 19: USART 4 clock enable in Sleep mode */ +#define RCC_APB1SMENR_USART5SMEN (1 << 20) /* Bit 20: USART 5 clock enable in Sleep mode */ #define RCC_APB1SMENR_I2C1SMEN (1 << 21) /* Bit 21: I2C 1 clock enable in Sleep mode */ #define RCC_APB1SMENR_I2C2SMEN (1 << 22) /* Bit 22: I2C 2 clock enable in Sleep mode */ #define RCC_APB1SMENR_USBSMEN (1 << 23) /* Bit 23: USB clock enable in Sleep mode */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h b/arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h index 0f6fc436ef..ad25ea2ff3 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h @@ -94,49 +94,36 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif +/* No UART 3 in L0 */ + #if STM32_NUSART > 2 -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) +# define STM32_USART4_CR1 (STM32_USART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART4_CR2 (STM32_USART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART4_CR3 (STM32_USART4_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART4_BRR (STM32_USART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART4_GTPR (STM32_USART4_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART4_RTOR (STM32_USART4_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART4_RQR (STM32_USART4_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART4_GTPR (STM32_USART4_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART4_ISR (STM32_USART4_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART4_ICR (STM32_USART4_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART4_RDR (STM32_USART4_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART4_TDR (STM32_USART4_BASE+STM32_USART_TDR_OFFSET) #endif #if STM32_NUSART > 3 -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) +# define STM32_USART5_CR1 (STM32_USART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART5_CR2 (STM32_USART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART5_CR3 (STM32_USART5_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART5_BRR (STM32_USART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART5_GTPR (STM32_USART5_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART5_RTOR (STM32_USART5_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART5_RQR (STM32_USART5_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART5_GTPR (STM32_USART5_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART5_ISR (STM32_USART5_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART5_ICR (STM32_USART5_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART5_RDR (STM32_USART5_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART5_TDR (STM32_USART5_BASE+STM32_USART_TDR_OFFSET) #endif /* Register Bitfield Definitions ****************************************************/ diff --git a/arch/arm/src/stm32f0l0/stm32_serial.c b/arch/arm/src/stm32f0l0/stm32_serial.c index d38a9b21b2..9815792854 100644 --- a/arch/arm/src/stm32f0l0/stm32_serial.c +++ b/arch/arm/src/stm32f0l0/stm32_serial.c @@ -553,7 +553,7 @@ static struct stm32_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32_IRQ_USART345678, + .irq = STM32_IRQ_USART3, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, @@ -614,7 +614,7 @@ static struct stm32_serial_s g_usart4priv = .priv = &g_usart4priv, }, - .irq = STM32_IRQ_USART345678, + .irq = STM32_IRQ_USART4, .parity = CONFIG_USART4_PARITY, .bits = CONFIG_USART4_BITS, .stopbits2 = CONFIG_USART4_2STOP, @@ -679,7 +679,7 @@ static struct stm32_serial_s g_usart5priv = .priv = &g_usart5priv, }, - .irq = STM32_IRQ_USART345678, + .irq = STM32_IRQ_USART5, .parity = CONFIG_USART5_PARITY, .bits = CONFIG_USART5_BITS, .stopbits2 = CONFIG_USART5_2STOP, diff --git a/arch/arm/src/stm32f0l0/stm32l0_rcc.c b/arch/arm/src/stm32f0l0/stm32l0_rcc.c index fc83e0c134..723fa80836 100644 --- a/arch/arm/src/stm32f0l0/stm32l0_rcc.c +++ b/arch/arm/src/stm32f0l0/stm32l0_rcc.c @@ -251,19 +251,19 @@ static inline void rcc_enableapb1(void) #endif #endif -#ifdef CONFIG_STM32F0L0_UART4 +#ifdef CONFIG_STM32F0L0_USART4 /* USART 4 clock enable */ #ifdef CONFIG_STM32F0L0_FORCEPOWER - regval |= RCC_APB1ENR_UART4EN; + regval |= RCC_APB1ENR_USART4EN; #endif #endif -#ifdef CONFIG_STM32F0L0_UART5 +#ifdef CONFIG_STM32F0L0_USART5 /* USART 5 clock enable */ #ifdef CONFIG_STM32F0L0_FORCEPOWER - regval |= RCC_APB1ENR_UART5EN; + regval |= RCC_APB1ENR_USART5EN; #endif #endif