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arch/risc-v/src/mpfs/mpfs_coremmc: clock, buswidth and fifo depth fixed

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4bit bus width support and FIC0 clock is 125MHz
VR register fifo depth bitfields 5:4 instead of 3:2
This commit is contained in:
Jari Nippula 2025-02-10 16:58:57 +02:00 • committed by Xiang Xiao
parent 5020572871
commit 96298efac8
1 changed files with 7 additions and 2 deletions
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9
arch/risc-v/src/mpfs/mpfs_coremmc.c
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@ -125,7 +125,7 @@
/* Clocks and timing */
#define MPFS_FPGA_FIC0_CLK (50000000)
#define MPFS_FPGA_FIC0_CLK (125000000)
#define COREMMC_CMDTIMEOUT (100000)
#define COREMMC_LONGTIMEOUT (100000000)
@ -1039,7 +1039,7 @@ static bool mpfs_device_reset(struct sdio_dev_s *dev)
/* Store fifo size for later to check no fifo overruns occur */
fifo_size = ((getreg8(MPFS_COREMMC_VR) >> 2) & 0x3);
fifo_size = ((getreg8(MPFS_COREMMC_VR) >> 4) & 0x3);
if (fifo_size == 0)
{
priv->fifo_depth = 512;
@ -1122,6 +1122,11 @@ static sdio_capset_t mpfs_capabilities(struct sdio_dev_s *dev)
caps |= SDIO_CAPS_1BIT_ONLY;
}
if (((getreg8(MPFS_COREMMC_VR) >> 2) & 3) == 0x01)
{
caps |= SDIO_CAPS_4BIT;
}
return caps;
}