xtensa/esp32s3: allow moving .bss data to the external PSRAM
This commit allows placing .bss data into the external PSRAM. Previously, the PSRAM was fully allocated to the heap memory only and now part of it can be used to allocate .bss data freeing the internal memory.
This commit is contained in:
Tiago Medicci Serrano
Alan C. Assis
parent
32bc95182a
commit
97aa90570c
3 changed files with 96 additions and 58 deletions
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@ -122,6 +122,9 @@ static struct smp_call_data_s g_call_data =
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SMP_CALL_INITIALIZER(pause_cpu_handler, NULL);
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#endif
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extern uint8_t _ext_ram_bss_start;
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extern uint8_t _ext_ram_bss_end;
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/****************************************************************************
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* ROM Function Prototypes
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****************************************************************************/
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@ -393,6 +396,7 @@ int IRAM_ATTR esp_spiram_init_cache(void)
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uint32_t mapped_vaddr_size;
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uint32_t target_mapped_vaddr_start;
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uint32_t target_mapped_vaddr_end;
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uint32_t ext_bss_size;
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int ret = psram_get_available_size(&psram_size);
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if (ret != OK)
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@ -473,10 +477,12 @@ int IRAM_ATTR esp_spiram_init_cache(void)
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cache_resume_dcache(0);
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/* Currently no non-heap stuff on ESP32S3 */
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ext_bss_size = ((intptr_t)&_ext_ram_bss_end -
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(intptr_t)&_ext_ram_bss_start);
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g_allocable_vaddr_start = g_mapped_vaddr_start;
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g_allocable_vaddr_end = g_mapped_vaddr_start + g_mapped_size;
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g_allocable_vaddr_start = g_mapped_vaddr_start + ext_bss_size;
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g_allocable_vaddr_end = g_mapped_vaddr_start + g_mapped_size -
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ext_bss_size;
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return ret;
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}
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@ -438,9 +438,64 @@ SECTIONS
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_sheap = ABSOLUTE(.);
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} >dram0_0_seg AT>ROM
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_image_drom_vma = ADDR(.flash.rodata);
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_image_drom_lma = LOADADDR(.flash.rodata);
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_image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma;
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/* The alignment of the ".flash.text" output section is forced to
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* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
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* of the next available Flash block.
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* This is required to meet the following constraint from the external
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* flash MMU:
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* VMA % 64KB == LMA % 64KB
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* i.e. the lower 16 bits of both the virtual address (address seen by the
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* CPU) and the load address (physical address of the external flash) must
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* be equal.
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*/
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.flash.text : ALIGN(0x00010000)
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{
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_stext = .;
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_instruction_reserved_start = ABSOLUTE(.);
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram.*)
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*(.wifiextrairam .wifiextrairam.*)
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*(EXCLUDE_FILE(*libpp.a) .wifiorslpiram EXCLUDE_FILE(*libpp.a) .wifiorslpiram.*)
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*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram.*)
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*(.wifislpiram .wifislpiram.*)
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*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram.*)
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/* CPU will try to prefetch up to 16 bytes of instructions.
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* This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += 16;
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_instruction_reserved_end = ABSOLUTE(.);
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_etext = .;
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} >irom0_0_seg AT>ROM
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_image_irom_vma = ADDR(.flash.text);
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_image_irom_lma = LOADADDR(.flash.text);
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_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
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/* Dummy section represents the .flash.text section but in drom0_0_seg.
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* Thus, it must have its alignment and (at least) its size.
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*/
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.flash.rodata_dummy (NOLOAD) :
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{
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_flash_rodata_dummy_start = ABSOLUTE(.);
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. = ALIGN(ALIGNOF(.flash.text)) + SIZEOF(.flash.text);
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/* Add alignment of MMU page size + 0x20 bytes for the mapping header. */
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. = ALIGN(0x10000) + 0x20;
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} > drom0_0_seg
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/* The alignment of the ".flash.rodata" output section is forced to
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* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
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@ -453,11 +508,6 @@ SECTIONS
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* be equal.
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*/
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.flash.rodata_dummy (NOLOAD) :
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{
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. = ALIGN(0x10000);
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} > ROM
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.flash.rodata : ALIGN(0x10000)
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{
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_rodata_reserved_start = ABSOLUTE(.);
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@ -544,62 +594,33 @@ SECTIONS
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} >drom0_0_seg AT>ROM
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_rodata_reserved_align = ALIGNOF(.flash.rodata);
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_image_irom_vma = ADDR(.flash.text);
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_image_irom_lma = LOADADDR(.flash.text);
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_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
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_image_drom_vma = ADDR(.flash.rodata);
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_image_drom_lma = LOADADDR(.flash.rodata);
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_image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma;
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/* The alignment of the ".flash.text" output section is forced to
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* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
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* of the next available Flash block.
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* This is required to meet the following constraint from the external
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* flash MMU:
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* VMA % 64KB == LMA % 64KB
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* i.e. the lower 16 bits of both the virtual address (address seen by the
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* CPU) and the load address (physical address of the external flash) must
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* be equal.
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/* Dummy section to skip flash rodata sections.
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* Because to `extern_ram_seg` and `drom0_0_seg` are on the same bus
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*/
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#ifndef CONFIG_ESP32S3_RUN_IRAM
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.flash.text_dummy (NOLOAD) : ALIGN(0x10000)
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.ext_ram.dummy (NOLOAD):
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{
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/* This section is required to skip .flash.rodata area because irom0_0_seg
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* and drom0_0_seg reflect the same address space on different buses.
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*/
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. = ORIGIN(extern_ram_seg);
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. = . + (_rodata_reserved_end - _flash_rodata_dummy_start);
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. = ALIGN (0x10000);
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} > extern_ram_seg
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. += _image_drom_lma;
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. += _image_drom_size;
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} >irom0_0_seg
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#endif
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/* This section holds .ext_ram.bss data, and will be put in PSRAM */
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.flash.text : ALIGN(0x00010000)
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.ext_ram.bss (NOLOAD) :
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{
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_stext = .;
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_instruction_reserved_start = ABSOLUTE(.);
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_ext_ram_bss_start = ABSOLUTE(.);
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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*(.ext_ram.bss .ext_ram.bss.*)
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*libpython3.13.a:(*.PyRuntime)
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*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram.*)
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*(.wifiextrairam .wifiextrairam.*)
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*(EXCLUDE_FILE(*libpp.a) .wifiorslpiram EXCLUDE_FILE(*libpp.a) .wifiorslpiram.*)
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*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram.*)
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*(.wifislpiram .wifislpiram.*)
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*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram.*)
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/* CPU will try to prefetch up to 16 bytes of instructions.
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* This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += 16;
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_instruction_reserved_end = ABSOLUTE(.);
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_etext = .;
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} >irom0_0_seg AT>ROM
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. = ALIGN(4);
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_ext_ram_bss_end = ABSOLUTE(.);
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} > extern_ram_seg
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.rtc.text :
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{
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@ -184,6 +184,17 @@ MEMORY
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
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len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
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/* `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region.
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* A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `esp32s3_sections.ld
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*/
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#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
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extern_ram_seg(RWX) : org = 0x3c000000 + ORIGIN(ROM),
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len = 0x2000000 - ORIGIN(ROM)
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#else
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extern_ram_seg(RWX) : org = 0x3c000020 , len = 0x2000000-0x20
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#endif
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}
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#ifdef CONFIG_ESP32S3_RUN_IRAM
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