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fix nxstyle

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Removed extra spaces from .h and .c files
This commit is contained in:
simbit18 2024-11-28 11:56:04 +01:00 • committed by Xiang Xiao
parent 968bb179fe
commit 9c9b945876
36 changed files with 297 additions and 297 deletions
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2
arch/arm/include/at32/at32f43xxx_irq.h
View file

@ -116,7 +116,7 @@
#define AT32_IRQ_DMA1CH3 (AT32_IRQ_FIRST+58) /* 58: DMA1 Stream 3 global interrupt */
#define AT32_IRQ_DMA1CH4 (AT32_IRQ_FIRST+59) /* 59: DMA1 Stream 4 global interrupt */
#define AT32_IRQ_DMA1CH5 (AT32_IRQ_FIRST+60) /* 60: DMA1 Stream 5 global interrupt */
#if defined(CONFIG_AT32_AT32F437)
#if defined(CONFIG_AT32_AT32F437)
# define AT32_IRQ_ETH (AT32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
# define AT32_IRQ_ETHWKUP (AT32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#endif

2
arch/arm/include/stm32u5/stm32u5xx_irq.h
View file

@ -192,7 +192,7 @@
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_IRQ_NEXTINTS 125
#else
# error "Unsupported STM32U5 chip"

4
arch/arm/src/at32/at32_adc.c
View file

@ -97,7 +97,7 @@
/* RCC reset ****************************************************************/
#define AT32_RCC_RSTR AT32_CRM_APB2RST
#define AT32_RCC_RSTR AT32_CRM_APB2RST
#define RCC_RSTR_ADC123RST CRM_APB2RST_ADCRST
/* ADC Channels/DMA *********************************************************/
@ -142,7 +142,7 @@
/* Number of channels per ADC:
*/
#if defined(CONFIG_AT32_AT32F43XX)
#if defined(CONFIG_AT32_AT32F43XX)
# define ADC_CHANNELS_NUMBER 19
#else
# error "Not supported"

2
arch/arm/src/at32/at32_dma_v1mux.c
View file

@ -959,7 +959,7 @@ static void at32_dmamux_sample(DMA_MUX dmamux, uint8_t chan,
static void at32_dmamux_dump(DMA_MUX dmamux, uint8_t channel,
const struct at32_dmaregs_s *regs)
{
#if 0
#if 0
dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel);
dmainfo(" CCR[%08x]: %08x\n",
dmamux->base + AT32_DMAMUX_CXCR_OFFSET(channel),

2
arch/arm/src/at32/at32_pwm.c
View file

@ -94,7 +94,7 @@
# define TIMCLK_TIM1 AT32_APB2_TIM1_CLKIN
# define TIMRCCEN_TIM1 AT32_CRM_APB2EN
# define TIMEN_TIM1 CRM_APB2EN_TMR1EN
# define TIMEN_TIM1 CRM_APB2EN_TMR1EN
# define TIMRCCRST_TIM1 AT32_CRM_APB2RST
# define TIMRST_TIM1 CRM_APB2RST_TMR1RST

6
arch/arm/src/at32/at32_sdio.c
View file

@ -104,7 +104,7 @@
#ifdef CONFIG_AT32_SDIO_DMA
# ifndef CONFIG_AT32_SDIO_DMAPRIO
# if defined(CONFIG_AT32_AT32F43XX)
# define CONFIG_AT32_SDIO_DMAPRIO DMA_CCR_PRIMED
# define CONFIG_AT32_SDIO_DMAPRIO DMA_CCR_PRIMED
# else
# error "Unknown AT32 DMA"
# endif
@ -990,9 +990,9 @@ static void at32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
dctrl &= (SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE |
SDIO_DCTRL_DBLOCKSIZE_MASK);
#ifdef CONFIG_AT32_SDIO_CARD
#ifdef CONFIG_AT32_SDIO_CARD
regval |= (dctrl | SDIO_DCTRL_DTEN | SDIO_DCTRL_SDIOEN);
#else
#else
regval |= (dctrl | SDIO_DCTRL_DTEN);
#endif

4
arch/arm/src/at32/hardware/at32_dbgmcu.h
View file

@ -62,7 +62,7 @@
#define DEBUG_APB1_APUSE_TMR3_PAUSE (1 << 1)
#define DEBUG_APB1_APUSE_TMR4_PAUSE (1 << 2)
#define DEBUG_APB1_APUSE_TMR5_PAUSE (1 << 3)
#define DEBUG_APB1_APUSE_TMR6_PAUSE (1 << 4)
#define DEBUG_APB1_APUSE_TMR6_PAUSE (1 << 4)
#define DEBUG_APB1_APUSE_TMR7_PAUSE (1 << 5)
#define DEBUG_APB1_APUSE_TMR12_PAUSE (1 << 6)
#define DEBUG_APB1_APUSE_TMR13_PAUSE (1 << 7)
@ -92,7 +92,7 @@
# define DEBUG_SER_ID_F437 (0x0E << DEBUG_SER_ID_SHIFT)
#define DEBUG_REV_ID_SHIFT (0)
# define DEBUG_REV_ID (0 << DEBUG_REV_ID_SHIFT)
# define DEBUG_REV_ID (0 << DEBUG_REV_ID_SHIFT)
/****************************************************************************
* Public Types

46
arch/arm/src/at32/hardware/at32f43xxx_rcc.h
View file

@ -53,29 +53,29 @@
/* Register Addresses *******************************************************/
#define AT32_CRM_CTRL (AT32_CRM_BASE+AT32_CRM_CTRL_OFFSET)
#define AT32_CRM_PLL_CFG (AT32_CRM_BASE+AT32_CRM_PLL_CFG_OFFSET)
#define AT32_CRM_CFG (AT32_CRM_BASE+AT32_CRM_CFG_OFFSET)
#define AT32_CRM_CLKINT (AT32_CRM_BASE+AT32_CRM_CLKINT_OFFSET)
#define AT32_CRM_AHBRST1 (AT32_CRM_BASE+AT32_CRM_AHBRST1_OFFSET)
#define AT32_CRM_AHBRST2 (AT32_CRM_BASE+AT32_CRM_AHBRST2_OFFSET)
#define AT32_CRM_AHBRST3 (AT32_CRM_BASE+AT32_CRM_AHBRST3_OFFSET)
#define AT32_CRM_APB1RST (AT32_CRM_BASE+AT32_CRM_APB1RST_OFFSET)
#define AT32_CRM_APB2RST (AT32_CRM_BASE+AT32_CRM_APB2RST_OFFSET)
#define AT32_CRM_AHBEN1 (AT32_CRM_BASE+AT32_CRM_AHBEN1_OFFSET)
#define AT32_CRM_AHBEN2 (AT32_CRM_BASE+AT32_CRM_AHBEN2_OFFSET)
#define AT32_CRM_AHBEN3 (AT32_CRM_BASE+AT32_CRM_AHBEN3_OFFSET)
#define AT32_CRM_APB1EN (AT32_CRM_BASE+AT32_CRM_APB1EN_OFFSET)
#define AT32_CRM_APB2EN (AT32_CRM_BASE+AT32_CRM_APB2EN_OFFSET)
#define AT32_CRM_AHBLPEN1 (AT32_CRM_BASE+AT32_CRM_AHBLPEN1_OFFSET)
#define AT32_CRM_AHBLPEN2 (AT32_CRM_BASE+AT32_CRM_AHBLPEN2_OFFSET)
#define AT32_CRM_AHBLPEN3 (AT32_CRM_BASE+AT32_CRM_AHBLPEN3_OFFSET)
#define AT32_CRM_APB1LPEN (AT32_CRM_BASE+AT32_CRM_APB1LPEN_OFFSET)
#define AT32_CRM_APB2LPEN (AT32_CRM_BASE+AT32_CRM_APB2LPEN_OFFSET)
#define AT32_CRM_BPDC (AT32_CRM_BASE+AT32_CRM_BPDC_OFFSET)
#define AT32_CRM_CTRLSTS (AT32_CRM_BASE+AT32_CRM_CTRLSTS_OFFSET)
#define AT32_CRM_MISC1 (AT32_CRM_BASE+AT32_CRM_MISC1_OFFSET)
#define AT32_CRM_MISC2 (AT32_CRM_BASE+AT32_CRM_MISC2_OFFSET)
#define AT32_CRM_CTRL (AT32_CRM_BASE+AT32_CRM_CTRL_OFFSET)
#define AT32_CRM_PLL_CFG (AT32_CRM_BASE+AT32_CRM_PLL_CFG_OFFSET)
#define AT32_CRM_CFG (AT32_CRM_BASE+AT32_CRM_CFG_OFFSET)
#define AT32_CRM_CLKINT (AT32_CRM_BASE+AT32_CRM_CLKINT_OFFSET)
#define AT32_CRM_AHBRST1 (AT32_CRM_BASE+AT32_CRM_AHBRST1_OFFSET)
#define AT32_CRM_AHBRST2 (AT32_CRM_BASE+AT32_CRM_AHBRST2_OFFSET)
#define AT32_CRM_AHBRST3 (AT32_CRM_BASE+AT32_CRM_AHBRST3_OFFSET)
#define AT32_CRM_APB1RST (AT32_CRM_BASE+AT32_CRM_APB1RST_OFFSET)
#define AT32_CRM_APB2RST (AT32_CRM_BASE+AT32_CRM_APB2RST_OFFSET)
#define AT32_CRM_AHBEN1 (AT32_CRM_BASE+AT32_CRM_AHBEN1_OFFSET)
#define AT32_CRM_AHBEN2 (AT32_CRM_BASE+AT32_CRM_AHBEN2_OFFSET)
#define AT32_CRM_AHBEN3 (AT32_CRM_BASE+AT32_CRM_AHBEN3_OFFSET)
#define AT32_CRM_APB1EN (AT32_CRM_BASE+AT32_CRM_APB1EN_OFFSET)
#define AT32_CRM_APB2EN (AT32_CRM_BASE+AT32_CRM_APB2EN_OFFSET)
#define AT32_CRM_AHBLPEN1 (AT32_CRM_BASE+AT32_CRM_AHBLPEN1_OFFSET)
#define AT32_CRM_AHBLPEN2 (AT32_CRM_BASE+AT32_CRM_AHBLPEN2_OFFSET)
#define AT32_CRM_AHBLPEN3 (AT32_CRM_BASE+AT32_CRM_AHBLPEN3_OFFSET)
#define AT32_CRM_APB1LPEN (AT32_CRM_BASE+AT32_CRM_APB1LPEN_OFFSET)
#define AT32_CRM_APB2LPEN (AT32_CRM_BASE+AT32_CRM_APB2LPEN_OFFSET)
#define AT32_CRM_BPDC (AT32_CRM_BASE+AT32_CRM_BPDC_OFFSET)
#define AT32_CRM_CTRLSTS (AT32_CRM_BASE+AT32_CRM_CTRLSTS_OFFSET)
#define AT32_CRM_MISC1 (AT32_CRM_BASE+AT32_CRM_MISC1_OFFSET)
#define AT32_CRM_MISC2 (AT32_CRM_BASE+AT32_CRM_MISC2_OFFSET)
/* Register Bitfield Definitions ********************************************/

2
arch/arm/src/at32/hardware/at32fxxxxx_otgfs.h
View file

@ -555,7 +555,7 @@
#define OTGFS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */
#define OTGFS_GUSBCFG_TRDT_MASK (15 << OTGFS_GUSBCFG_TRDT_SHIFT)
# define OTGFS_GUSBCFG_TRDT(n) ((n) << OTGFS_GUSBCFG_TRDT_SHIFT)
# define OTGFS_GUSBCFG_TRDT(n) ((n) << OTGFS_GUSBCFG_TRDT_SHIFT)
#define OTGFS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */
#define OTGFS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */

2
arch/arm/src/csk6/csk6_lowputc.c
View file

@ -234,7 +234,7 @@ void csk6_lowsetup(void)
CSK6_UART0_BASE + 0x0c);
#endif
#if (CSK6_CONSOLE_NBITS == 5)
#if (CSK6_CONSOLE_NBITS == 5)
modreg32(REG_VALUE_SHIFT(0x00, 0),
REG_FIELD_MASK(2, 0),
CSK6_UART0_BASE + 0x0c);

2
arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h
View file

@ -257,7 +257,7 @@
#define CCM_CG_CTRL_RSTDIV_SHIFT (16) /* Bits 16-23: Clock group global restart count (RSTDIV) */
#define CCM_CG_CTRL_RSTDIV_MASK (0xff << CCM_CG_CTRL_RSTDIV_SHIFT)
# define CCM_CG_CTRL_RSTDIV(n) (((n)-1) << CCM_CG_CTRL_RSTDIV_SHIFT) /* Divide selected clock by n */
#define CCM_CG_CTRL_OFF (1 << 24)
#define CCM_CG_CTRL_OFF (1 << 24)
/* Bit 24: Shutdown all clocks in clock group (OFF) */
/* Bits 25-31: Reserved */

104
arch/arm/src/rp23xx/hardware/rp23xx_intctrl.h
View file

@ -31,58 +31,58 @@
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_TIMER0_IRQ_0 0
#define RP23XX_TIMER0_IRQ_1 1
#define RP23XX_TIMER0_IRQ_2 2
#define RP23XX_TIMER0_IRQ_3 3
#define RP23XX_TIMER1_IRQ_0 4
#define RP23XX_TIMER1_IRQ_1 5
#define RP23XX_TIMER1_IRQ_2 6
#define RP23XX_TIMER1_IRQ_3 7
#define RP23XX_PWM_IRQ_WRAP_0 8
#define RP23XX_PWM_IRQ_WRAP_1 9
#define RP23XX_DMA_IRQ_0 10
#define RP23XX_DMA_IRQ_1 11
#define RP23XX_DMA_IRQ_2 12
#define RP23XX_DMA_IRQ_3 13
#define RP23XX_USBCTRL_IRQ 14
#define RP23XX_PIO0_IRQ_0 15
#define RP23XX_PIO0_IRQ_1 16
#define RP23XX_PIO1_IRQ_0 17
#define RP23XX_PIO1_IRQ_1 18
#define RP23XX_PIO2_IRQ_0 19
#define RP23XX_PIO2_IRQ_1 20
#define RP23XX_IO_IRQ_BANK0 21
#define RP23XX_IO_IRQ_BANK0_NS 22
#define RP23XX_IO_IRQ_QSPI 23
#define RP23XX_IO_IRQ_QSPI_NS 24
#define RP23XX_SIO_IRQ_FIFO 25
#define RP23XX_SIO_IRQ_BELL 26
#define RP23XX_SIO_IRQ_FIFO_NS 27
#define RP23XX_SIO_IRQ_BELL_NS 28
#define RP23XX_SIO_IRQ_MTIMECMP 29
#define RP23XX_CLOCKS_IRQ 30
#define RP23XX_SPI0_IRQ 31
#define RP23XX_SPI1_IRQ 32
#define RP23XX_UART0_IRQ 33
#define RP23XX_UART1_IRQ 34
#define RP23XX_ADC_IRQ_FIFO 35
#define RP23XX_I2C0_IRQ 36
#define RP23XX_I2C1_IRQ 37
#define RP23XX_OTP_IRQ 38
#define RP23XX_TRNG_IRQ 39
#define RP23XX_PROC0_IRQ_CTI 40
#define RP23XX_PROC1_IRQ_CTI 41
#define RP23XX_PLL_SYS_IRQ 42
#define RP23XX_PLL_USB_IRQ 43
#define RP23XX_POWMAN_IRQ_POW 44
#define RP23XX_POWMAN_IRQ_TIMER 45
#define RP23XX_SPARE_IRQ_0 46
#define RP23XX_SPARE_IRQ_1 47
#define RP23XX_SPARE_IRQ_2 48
#define RP23XX_SPARE_IRQ_3 49
#define RP23XX_SPARE_IRQ_4 50
#define RP23XX_SPARE_IRQ_5 51
#define RP23XX_TIMER0_IRQ_0 0
#define RP23XX_TIMER0_IRQ_1 1
#define RP23XX_TIMER0_IRQ_2 2
#define RP23XX_TIMER0_IRQ_3 3
#define RP23XX_TIMER1_IRQ_0 4
#define RP23XX_TIMER1_IRQ_1 5
#define RP23XX_TIMER1_IRQ_2 6
#define RP23XX_TIMER1_IRQ_3 7
#define RP23XX_PWM_IRQ_WRAP_0 8
#define RP23XX_PWM_IRQ_WRAP_1 9
#define RP23XX_DMA_IRQ_0 10
#define RP23XX_DMA_IRQ_1 11
#define RP23XX_DMA_IRQ_2 12
#define RP23XX_DMA_IRQ_3 13
#define RP23XX_USBCTRL_IRQ 14
#define RP23XX_PIO0_IRQ_0 15
#define RP23XX_PIO0_IRQ_1 16
#define RP23XX_PIO1_IRQ_0 17
#define RP23XX_PIO1_IRQ_1 18
#define RP23XX_PIO2_IRQ_0 19
#define RP23XX_PIO2_IRQ_1 20
#define RP23XX_IO_IRQ_BANK0 21
#define RP23XX_IO_IRQ_BANK0_NS 22
#define RP23XX_IO_IRQ_QSPI 23
#define RP23XX_IO_IRQ_QSPI_NS 24
#define RP23XX_SIO_IRQ_FIFO 25
#define RP23XX_SIO_IRQ_BELL 26
#define RP23XX_SIO_IRQ_FIFO_NS 27
#define RP23XX_SIO_IRQ_BELL_NS 28
#define RP23XX_SIO_IRQ_MTIMECMP 29
#define RP23XX_CLOCKS_IRQ 30
#define RP23XX_SPI0_IRQ 31
#define RP23XX_SPI1_IRQ 32
#define RP23XX_UART0_IRQ 33
#define RP23XX_UART1_IRQ 34
#define RP23XX_ADC_IRQ_FIFO 35
#define RP23XX_I2C0_IRQ 36
#define RP23XX_I2C1_IRQ 37
#define RP23XX_OTP_IRQ 38
#define RP23XX_TRNG_IRQ 39
#define RP23XX_PROC0_IRQ_CTI 40
#define RP23XX_PROC1_IRQ_CTI 41
#define RP23XX_PLL_SYS_IRQ 42
#define RP23XX_PLL_USB_IRQ 43
#define RP23XX_POWMAN_IRQ_POW 44
#define RP23XX_POWMAN_IRQ_TIMER 45
#define RP23XX_SPARE_IRQ_0 46
#define RP23XX_SPARE_IRQ_1 47
#define RP23XX_SPARE_IRQ_2 48
#define RP23XX_SPARE_IRQ_3 49
#define RP23XX_SPARE_IRQ_4 50
#define RP23XX_SPARE_IRQ_5 51
#define RP23XX_IRQ_COUNT 52
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_INTCTRL_H */

22
arch/arm/src/sama5/hardware/sam_classd.h
View file

@ -76,15 +76,15 @@
/* ClassD Register Addresses */
#define SAM_CLASSD_CR (SAM_CLASSD_VBASE + SAM_CLASSD_CR_OFFSET)
#define SAM_CLASSD_MR (SAM_CLASSD_VBASE + SAM_CLASSD_MR_OFFSET)
#define SAM_CLASSD_INTPMR (SAM_CLASSD_VBASE + SAM_CLASSD_INTPMR_OFFSET)
#define SAM_CLASSD_INTSR (SAM_CLASSD_VBASE + SAM_CLASSD_INTSR_OFFSET)
#define SAM_CLASSD_THR (SAM_CLASSD_VBASE + SAM_CLASSD_THR_OFFSET)
#define SAM_CLASSD_IER (SAM_CLASSD_VBASE + SAM_CLASSD_IER_OFFSET)
#define SAM_CLASSD_IDR (SAM_CLASSD_VBASE + SAM_CLASSD_IDR_OFFSET)
#define SAM_CLASSD_IMR (SAM_CLASSD_VBASE + SAM_CLASSD_IMR_OFFSET)
#define SAM_CLASSD_ISR (SAM_CLASSD_VBASE + SAM_CLASSD_ISR_OFFSET)
#define SAM_CLASSD_WPMR (SAM_CLASSD_VBASE + SAM_CLASSD_WPMR_OFFSET)
#define SAM_CLASSD_MR (SAM_CLASSD_VBASE + SAM_CLASSD_MR_OFFSET)
#define SAM_CLASSD_INTPMR (SAM_CLASSD_VBASE + SAM_CLASSD_INTPMR_OFFSET)
#define SAM_CLASSD_INTSR (SAM_CLASSD_VBASE + SAM_CLASSD_INTSR_OFFSET)
#define SAM_CLASSD_THR (SAM_CLASSD_VBASE + SAM_CLASSD_THR_OFFSET)
#define SAM_CLASSD_IER (SAM_CLASSD_VBASE + SAM_CLASSD_IER_OFFSET)
#define SAM_CLASSD_IDR (SAM_CLASSD_VBASE + SAM_CLASSD_IDR_OFFSET)
#define SAM_CLASSD_IMR (SAM_CLASSD_VBASE + SAM_CLASSD_IMR_OFFSET)
#define SAM_CLASSD_ISR (SAM_CLASSD_VBASE + SAM_CLASSD_ISR_OFFSET)
#define SAM_CLASSD_WPMR (SAM_CLASSD_VBASE + SAM_CLASSD_WPMR_OFFSET)
/* ClassD Register Bit Field Definitions */
@ -103,7 +103,7 @@
#define CLASSD_MR_PWMTYP_BIT (1 << CLASSD_MR_PWMTYP_SHIFT)
/* Bit 8, PWM Modulation Type */
#define CLASSD_MR_NOVR_SHIFT (16) /* Bit 16, Non-Overlapping Enable */
#define CLASSD_MR_NOVR_BIT (1 << CLASSD_MR_NOVR_SHIFT)
#define CLASSD_MR_NOVR_BIT (1 << CLASSD_MR_NOVR_SHIFT)
#define CLASSD_MR_NOVRVAL_SHIFT (20) /* Bit 20/21, Non-Overlap Value */
#define CLASSD_MR_NOVRVAL_MASK (3 << CLASSD_MR_NOVRVAL_SHIFT)
#define CLASSD_MR_NOVR(n) ((n) << CLASSD_MR_NOVRVAL_SHIFT)
@ -117,7 +117,7 @@
#define CLASSD_VOL_RIGHT(n) ((n) << CLASSD_INTPMR_ATTR_SHIFT)
#define CLASSD_INTPMR_DSPCLKF_SHIFT (16) /* Bit 16, DSP Clock Frequency */
#define CLASSD_INTPMR_DSPCLKF_BIT (1 << CLASSD_INTPMR_DSPCLKF_SHIFT)
#define CLASSD_INTPMR_DSPCLKF_BIT (1 << CLASSD_INTPMR_DSPCLKF_SHIFT)
#define CLASSD_INTPMR_DEEMP_SHIFT (18) /* Bit 18, Enable De-emph. filter */
#define CLASSD_INTPMR_DEEMP_BIT (1 << CLASSD_INTPMR_DEEMP_SHIFT)
#define CLASSD_INTPMR_SWAP_SHIFT (19) /* Bit 19, Swap L&R Channels */

6
arch/arm/src/sama5/sam_classd.c
View file

@ -335,7 +335,7 @@ static void classd_putreg(uint32_t regaddr, uint32_t regval);
static void classd_dump_registers(const char *msg);
#else
# define classd_dump_registers(msg);
#endif
#endif
/* Audio lower half functions */
@ -501,9 +501,9 @@ static struct sam_classd_config_s sam_classd_const =
#if defined(CONFIG_SAMA5D2_CLASSD_EQ_FLAT)
.eq_mode = CLASSD_EQ_FLAT,
# elif defined(CONFIG_SAMA5D2_CLASSD_EQ_BB12)
# elif defined(CONFIG_SAMA5D2_CLASSD_EQ_BB12)
.eq_mode = CLASSD_EQ_BASS_BOOST_12DB,
# elif defined(CONFIG_SAMA5D2_CLASSD_EQ_BB6)
# elif defined(CONFIG_SAMA5D2_CLASSD_EQ_BB6)
.eq_mode = CLASSD_EQ_BASS_BOOST_6DB,
# elif defined(CONFIG_SAMA5D2_CLASSD_EQ_BC12)
.eq_mode = CLASSD_EQ_BASS_CUT_12DB,

4
arch/arm/src/sama5/sam_spi.c
View file

@ -1556,7 +1556,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
rxflags = DMACH_FLAG_FIFOCFG_LARGEST | DMACH_FLAG_PERIPHPID(spi->pid) |
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH |
#ifdef ATSAMA5D2
#ifdef ATSAMA5D2
DMACH_FLAG_PERIPHAHB_AHB_IF1 | DMACH_FLAG_PERIPHWIDTH_8BITS |
#else
DMACH_FLAG_PERIPHAHB_AHB_IF2 | DMACH_FLAG_PERIPHWIDTH_8BITS |
@ -1582,7 +1582,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
txflags = DMACH_FLAG_FIFOCFG_LARGEST | DMACH_FLAG_PERIPHPID(spi->pid) |
DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH |
#ifdef ATSAMA5D2
#ifdef ATSAMA5D2
DMACH_FLAG_PERIPHAHB_AHB_IF1 | DMACH_FLAG_PERIPHWIDTH_8BITS |
#else
DMACH_FLAG_PERIPHAHB_AHB_IF2 | DMACH_FLAG_PERIPHWIDTH_8BITS |

4
arch/arm/src/sama5/sam_tsd.c
View file

@ -525,7 +525,7 @@ static void sam_tsd_bottomhalf(void *arg)
uint32_t yscale;
uint32_t y;
uint32_t ydiff;
#ifdef CONFIG_SAMA5_TSD_4WIRE
#ifdef CONFIG_SAMA5_TSD_4WIRE
uint32_t z1;
uint32_t z2;
uint32_t pressr;
@ -570,7 +570,7 @@ static void sam_tsd_bottomhalf(void *arg)
ier = ADC_INT_PEN;
#else
ier = ADC_TSD_PRESSINTS;
#endif
#endif
/* Ignore the interrupt if the pen was already up (CONTACT_NONE == pen
* up and already reported; CONTACT_UP == pen up, but not reported)

54
arch/arm/src/stm32h5/hardware/stm32_adc.h
View file

@ -100,20 +100,20 @@
#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET)
#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET)
#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET)
#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET)
#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET)
#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET)
#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET)
#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET)
#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET)
#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET)
#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET)
#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET)
#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET)
#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET)
#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET)
#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET)
@ -138,20 +138,20 @@
#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET)
#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET)
#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET)
#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET)
#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET)
#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET)
#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET)
#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET)
#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET)
#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET)
#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET)
#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET)
#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET)
#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET)
#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET)
#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET)
@ -322,7 +322,7 @@
#define ADC_SMPR1_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
#define ADC_SMPR1_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT)
#define ADC_SMPR1_SMPPLUS (1 << 31) /* Addition of one clock cycle to the sampling time */
#define ADC_SMPR1_SMPPLUS (1 << 31) /* Addition of one clock cycle to the sampling time */
/* ADC sample time register 2 */

112
arch/arm/src/stm32h5/hardware/stm32_dbgmcu.h
View file

@ -141,92 +141,92 @@
/* Debug MCU Status Register */
#define DBGMCU_SR_AP_PRESENT_SHIFT (0)
#define DBGMCU_SR_AP_PRESENT_MASK (0xffff << DBGMCU_SR_AP_PRESENT_SHIFT)
#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_MASK
#define DBGMCU_SR_AP_PRESENT_SHIFT (0)
#define DBGMCU_SR_AP_PRESENT_MASK (0xffff << DBGMCU_SR_AP_PRESENT_SHIFT)
#define DBGMCU_SR_AP_PRESENT DBGMCU_SR_AP_PRESENT_MASK
#define DBGMCU_SR_AP_ENABLED_SHIFT (16)
#define DBGMCU_SR_AP_ENABLED_MASK (0xffff << DBGMCU_SR_AP_ENABLED_SHIFT)
#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_MASK
#define DBGMCU_SR_AP_ENABLED_MASK (0xffff << DBGMCU_SR_AP_ENABLED_SHIFT)
#define DBGMCU_SR_AP_ENABLED DBGMCU_SR_AP_ENABLED_MASK
/* Debug MCU Authorization Acknowledge Register */
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_SHIFT (0)
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_MASK (1 << DBGMCU_DBG_AUTH_ACK_HOST_ACK_SHIFT)
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_MASK
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_SHIFT (1)
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_MASK (1 << DBGMCU_DBG_AUTH_ACK_DEV_ACK_SHIFT)
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK DBGMCU_DBG_AUTH_ACK_DEV_ACK_MASK
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_SHIFT (0)
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_MASK (1 << DBGMCU_DBG_AUTH_ACK_HOST_ACK_SHIFT)
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_MASK
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_SHIFT (1)
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK_MASK (1 << DBGMCU_DBG_AUTH_ACK_DEV_ACK_SHIFT)
#define DBGMCU_DBG_AUTH_ACK_DEV_ACK DBGMCU_DBG_AUTH_ACK_DEV_ACK_MASK
/* Debug MCU CoreSight Peripheral Identity Register 4 */
#define DBGMCU_PIDR4_JEP106CON_SHIFT (0)
#define DBGMCU_PIDR4_JEP106CON_MASK (0xf << DBGMCU_PIDR4_JEP106CON_SHIFT)
#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_MASK
#define DBGMCU_PIDR4_SIZE_SHIFT (0)
#define DBGMCU_PIDR4_SIZE_MASK (0xf << DBGMCU_PIDR4_SIZE_SHIFT)
#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_MASK
#define DBGMCU_PIDR4_JEP106CON_SHIFT (0)
#define DBGMCU_PIDR4_JEP106CON_MASK (0xf << DBGMCU_PIDR4_JEP106CON_SHIFT)
#define DBGMCU_PIDR4_JEP106CON DBGMCU_PIDR4_JEP106CON_MASK
#define DBGMCU_PIDR4_SIZE_SHIFT (0)
#define DBGMCU_PIDR4_SIZE_MASK (0xf << DBGMCU_PIDR4_SIZE_SHIFT)
#define DBGMCU_PIDR4_SIZE DBGMCU_PIDR4_SIZE_MASK
/* Debug MCU CoreSight Peripheral Identity Register 0 */
#define DBGMCU_PIDR0_PARTNUM_SHIFT (0)
#define DBGMCU_PIDR0_PARTNUM_MASK (0xff << DBGMCU_PIDR0_PARTNUM_SHIFT)
#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_MASK
#define DBGMCU_PIDR0_PARTNUM_SHIFT (0)
#define DBGMCU_PIDR0_PARTNUM_MASK (0xff << DBGMCU_PIDR0_PARTNUM_SHIFT)
#define DBGMCU_PIDR0_PARTNUM DBGMCU_PIDR0_PARTNUM_MASK
/* Debug MCU CoreSight Peripheral Identity Register 1 */
#define DBGMCU_PIDR1_PARTNUM_SHIFT (0)
#define DBGMCU_PIDR1_PARTNUM_MASK (0xf << DBGMCU_PIDR1_PARTNUM_SHIFT)
#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_MASK
#define DBGMCU_PIDR1_JEP106ID_SHIFT (4)
#define DBGMCU_PIDR1_JEP106ID_MASK (0xf << DBGMCU_PIDR1_JEP106ID_SHIFT)
#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_MASK
#define DBGMCU_PIDR1_PARTNUM_SHIFT (0)
#define DBGMCU_PIDR1_PARTNUM_MASK (0xf << DBGMCU_PIDR1_PARTNUM_SHIFT)
#define DBGMCU_PIDR1_PARTNUM DBGMCU_PIDR1_PARTNUM_MASK
#define DBGMCU_PIDR1_JEP106ID_SHIFT (4)
#define DBGMCU_PIDR1_JEP106ID_MASK (0xf << DBGMCU_PIDR1_JEP106ID_SHIFT)
#define DBGMCU_PIDR1_JEP106ID DBGMCU_PIDR1_JEP106ID_MASK
/* Debug MCU CoreSight Peripheral Identity Register 2 */
#define DBGMCU_PIDR2_JEP106ID_SHIFT (0)
#define DBGMCU_PIDR2_JEP106ID_MASK (0x7 << DBGMCU_PIDR2_JEP106ID_SHIFT)
#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_MASK
#define DBGMCU_PIDR2_JEDEC_SHIFT (3)
#define DBGMCU_PIDR2_JEDEC_MASK (0x1 << DBGMCU_PIDR2_JEDEC_SHIFT)
#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_MASK
#define DBGMCU_PIDR2_REVISION_SHIFT (4)
#define DBGMCU_PIDR2_REVISION_MASK (0xf << DBGMCU_PIDR2_REVISION_SHIFT)
#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_MASK
#define DBGMCU_PIDR2_JEP106ID_SHIFT (0)
#define DBGMCU_PIDR2_JEP106ID_MASK (0x7 << DBGMCU_PIDR2_JEP106ID_SHIFT)
#define DBGMCU_PIDR2_JEP106ID DBGMCU_PIDR2_JEP106ID_MASK
#define DBGMCU_PIDR2_JEDEC_SHIFT (3)
#define DBGMCU_PIDR2_JEDEC_MASK (0x1 << DBGMCU_PIDR2_JEDEC_SHIFT)
#define DBGMCU_PIDR2_JEDEC DBGMCU_PIDR2_JEDEC_MASK
#define DBGMCU_PIDR2_REVISION_SHIFT (4)
#define DBGMCU_PIDR2_REVISION_MASK (0xf << DBGMCU_PIDR2_REVISION_SHIFT)
#define DBGMCU_PIDR2_REVISION DBGMCU_PIDR2_REVISION_MASK
/* Debug MCU CoreSight Peripheral Identity Register 3 */
#define DBGMCU_PIDR3_CMOD_SHIFT (0)
#define DBGMCU_PIDR3_CMOD_MASK (0xf << DBGMCU_PIDR3_CMOD_SHIFT)
#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_MASK
#define DBGMCU_PIDR3_REVAND_SHIFT (4)
#define DBGMCU_PIDR3_REVAND_MASK (0xf << DBGMCU_PIDR3_REVAND_SHIFT)
#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_MASK
#define DBGMCU_PIDR3_CMOD_SHIFT (0)
#define DBGMCU_PIDR3_CMOD_MASK (0xf << DBGMCU_PIDR3_CMOD_SHIFT)
#define DBGMCU_PIDR3_CMOD DBGMCU_PIDR3_CMOD_MASK
#define DBGMCU_PIDR3_REVAND_SHIFT (4)
#define DBGMCU_PIDR3_REVAND_MASK (0xf << DBGMCU_PIDR3_REVAND_SHIFT)
#define DBGMCU_PIDR3_REVAND DBGMCU_PIDR3_REVAND_MASK
/* Debug MCU CoreSight Component Identity Register 0 */
#define DBGMCU_CIDR0_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR0_PREAMBLE_MASK (0xff << DBGMCU_CIDR0_PREAMBLE_SHIFT)
#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_MASK
#define DBGMCU_CIDR0_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR0_PREAMBLE_MASK (0xff << DBGMCU_CIDR0_PREAMBLE_SHIFT)
#define DBGMCU_CIDR0_PREAMBLE DBGMCU_CIDR0_PREAMBLE_MASK
/* Debug MCU CoreSight Component Identity Register 1 */
#define DBGMCU_CIDR1_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR1_PREAMBLE_MASK (0xf << DBGMCU_CIDR1_PREAMBLE_SHIFT)
#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_MASK
#define DBGMCU_CIDR1_CLASS_SHIFT (4)
#define DBGMCU_CIDR1_CLASS_MASK (0xf << DBGMCU_CIDR1_CLASS_SHIFT)
#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_MASK
#define DBGMCU_CIDR1_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR1_PREAMBLE_MASK (0xf << DBGMCU_CIDR1_PREAMBLE_SHIFT)
#define DBGMCU_CIDR1_PREAMBLE DBGMCU_CIDR1_PREAMBLE_MASK
#define DBGMCU_CIDR1_CLASS_SHIFT (4)
#define DBGMCU_CIDR1_CLASS_MASK (0xf << DBGMCU_CIDR1_CLASS_SHIFT)
#define DBGMCU_CIDR1_CLASS DBGMCU_CIDR1_CLASS_MASK
/* Debug MCU CoreSight Component Identity Register 2 */
#define DBGMCU_CIDR2_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR2_PREAMBLE_MASK (0xff << DBGMCU_CIDR2_PREAMBLE_SHIFT)
#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_MASK
#define DBGMCU_CIDR2_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR2_PREAMBLE_MASK (0xff << DBGMCU_CIDR2_PREAMBLE_SHIFT)
#define DBGMCU_CIDR2_PREAMBLE DBGMCU_CIDR2_PREAMBLE_MASK
/* Debug MCU CoreSight Component Identity Register 3 */
#define DBGMCU_CIDR3_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR3_PREAMBLE_MASK (0xff << DBGMCU_CIDR3_PREAMBLE_SHIFT)
#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_MASK
#define DBGMCU_CIDR3_PREAMBLE_SHIFT (0)
#define DBGMCU_CIDR3_PREAMBLE_MASK (0xff << DBGMCU_CIDR3_PREAMBLE_SHIFT)
#define DBGMCU_CIDR3_PREAMBLE DBGMCU_CIDR3_PREAMBLE_MASK
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_DBGMCU_H */

2
arch/arm/src/stm32h5/hardware/stm32_sbs.h
View file

@ -41,7 +41,7 @@
/* Register Offsets *********************************************************/
#define STM32_SBS_HDPLCR_OFFSET 0x0010
#define STM32_SBS_HDPLCR_OFFSET 0x0010
#define STM32_SBS_HPDLSR_OFFSET 0x0014
#define STM32_SBS_NEXTHDPLCR_OFFSET 0x0018
#define STM32_SBS_DBGCR_OFFSET 0x0020

6
arch/arm/src/stm32h5/hardware/stm32_tim.h
View file

@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_TIM_H
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_TIM_H
/****************************************************************************
* Included Files
@ -502,7 +502,7 @@
# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
#define ATIM_SMCR_TS43_SHIFT (20)
#define ATIM_SMCR_TS43_SHIFT (20)
#define ATIM_SMCR_TS43_MASK (3 << ATIM_SMCR_TS43_SHIFT) /* Trigger selection bits 4:3. */
#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */

136
arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h
View file

@ -168,73 +168,73 @@
/* Register Addresses *******************************************************/
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_NSKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSKEYR_OFFSET)
#define STM32_FLASH_SECKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECKEYR_OFFSET)
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
#define STM32_FLASH_NSOBKKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSOBKKEYR_OFFSET)
#define STM32_FLASH_SECOBKKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECOBKKEYR_OFFSET)
#define STM32_FLASH_OPSR (STM32_FLASHIF_BASE + STM32_FLASH_OPSR_OFFSET)
#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE + STM32_FLASH_OPTCR_OFFSET)
#define STM32_FLASH_NSSR (STM32_FLASHIF_BASE + STM32_FLASH_NSSR_OFFSET)
#define STM32_FLASH_SECSR (STM32_FLASHIF_BASE + STM32_FLASH_SECSR_OFFSET)
#define STM32_FLASH_NSCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCR_OFFSET)
#define STM32_FLASH_SECCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCR_OFFSET)
#define STM32_FLASH_NSCCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCCR_OFFSET)
#define STM32_FLASH_SECCCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCCR_OFFSET)
#define STM32_FLASH_PRIVCFGR (STM32_FLASHIF_BASE + STM32_FLASH_PRIVCFGR_OFFSET)
#define STM32_FLASH_NSOBKCFGR (STM32_FLASHIF_BASE + STM32_FLASH_NSOBKCFGR_OFFSET)
#define STM32_FLASH_SECOBKCFGR (STM32_FLASHIF_BASE + STM32_FLASH_SECOBKCFGR_OFFSET)
#define STM32_FLASH_HDPEXTR (STM32_FLASHIF_BASE + STM32_FLASH_HDPEXTR_OFFSET)
#define STM32_FLASH_OPTSR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_CUR_OFFSET)
#define STM32_FLASH_OPTSR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_PRG_OFFSET)
#define STM32_FLASH_NSEPOCHR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_NSEPOCHR_CUR_OFFSET)
#define STM32_FLASH_NSEPOCHR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_NSEPOCHR_PRG_OFFSET)
#define STM32_FLASH_SECEPOCHR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECEPOCHR_CUR_OFFSET)
#define STM32_FLASH_SECEPOCHR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECEPOCHR_PRG_OFFSET)
#define STM32_FLASH_OPTSR2_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR2_CUR_OFFSET)
#define STM32_FLASH_OPTSR2_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR2_PRG_OFFSET)
#define STM32_FLASH_NSBOOTR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTR_CUR_OFFSET)
#define STM32_FLASH_NSBOOTR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTR_PRG_OFFSET)
#define STM32_FLASH_SECBOOTR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTR_CUR_OFFSET)
#define STM32_FLASH_SECBOOTR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTR_PRG_OFFSET)
#define STM32_FLASH_OTBPBLR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OTBPBLR_CUR_OFFSET)
#define STM32_FLASH_OTBPBLR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OTBPBLR_PRG_OFFSET)
#define STM32_FLASH_SECBB1R_1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_1_OFFSET)
#define STM32_FLASH_SECBB1R_2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_2_OFFSET)
#define STM32_FLASH_SECBB1R_3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_3_OFFSET)
#define STM32_FLASH_SECBB1R_4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_4_OFFSET)
#define STM32_FLASH_PRIVBB1R_1 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_1_OFFSET)
#define STM32_FLASH_PRIVBB1R_2 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_2_OFFSET)
#define STM32_FLASH_PRIVBB1R_3 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_3_OFFSET)
#define STM32_FLASH_PRIVBB1R_4 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_4_OFFSET)
#define STM32_FLASH_SECWM1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R_CUR_OFFSET)
#define STM32_FLASH_SECWM1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R_PRG_OFFSET)
#define STM32_FLASH_WRP1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1R_CUR_OFFSET)
#define STM32_FLASH_WRP1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_WRP1R_PRG_OFFSET)
#define STM32_FLASH_EDATA1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_EDATA1R_CUR_OFFSET)
#define STM32_FLASH_EDATA1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_EDATA1R_PRG_OFFSET)
#define STM32_FLASH_HDP1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_HDP1R_CUR_OFFSET)
#define STM32_FLASH_HDP1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_HDP1R_PRG_OFFSET)
#define STM32_FLASH_ECCCORR (STM32_FLASHIF_BASE + STM32_FLASH_ECCCORR_OFFSET)
#define STM32_FLASH_ECCDETR (STM32_FLASHIF_BASE + STM32_FLASH_ECCDETR_OFFSET)
#define STM32_FLASH_ECCDR (STM32_FLASHIF_BASE + STM32_FLASH_ECCDR_OFFSET)
#define STM32_FLASH_SECBB2R_1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_1_OFFSET)
#define STM32_FLASH_SECBB2R_2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_2_OFFSET)
#define STM32_FLASH_SECBB2R_3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_3_OFFSET)
#define STM32_FLASH_SECBB2R_4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_4_OFFSET)
#define STM32_FLASH_PRIVBB2R_1 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_1_OFFSET)
#define STM32_FLASH_PRIVBB2R_2 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_2_OFFSET)
#define STM32_FLASH_PRIVBB2R_3 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_3_OFFSET)
#define STM32_FLASH_PRIVBB2R_4 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_4_OFFSET)
#define STM32_FLASH_SECWM2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R_CUR_OFFSET)
#define STM32_FLASH_SECWM2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R_PRG_OFFSET)
#define STM32_FLASH_WRP2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2R_CUR_OFFSET)
#define STM32_FLASH_WRP2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_WRP2R_PRG_OFFSET)
#define STM32_FLASH_EDATA2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_EDATA2R_CUR_OFFSET)
#define STM32_FLASH_EDATA2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_EDATA2R_PRG_OFFSET)
#define STM32_FLASH_HDP2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_HDP2R_CUR_OFFSET)
#define STM32_FLASH_HDP2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_HDP2R_PRG_OFFSET)
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_NSKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSKEYR_OFFSET)
#define STM32_FLASH_SECKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECKEYR_OFFSET)
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
#define STM32_FLASH_NSOBKKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSOBKKEYR_OFFSET)
#define STM32_FLASH_SECOBKKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECOBKKEYR_OFFSET)
#define STM32_FLASH_OPSR (STM32_FLASHIF_BASE + STM32_FLASH_OPSR_OFFSET)
#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE + STM32_FLASH_OPTCR_OFFSET)
#define STM32_FLASH_NSSR (STM32_FLASHIF_BASE + STM32_FLASH_NSSR_OFFSET)
#define STM32_FLASH_SECSR (STM32_FLASHIF_BASE + STM32_FLASH_SECSR_OFFSET)
#define STM32_FLASH_NSCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCR_OFFSET)
#define STM32_FLASH_SECCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCR_OFFSET)
#define STM32_FLASH_NSCCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCCR_OFFSET)
#define STM32_FLASH_SECCCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCCR_OFFSET)
#define STM32_FLASH_PRIVCFGR (STM32_FLASHIF_BASE + STM32_FLASH_PRIVCFGR_OFFSET)
#define STM32_FLASH_NSOBKCFGR (STM32_FLASHIF_BASE + STM32_FLASH_NSOBKCFGR_OFFSET)
#define STM32_FLASH_SECOBKCFGR (STM32_FLASHIF_BASE + STM32_FLASH_SECOBKCFGR_OFFSET)
#define STM32_FLASH_HDPEXTR (STM32_FLASHIF_BASE + STM32_FLASH_HDPEXTR_OFFSET)
#define STM32_FLASH_OPTSR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_CUR_OFFSET)
#define STM32_FLASH_OPTSR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_PRG_OFFSET)
#define STM32_FLASH_NSEPOCHR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_NSEPOCHR_CUR_OFFSET)
#define STM32_FLASH_NSEPOCHR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_NSEPOCHR_PRG_OFFSET)
#define STM32_FLASH_SECEPOCHR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECEPOCHR_CUR_OFFSET)
#define STM32_FLASH_SECEPOCHR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECEPOCHR_PRG_OFFSET)
#define STM32_FLASH_OPTSR2_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR2_CUR_OFFSET)
#define STM32_FLASH_OPTSR2_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR2_PRG_OFFSET)
#define STM32_FLASH_NSBOOTR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTR_CUR_OFFSET)
#define STM32_FLASH_NSBOOTR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTR_PRG_OFFSET)
#define STM32_FLASH_SECBOOTR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTR_CUR_OFFSET)
#define STM32_FLASH_SECBOOTR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTR_PRG_OFFSET)
#define STM32_FLASH_OTBPBLR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OTBPBLR_CUR_OFFSET)
#define STM32_FLASH_OTBPBLR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OTBPBLR_PRG_OFFSET)
#define STM32_FLASH_SECBB1R_1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_1_OFFSET)
#define STM32_FLASH_SECBB1R_2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_2_OFFSET)
#define STM32_FLASH_SECBB1R_3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_3_OFFSET)
#define STM32_FLASH_SECBB1R_4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R_4_OFFSET)
#define STM32_FLASH_PRIVBB1R_1 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_1_OFFSET)
#define STM32_FLASH_PRIVBB1R_2 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_2_OFFSET)
#define STM32_FLASH_PRIVBB1R_3 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_3_OFFSET)
#define STM32_FLASH_PRIVBB1R_4 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R_4_OFFSET)
#define STM32_FLASH_SECWM1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R_CUR_OFFSET)
#define STM32_FLASH_SECWM1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R_PRG_OFFSET)
#define STM32_FLASH_WRP1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1R_CUR_OFFSET)
#define STM32_FLASH_WRP1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_WRP1R_PRG_OFFSET)
#define STM32_FLASH_EDATA1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_EDATA1R_CUR_OFFSET)
#define STM32_FLASH_EDATA1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_EDATA1R_PRG_OFFSET)
#define STM32_FLASH_HDP1R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_HDP1R_CUR_OFFSET)
#define STM32_FLASH_HDP1R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_HDP1R_PRG_OFFSET)
#define STM32_FLASH_ECCCORR (STM32_FLASHIF_BASE + STM32_FLASH_ECCCORR_OFFSET)
#define STM32_FLASH_ECCDETR (STM32_FLASHIF_BASE + STM32_FLASH_ECCDETR_OFFSET)
#define STM32_FLASH_ECCDR (STM32_FLASHIF_BASE + STM32_FLASH_ECCDR_OFFSET)
#define STM32_FLASH_SECBB2R_1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_1_OFFSET)
#define STM32_FLASH_SECBB2R_2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_2_OFFSET)
#define STM32_FLASH_SECBB2R_3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_3_OFFSET)
#define STM32_FLASH_SECBB2R_4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R_4_OFFSET)
#define STM32_FLASH_PRIVBB2R_1 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_1_OFFSET)
#define STM32_FLASH_PRIVBB2R_2 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_2_OFFSET)
#define STM32_FLASH_PRIVBB2R_3 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_3_OFFSET)
#define STM32_FLASH_PRIVBB2R_4 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R_4_OFFSET)
#define STM32_FLASH_SECWM2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R_CUR_OFFSET)
#define STM32_FLASH_SECWM2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R_PRG_OFFSET)
#define STM32_FLASH_WRP2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2R_CUR_OFFSET)
#define STM32_FLASH_WRP2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_WRP2R_PRG_OFFSET)
#define STM32_FLASH_EDATA2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_EDATA2R_CUR_OFFSET)
#define STM32_FLASH_EDATA2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_EDATA2R_PRG_OFFSET)
#define STM32_FLASH_HDP2R_CUR (STM32_FLASHIF_BASE + STM32_FLASH_HDP2R_CUR_OFFSET)
#define STM32_FLASH_HDP2R_PRG (STM32_FLASHIF_BASE + STM32_FLASH_HDP2R_PRG_OFFSET)
/* Register Bitfield Definitions ********************************************/
@ -246,7 +246,7 @@
#define FLASH_ACR_WRHIGHFREQ_SHIFT (4)
#define FLASH_ACR_WRHIGHFREQ_MASK (0x3 << FLASH_ACR_WRHIGHFREQ_SHIFT)
# define FLASH_ACR_WRHIGHFREQ(n) ((n) << FLASH_ACR_WRHIGHFREQ_SHIFT) /* Used to control the delay between NVM
# define FLASH_ACR_WRHIGHFREQ(n) ((n) << FLASH_ACR_WRHIGHFREQ_SHIFT) /* Used to control the delay between NVM
* signals during programming operations
*/
#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch Enable */

28
arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h
View file

@ -141,7 +141,7 @@
#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */
#define RCC_CR_HSIKERON (1 << 2) /* Bit 2: HSI clock enable in Stop mode */
#define RCC_CR_HSIDIV_SHIFT (3) /* Bit [4:3] HSI Divider */
#define RCC_CR_HSIDIV_MASK (0x3 << RCC_CR_HSIDIV_SHIFT)
#define RCC_CR_HSIDIV_MASK (0x3 << RCC_CR_HSIDIV_SHIFT)
# define RCC_CR_HSIDIV(n) (((n) << RCC_CR_HSIDIV_SHIFT & RCC_CR_HSIDIV_MASK))
#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI divider flag */
@ -156,7 +156,7 @@
#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: HSE clock bypass */
#define RCC_CR_HSECSSON (1 << 19) /* Bit 19: HSE clock security system enable */
#define RCC_CR_HSEEXT (1 << 20) /* Bit 20: HSE external high speed clock
#define RCC_CR_HSEEXT (1 << 20) /* Bit 20: HSE external high speed clock
* type in bypass mode */
#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: PLL1 enable */
#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: PLL1 clock ready flag */
@ -1221,18 +1221,18 @@
/* Secure Configuration Register */
#define RCC_SECCFGR_HSISEC (1 << 0) /* HSI clock configuration and status bits security */
#define RCC_SECCFGR_HSESEC (1 << 1) /* HSE clock configuration and status bits security */
#define RCC_SECCFGR_CSISEC (1 << 2) /* CSI clock configuration and status bits security */
#define RCC_SECCFGR_LSISEC (1 << 3) /* LSI clock configuration and status bits security */
#define RCC_SECCFGR_LSESEC (1 << 4) /* LSE clock configuration and status bits security */
#define RCC_SECCFGR_SYSCLKSEC (1 << 5) /* SYSCLK configuration and status bits security */
#define RCC_SECCFGR_PRESCSEC (1 << 6) /* PRESC configuration and status bits security */
#define RCC_SECCFGR_PLL1SEC (1 << 7) /* PLL1 configuration and status bits security */
#define RCC_SECCFGR_PLL2SEC (1 << 8) /* PLL2 configuration and status bits security */
#define RCC_SECCFGR_PLL3SEC (1 << 9) /* PLL3 configuration and status bits security */
#define RCC_SECCFGR_HSI48SEC (1 << 11) /* HSI48 configuration and status bits security */
#define RCC_SECCFGR_RMVRST (1 << 12) /* Remove Reset flag security */
#define RCC_SECCFGR_HSISEC (1 << 0) /* HSI clock configuration and status bits security */
#define RCC_SECCFGR_HSESEC (1 << 1) /* HSE clock configuration and status bits security */
#define RCC_SECCFGR_CSISEC (1 << 2) /* CSI clock configuration and status bits security */
#define RCC_SECCFGR_LSISEC (1 << 3) /* LSI clock configuration and status bits security */
#define RCC_SECCFGR_LSESEC (1 << 4) /* LSE clock configuration and status bits security */
#define RCC_SECCFGR_SYSCLKSEC (1 << 5) /* SYSCLK configuration and status bits security */
#define RCC_SECCFGR_PRESCSEC (1 << 6) /* PRESC configuration and status bits security */
#define RCC_SECCFGR_PLL1SEC (1 << 7) /* PLL1 configuration and status bits security */
#define RCC_SECCFGR_PLL2SEC (1 << 8) /* PLL2 configuration and status bits security */
#define RCC_SECCFGR_PLL3SEC (1 << 9) /* PLL3 configuration and status bits security */
#define RCC_SECCFGR_HSI48SEC (1 << 11) /* HSI48 configuration and status bits security */
#define RCC_SECCFGR_RMVRST (1 << 12) /* Remove Reset flag security */
#define RCC_SECCFGR_CKPERSELSEC (1 << 13) /* PER_CK selection security */
/* Privilege Configuration Register */

2
arch/arm/src/stm32u5/hardware/stm32_memorymap.h
View file

@ -70,7 +70,7 @@
#else
# error "stm32_memorymap: unsupported STM32U5 memory map"
#endif
#endif
/* System Memory Addresses **************************************************/

2
arch/arm/src/stm32u5/hardware/stm32_spi.h
View file

@ -31,7 +31,7 @@
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# include "hardware/stm32u5xx_spi.h"
#else
# error "Unsupported STM32U5 chip"

2
arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h
View file

@ -30,7 +30,7 @@
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
/****************************************************************************
* Pre-processor Definitions

2
arch/risc-v/include/hpm6000/hpm_irq.h
View file

@ -83,7 +83,7 @@
#define HPM_IRQ_HALL1 (HPM_IRQ_PERI_START + 46)
#define HPM_IRQ_QEI1 (HPM_IRQ_PERI_START + 47)
#define HPM_IRQ_SDP (HPM_IRQ_PERI_START + 48)
#define HPM_IRQ_XPI0 (HPM_IRQ_PERI_START + 49)
#define HPM_IRQ_XPI0 (HPM_IRQ_PERI_START + 49)
#define HPM_IRQ_XPI1 (HPM_IRQ_PERI_START + 50)
#define HPM_IRQ_XDMA (HPM_IRQ_PERI_START + 51)
#define HPM_IRQ_HDMA (HPM_IRQ_PERI_START + 52)

4
arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h
View file

@ -173,7 +173,7 @@
#define HPM_SYSCTL_POWER_CPU0_STATUS (HPM_SYSCTL_BASE + 0x1000)
#define HPM_SYSCTL_POWER_CPU0_LF_WAIT (HPM_SYSCTL_BASE + 0x1004)
#define HPM_SYSCTL_POWER_CPU0_OFF_WAIT (HPM_SYSCTL_BASE + 0x100c)
#define HPM_SYSCTL_RESET_SOC_CONTROL (HPM_SYSCTL_BASE + 0x1400)
#define HPM_SYSCTL_RESET_SOC_CONTROL (HPM_SYSCTL_BASE + 0x1400)
#define HPM_SYSCTL_RESET_SOC_CONFIG (HPM_SYSCTL_BASE + 0x1404)
#define HPM_SYSCTL_RESET_SOC_COUNTER (HPM_SYSCTL_BASE + 0x140c)
#define HPM_SYSCTL_RESET_CPU0_CONTROL (HPM_SYSCTL_BASE + 0x1410)
@ -406,7 +406,7 @@
#define SYSCTL_MONITOR_CONTROL_ACCURACY (1 << 9)
#define SYSCTL_MONITOR_CONTROL_REFERENCE (1 << 8)
#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0)
#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xffU << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xffU << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
#define SYSCTL_MONITOR_CONTROL_SELECTION(n) ((n) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24)

2
arch/risc-v/src/hpm6000/hpm_ioc.h
View file

@ -47,7 +47,7 @@
#define PAD_ALT_SHIFT (11) /* Bits 11-15: Peripheral alternate function */
#define PAD_ALT_MASK (0x1f << PAD_ALT_SHIFT)
# define PAD_ALT0 (0 << PAD_ALT_SHIFT)
# define PAD_ALT0 (0 << PAD_ALT_SHIFT)
# define PAD_ALT1 (1 << PAD_ALT_SHIFT)
# define PAD_ALT2 (2 << PAD_ALT_SHIFT)
# define PAD_ALT3 (3 << PAD_ALT_SHIFT)

4
arch/risc-v/src/jh7110/jh7110_mm_init.c
View file

@ -65,8 +65,8 @@
#define SLAB_COUNT (sizeof(m_l3_pgtable) / RV_MMU_PAGE_SIZE)
#define KMM_PAGE_SIZE RV_MMU_L3_PAGE_SIZE
#define KMM_PBASE PGT_L3_PBASE
#define KMM_PBASE_IDX 3
#define KMM_PBASE PGT_L3_PBASE
#define KMM_PBASE_IDX 3
#define KMM_SPBASE PGT_L2_PBASE
#define KMM_SPBASE_IDX 2

4
arch/risc-v/src/litex/litex_mm_init.c
View file

@ -60,8 +60,8 @@
#define SLAB_COUNT (sizeof(m_l2_pgtable) / RV_MMU_PAGE_SIZE)
#define KMM_PAGE_SIZE RV_MMU_L2_PAGE_SIZE
#define KMM_PBASE PGT_L2_PBASE
#define KMM_PBASE_IDX 2
#define KMM_PBASE PGT_L2_PBASE
#define KMM_PBASE_IDX 2
#define KMM_SPBASE PGT_L1_PBASE
#define KMM_SPBASE_IDX 1

8
arch/risc-v/src/qemu-rv/qemu_rv_mm_init.c
View file

@ -60,8 +60,8 @@
#define SLAB_COUNT (sizeof(m_l2_pgtable) / RV_MMU_PAGE_SIZE)
#define KMM_PAGE_SIZE RV_MMU_L2_PAGE_SIZE
#define KMM_PBASE PGT_L2_PBASE
#define KMM_PBASE_IDX 2
#define KMM_PBASE PGT_L2_PBASE
#define KMM_PBASE_IDX 2
#define KMM_SPBASE PGT_L1_PBASE
#define KMM_SPBASE_IDX 1
@ -83,8 +83,8 @@
#define SLAB_COUNT (sizeof(m_l3_pgtable) / RV_MMU_PAGE_SIZE)
#define KMM_PAGE_SIZE RV_MMU_L3_PAGE_SIZE
#define KMM_PBASE PGT_L3_PBASE
#define KMM_PBASE_IDX 3
#define KMM_PBASE PGT_L3_PBASE
#define KMM_PBASE_IDX 3
#define KMM_SPBASE PGT_L2_PBASE
#define KMM_SPBASE_IDX 2

2
boards/arm/at32/at32f437-mini/include/board.h
View file

@ -228,7 +228,7 @@
* usb clock use pll
* usb_clk = 288/6 = 48MHz
*/
#define USB_CONFIG_USBDIV (CRM_MISC2_USBDIV_6P0)
#define USB_CONFIG_USBDIV (CRM_MISC2_USBDIV_6P0)
/* USART1 */

4
boards/arm/at32/at32f437-mini/src/at32_gpio.c
View file

@ -125,9 +125,9 @@ static struct at32gpio_dev_s g_gpout[BOARD_NGPIOOUT];
static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] =
{
#if 0
#if 0
GPIO_INT1,
#endif
#endif
};
static struct at32gpint_dev_s g_gpint[BOARD_NGPIOINT];

2
boards/arm/at32/at32f437-mini/src/at32_usb.c
View file

@ -320,7 +320,7 @@ void at32_usbhost_vbusdrive(int iface, bool enable)
#ifdef CONFIG_USBHOST
int at32_setup_overcurrent(xcpt_t handler, void *arg)
{
#ifdef CONFIG_AT32_OTGFS_VBUS_CONTROL
#ifdef CONFIG_AT32_OTGFS_VBUS_CONTROL
return at32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
#endif

2
boards/arm/at32/at32f437-mini/src/at32f437-mini.h
View file

@ -156,7 +156,7 @@
#define GPIO_OUT1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_DRV_MODETATE|\
GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN2)
#define GPIO_IN1
#define GPIO_INT1
#define GPIO_INT1
/* LEDs */

2
drivers/mtd/at25ee.c
View file

@ -267,7 +267,7 @@ static void at25ee_lock(FAR struct spi_dev_s *dev)
#ifdef CONFIG_SPI_DELAY_CONTROL
SPI_SETDELAY(dev, CONFIG_AT25EE_START_DELAY, CONFIG_AT25EE_STOP_DELAY,
CONFIG_AT25EE_CS_DELAY, CONFIG_AT25EE_IFDELAY);
#endif
#endif
}
/****************************************************************************