From 9e4cd2f720db12f54dbbe72b92d73afcc34b1931 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Fri, 9 Feb 2018 13:00:20 -0600 Subject: [PATCH] arch/arm/src/xmc4/: Fix USIC_BRG_SCLKCFG definition --- arch/arm/src/xmc4/chip/xmc4_usic.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 0ca992d548..af43e11f90 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -465,7 +465,12 @@ # define USIC_BRG_PDIV(n) ((uint32_t)(n) << USIC_BRG_PDIV_SHIFT) #define USIC_BRG_SCLKOSEL (1 << 28) /* Bit 28: Shift Clock Output Select */ #define USIC_BRG_MCLKCFG (1 << 29) /* Bit 29: Master Clock Configuration */ -#define USIC_BRG_SCLKCFG (1 << 30) /* Bit 30: Shift Clock Output Configuration */ +#define USIC_BRG_SCLKCFG_SHIFT 30 /* Bits 30-31: Shift Clock Output Configuration */ +#define USIC_BRG_SCLKCFG_MASK (3 << USIC_BRG_SCLKCFG_SHIFT) +# define USIC_BRG_SCLKCFG_NOINVNODLY (0 << USIC_BRG_SCLKCFG_SHIFT) /* No inverted signal and no delay */ +# define USIC_BRG_SCLKCFG_INVNODLY (1 << USIC_BRG_SCLKCFG_SHIFT) /* Inverted signal and no delay */ +# define USIC_BRG_SCLKCFG_NOINVDLY (2 << USIC_BRG_SCLKCFG_SHIFT) /* No inverted signal and 1/2 delay */ +# define USIC_BRG_SCLKCFG_INVDLY (3 << USIC_BRG_SCLKCFG_SHIFT) /* Inverted signal and 1/2 delay */ /* Interrupt Node Pointer Register */