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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3431 42af7a65-404d-4744-a932-0658087f49c3
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patacongo 2011-03-28 15:01:43 +00:00
parent c5ec593bc4
commit a082aebc77
14 changed files with 803 additions and 370 deletions
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@ -49,7 +49,7 @@
* Separated C5471 serial driver; a shareable part is
in drivers/. ; the C5471 specific part is in arch/C5471.
serial.h defines the interface.
* Fixed mq_receive() and mq_send() -- bad memcpy()
* Fixed mq_receive() and mq_send(): bad memcpy()
* Fixed C5471 signal deliver logic: use of dbg() and
other actions by use signal handler can alter errno.
need to protect errno during signal handling.
@ -247,7 +247,7 @@
* Removed unused uIP files
* sched/, mm/, and net/ subsystem debug can not be selectively enabled/disabled
* Correct socket close logic -- needs to disconnect TCP socket on close
* Correct socket close logic: needs to disconnect TCP socket on close
* uIP webserver now seems to be fully functional
* fs/ and lib/ subystem debug can not be selectively enabled/disabled
* Added vsnprintf
@ -358,7 +358,7 @@
0.3.11 2008-06-01 Gregory Nutt <spudmonkey@racsa.co.cr>
* Add support for recursive mutexes.
* Eliminate a memory leak -- contained watchdog instance was not being
* Eliminate a memory leak: contained watchdog instance was not being
deleted with a POSIX timer was deleted reported by kwonsk.
* Eliminate a deadlock condition in opendir() reported by kwonsk.
* Fix several FAT filesystem problems reported by kwonsk (Changes not yet
@ -604,7 +604,7 @@
against toolchains that do not support 64-bit type 'long long'.
* Fix errors in some function prototypes in dirent.h
* Add eZ80F91 EMAC driver
* Fix recvfrom() compilation error -- only noted under ZDS
* Fix recvfrom() compilation error: only noted under ZDS
* Updated all ARM Make.def files to work with gcc 2.4.2 (However, there are
still some build issues associated with that toolchain in use of arm-elf-objcopy
-- see the TODO.txt list for details)
@ -924,58 +924,58 @@
context switches and background/user context switches. This change should
improve the performance of those background/user context switches by a factor
of about two.
* arch/arm/src/stm32/ - fix several typos in the serial logic. It turns out
* arch/arm/src/stm32/: fix several typos in the serial logic. It turns out
that these typose don't make any difference as long as you use only one
serial port and all uarts are configured the same. But the typos are bugs
waiting to happen in any other configuration.
* arch/arm/src/stm32/ - You have to configure CTS/RTS function pins for USART
* arch/arm/src/stm32/: You have to configure CTS/RTS function pins for USART
2 and USART 3 even if you are not using flow control.
* arch/arm/src/stm32/stm32_usbdev.c - Added a USB device-side driver for the
* arch/arm/src/stm32/stm32_usbdev.c: Added a USB device-side driver for the
STM32. NOTE: This is an early release of the USB driver. There is at least
one known issue. The examples/usbserial test only executes correctly under
certain conditions (see the full bug description in the TODO list).
* arch/arm/src/stm32/stm32_rcc.c - Fixed an error in clock initialization.
* arch/arm/src/stm32/stm32_rcc.c: Fixed an error in clock initialization.
On some boards (none of mine), the HSE (high speed external clock) delay
loop times out if the optimization level is high. The STM32 then falls
back to the HSI (internal clock), and the system clock is too slow by a
factor of 11.1%. This was fixed by simply add the volatile storage class
to the timeout loop counter
* arch/arm/src/stm32/stm32_irq.c - Fixed a critical bug in the interrupt
* arch/arm/src/stm32/stm32_irq.c: Fixed a critical bug in the interrupt
control logic. The wrong register was being used for interrupts in a
certain range. Worked fine until you try to use an interrupt in that
range!
4.14 2009-12-02 Gregory Nutt <spudmonkey@racsa.co.cr>
* arch/arm/src/stm32/stm32_gpio.c - Add support for configure an input GPIO
* arch/arm/src/stm32/stm32_gpio.c: Add support for configure an input GPIO
to generate an EXTI interrupt.
* config/stm3210e-eval/src/up_buttons.c - Add support for on-board buttons.
* include/nuttx/rwbuffer.h -- Add generic support for read-ahead buffering
* config/stm3210e-eval/src/up_buttons.c: Add support for on-board buttons.
* include/nuttx/rwbuffer.h: Add generic support for read-ahead buffering
and write buffering that can be used in any block driver.
* include/nuttx/wqueue.h -- Added a generic worker thread that can used to
* include/nuttx/wqueue.h: Added a generic worker thread that can used to
defer processing from an interrupt to a task.
* include/nuttx/sdio.h -- Defines a generic SD/SDIO interface can can be
* include/nuttx/sdio.h: Defines a generic SD/SDIO interface can can be
bound to a MMC/SD driver to provide SDIO-based MMC/SD support.
* drivers/mmcsd/mmcsd_sdio.c -- Provides an SDIO-based MMC/SD driver.
* arch/arm/src/stm32/stm32_sdio.c -- Provides an STM32 implementation of
* drivers/mmcsd/mmcsd_sdio.c: Provides an SDIO-based MMC/SD driver.
* arch/arm/src/stm32/stm32_sdio.c: Provides an STM32 implementation of
the SDIO interface defined in include/nuttx/sdio.h.
* fs/fs_mount.c -- Correct error handling logic. If the bind() method
* fs/fs_mount.c: Correct error handling logic. If the bind() method
fails, then a reserved node is left in the tree. This causes subsequent
attempts to mount at the location to fail (reporting that the node
already exists). This is a problem for block drivers for removable
media: The bind method could fail repeatedly until media is inserted.
* arch/arm/src/stm32/chip.h & stm32_dma.c -- Fixed several definitions
* arch/arm/src/stm32/chip.h & stm32_dma.c: Fixed several definitions
that can cause compilation errors when DMA2 is enabled.
* arch/arm/src/stm32/stm32_dma.c - Integrated and debugged STM32 DMA
* arch/arm/src/stm32/stm32_dma.c: Integrated and debugged STM32 DMA
functionality that was added in 0.4.12.
* configs/stm3210e-eval/usbstorage - Add a configuration to exercise
* configs/stm3210e-eval/usbstorage: Add a configuration to exercise
the STM32 with the USB mass storage device class example
(examples/usbstorage).
* configs/mcu123-lpc214x/up_usbstrg - Move LPC-specific code from
* configs/mcu123-lpc214x/up_usbstrg: Move LPC-specific code from
examples/usbstorage to configs/mcu123-lpc214x.
* configs/stm321e-eval/up_usbstrg - Add STM32-specific logic for the
* configs/stm321e-eval/up_usbstrg: Add STM32-specific logic for the
examples/usbstorage test.
* arch/arm/src/stm32/stm32_usbdev.c - Fix bugs in STM32 USB device-side
* arch/arm/src/stm32/stm32_usbdev.c: Fix bugs in STM32 USB device-side
driver: (1) Need to disconnect after reset received, (2) Status setup
to recover from stall on TX endpoint.
@ -984,7 +984,7 @@
* arch/hc: Adding framework to support m68hc11/12
* configs/demo9s12ne64: Configuration to support Freescale DEMO9S12NE64
development board (MC9S12NE64 m68hcs12 processor).
* drivers/mtd/ftl.c - A FLASH translation layer (FTL) has been implemented.
* drivers/mtd/ftl.c: A FLASH translation layer (FTL) has been implemented.
This layer will convert a FLASH MTD interface into a block driver that
can be used with any file system. Good performance of this layer will
depend upon functioning write buffer support!
@ -994,7 +994,7 @@
between uint32 (32-bits) and an mc68hc12 pointer (16-bits).
* sys/types: Size of off_t and blkcnt_t should not depend on size of
int in the architecture; Removed non-standard type STATUS
* include/ - Added header files stdint.h, stdbool.h, cxx/cstdint, and
* include/: Added header files stdint.h, stdbool.h, cxx/cstdint, and
cxx/cstdbool
* Changed ALL references to non-standard fixed-size types (like uint32,
ubyte, etc.) to standard types (like uint32_t, uint8_t, etc.) from
@ -1002,30 +1002,30 @@
most of the files in the system! Almost all configurations have been
re-built and many have been re-verified in order to get confidence in
these changes.
* graphics/ and examples/nx - Fix numerous build errors that have been
* graphics/ and examples/nx: Fix numerous build errors that have been
introduced lately. NXGL has suffered some bit-rot from not being used
in some of the most recent ports.
* The misc/pascal NuttX add-on package has been updated to use the new
standard types from stdint.h and stdbool.h and re-integrated with NuttX.
The released pascal-2.0 will be the first version that contains the
compatible changes.
* arch/arm/src/lm3s/lm3s_ethernet.c - Fixed an important bug in the LM3S
* arch/arm/src/lm3s/lm3s_ethernet.c: Fixed an important bug in the LM3S
ethernet driver: If full packet is received, the packet-too-big check
will fail because it needs to subtract 6 from the packet size (to
account for the 2-byte packet length and the 4-byte packet FCS in the
FIFO).
* net/accept.c - Fixed a bad assertion (only happens when debug is enabled).
* net/send.c net/uip/uip_tcpseqno.c - Fixed a critical error in the TCP/IP
* net/accept.c: Fixed a bad assertion (only happens when debug is enabled).
* net/send.c net/uip/uip_tcpseqno.c: Fixed a critical error in the TCP/IP
logic. The NuttX port of uIP imcludes logic to send data ahead without
waiting for ACKs from the recipient; this greatly improves throughput.
However, the packet sequence number was not being updated correctly and,
as a result, packets were not be ACKed by the recipient and transfers
would sometimes stall. This is a very important bug fix (in fact, I
don't understand how TCP/IP worked at all without this fix???)
* include/nuttx/arch.h and arch/*/common/up_udelay.c - Change argument
* include/nuttx/arch.h and arch/*/common/up_udelay.c: Change argument
of up_udelay() to type useconds_t to avoid warnings when sizeof(int)
is 16-bits.
* drivers/mmcsd/* - Add casts in constant expressions to avoid warnings
* drivers/mmcsd/*: Add casts in constant expressions to avoid warnings
when sizeof(int) is 16-bits.
5.1 2010-01-30 Gregory Nutt <spudmonkey@racsa.co.cr>
@ -1042,194 +1042,194 @@
the larger (but faster) table look-up version of the CRC32 algorithm.
* confgs/ea3131/tools: Added a tool to create a image suitable for
use with the LPC313x bootloader.
* configs/sam3u-3k/ostest - Completed verification of the basic NuttX
* configs/sam3u-3k/ostest: Completed verification of the basic NuttX
OS test for the SAM3U.
* arch/arm/src/common/up_createstack - stack was always been cleared
* arch/arm/src/common/up_createstack: stack was always been cleared
when it was allocated. This is a good feature for monitoring the
stack during debug, but really hurts thread start-up performance.
Clearing is now done if CONFIG_DEBUG=y only. Changes was only made
for arm, but really should be made for all architectures.
* configs/sam3u/nsh - Added NSH configuration for SAM3U
* configs/sam3u/nsh: Added NSH configuration for SAM3U
5.2 2010-03-18 Gregory Nutt <spudmonkey@racsa.co.cr>
* arch/arm/src/sam3u/sam3u_pio.c - Fix an address calculation error
* arch/arm/src/sam3u/sam3u_pio.c: Fix an address calculation error
that caused ports B & C to get mapped to the PIOA base address.
This is an important bugfix! (a patch is available)
* arch/arm/src/lpc313x/lpc313x_boot.c - Fix an error in the vector
* arch/arm/src/lpc313x/lpc313x_boot.c: Fix an error in the vector
initialization was causing a memory fault.
* lib/lib_strtod.c - Add strtod()
* lpc3131/ea3131 - Several bring fixes submitted by David Hewson. The
* lib/lib_strtod.c: Add strtod()
* lpc3131/ea3131: Several bring fixes submitted by David Hewson. The
lpc3131 is almost there! Thanks David!
* arch/arm/src/arm/up_head.S - Corrected backward conditional compilation
* arch/arm/src/arm/up_head.S: Corrected backward conditional compilation
that selects if vectors are located at 0x0000:0000 or 0xffff:f000.
This fixes the last show stopper bug in the lpc313x bring-up.
* configs/ea3131/nsh - Added a NuttShell (NSH) configuration for the
* configs/ea3131/nsh: Added a NuttShell (NSH) configuration for the
EA3131.
5.3 2010-04-11 Gregory Nutt <spudmonkey@racsa.co.cr>
* arch/arm/src/lpc313x/lpc313x_usbdev.c - USB driver for the LPC313x
* arch/arm/src/lpc313x/lpc313x_usbdev.c: USB driver for the LPC313x
contributed by David Hewson.
* configs/ea3131/src/up_ubstrgc.c, configs/ea3131/usbserial,
configs/ea3131/usbstorage - USB storage and USB serial example support
configs/ea3131/usbstorage: USB storage and USB serial example support
contributed by David Hewson.
* Several important compilation error fixes in lpc313x and (dualspeed) USB
code also contributed by David Hewson.
* arch/arm/src/sam3u/sam3u_dmac.c - DMA support for the AT90SAM3U.
* arch/arm/src/sam3u/sam3u_hsmci.c - SD memory card support for AT90SAM3U
* arch/arm/src/sam3u/sam3u_dmac.c: DMA support for the AT90SAM3U.
* arch/arm/src/sam3u/sam3u_hsmci.c: SD memory card support for AT90SAM3U
(Neither the DMA nor the HSMCI driver are functional on the initial checkin).
* drivers/usbdev - Several important fixes to the USB mass storage driver
* drivers/usbdev: Several important fixes to the USB mass storage driver
submitted by David Hewson.
* configs/olimex-lpc2378, arch/arm/include/lpc2378, and arch/arm/src/lpc2378 -
Basic port of the NXP 2378 on the Olimex board contributed by
Rommel Marcelo.
* arch/arm/src/sam3u/sam3u_internal.h - Fixed a critical bug in the AT91SAM3U
* arch/arm/src/sam3u/sam3u_internal.h: Fixed a critical bug in the AT91SAM3U
PIO decoding. No PIOs greater than 15 could be used on any port! Obviously,
no one has been using this port.
5.4 2010-04-23 Gregory Nutt <spudmonkey@racsa.co.cr>
* include/nuttx/lcd.h - Defines an LCD interface.
* graphics/nxglib/fb and lcd - Support LCD and framebuffer rasterizers for NX.
* configs/sam3u-ek/src/up_lcd.c - LCD driver for LCD on SAM3U-EK development
* include/nuttx/lcd.h: Defines an LCD interface.
* graphics/nxglib/fb and lcd: Support LCD and framebuffer rasterizers for NX.
* configs/sam3u-ek/src/up_lcd.c: LCD driver for LCD on SAM3U-EK development
board.
* configs/sam3u-ek/nx - NX graphics configuration for the SAM3U-EK
* configs/sam3u-ek/nx: NX graphics configuration for the SAM3U-EK
5.5 2010-05-09 Gregory Nutt <spudmonkey@racsa.co.cr>
* drivers/net/enc28j60.c - Microchip ENC28J60 SPI ethernet chip driver.
* drivers/net/enc28j60.c: Microchip ENC28J60 SPI ethernet chip driver.
(untested on original check-in).
* configs/olimex-str7p11/nettest - examples/nettest configuration using
* configs/olimex-str7p11/nettest: examples/nettest configuration using
the ENC28J60 driver on the Olimex STMicro STR-P711.
(unverified on original check-in)
* configs/olimex-str7p11/src/up_enc28j60.c - Add ENC28J60 initialization
* configs/olimex-str7p11/src/up_enc28j60.c: Add ENC28J60 initialization
logic.
* configs/olimex-str7p11/src/up_spi.c - Fixed some bugs; added support
* configs/olimex-str7p11/src/up_spi.c: Fixed some bugs; added support
for ENC28J60.
* arch/arm/src/str7x/str7x_xti.c - Add basic XTI support (external
* arch/arm/src/str7x/str7x_xti.c: Add basic XTI support (external
interrupts).
* arch/arm/src/lm3s and arch/arm/include/lm3s - Add definitions for
* arch/arm/src/lm3s and arch/arm/include/lm3s: Add definitions for
LM3S6965
* configs/lm3s6965-ek - Add configuration for Stellaris LM3S6965
* configs/lm3s6965-ek: Add configuration for Stellaris LM3S6965
Evaluation Kit (including basic examples/ostest configuration)
* lib/lib_dtoa.c and lib/lib_dtoa.c - printf will not print floating
* lib/lib_dtoa.c and lib/lib_dtoa.c: printf will not print floating
point values if you select CONFIG_LIBC_FLOATINGPOINT in your
configuration file. Contributed by Yolande Cates. NOTE: these
floating point operations have not been well tested and may not
be portable to all floating point implementations.
* configs/lm3s6965-ek/nsh - Added NuttShell (NSH) configuration for
* configs/lm3s6965-ek/nsh: Added NuttShell (NSH) configuration for
the LM3S6965 Evaluation Kit. Includes both serial and telnet
interfaces.
* net/net_close.c - Correct a UDP reference counting error
* net/net_close.c: Correct a UDP reference counting error
5.6 2010-06-05 Gregory Nutt <spudmonkey@racsa.co.cr>
* drivers/lcd/p14201.c - Driver for RiT P14201 series 128x96 4-bit OLED.
* configs/lm3s6965-ek/nx - NX graphics configuration for the LM3S6965
* drivers/lcd/p14201.c: Driver for RiT P14201 series 128x96 4-bit OLED.
* configs/lm3s6965-ek/nx: NX graphics configuration for the LM3S6965
Ethernet Evaluation Kit.
* graphics/ - Numerous fixes to get the P14201 4-bpp grayscale display
* graphics/: Numerous fixes to get the P14201 4-bpp grayscale display
working (there may still be some minor issues .. see the TODO list).
* arch/arm/include/lpc17xx and arch/arm/src/lpc17xxx - Began port for
* arch/arm/include/lpc17xx and arch/arm/src/lpc17xxx: Began port for
NXP LPC1768. As of the 5.6 release, there is a complete set of
LPC17xx header files defining all bits in all LPC17xx registers,
but little else (I still do not have hardware in hand).
* drivers/mtd/m25px.c - Add support for M25P1 flash part (See NOTE)
* include/nuttx/i2c.h - Extended I2C interface definition to handle
* drivers/mtd/m25px.c: Add support for M25P1 flash part (See NOTE)
* include/nuttx/i2c.h: Extended I2C interface definition to handle
multiple transfers (See NOTE).
* include/nuttx/usbdev.h - Corrected an important macro definition
* include/nuttx/usbdev.h: Corrected an important macro definition
needed to correctly handle USB null packet transfers (See NOTE).
* arch/arm/src/lpc313x - New drivers: I2C and SPI. Plus several
* arch/arm/src/lpc313x: New drivers: I2C and SPI. Plus several
important LPC313x USB bug fixes (See NOTE).
NOTE: Contributed by David Hewson.
5.7 2010-06-22 Gregory Nutt <spudmonkey@racsa.co.cr>
* configs/nucleus2g - Add ostest configuration for the Nucleus 2G
* configs/nucleus2g: Add ostest configuration for the Nucleus 2G
LPC1768 board from 2G Engineering (http://www.2g-eng.com/)
* arch/arm/src/lpc17xx - Added basic LPC17xx boot-up logic,
* arch/arm/src/lpc17xx: Added basic LPC17xx boot-up logic,
interrupt handling, and GPIO configuration.
* configs/nucleus2g/ostest - Completed bring-up of LPC1768 on
* configs/nucleus2g/ostest: Completed bring-up of LPC1768 on
the Nucleus2G board using the examples/ostest
* configs/nucleus2g/nsh - Added and verified a NuttShell (NSH)
* configs/nucleus2g/nsh: Added and verified a NuttShell (NSH)
configuration for the LPC1768 on the Nucleus2G board.
5.8 2010-07-18 Gregory Nutt <spudmonkey@racsa.co.cr>
* configs/nucleus2g/src/up_nsh.c and up_ssp.c - Add support
* configs/nucleus2g/src/up_nsh.c and up_ssp.c: Add support
for SPI-based MMC/SD cards and integrate into the NSH example.
* arch/arm/src/lm3s/lm3s_vectors.S - Correct vectors for GPIOC & D
* arch/arm/src/lm3s/lm3s_vectors.S: Correct vectors for GPIOC & D
interrupts.
* arch/arm/src/lpc17xx/lp17_clockconfig.c - Power was not being
* arch/arm/src/lpc17xx/lp17_clockconfig.c: Power was not being
provided to GPIO module. This is a critical bugfix!
* arch/arm/src/lpc17xx/lpc17_serial.c - Improved logic to handle
* arch/arm/src/lpc17xx/lpc17_serial.c: Improved logic to handle
missed TX interrupts.
* arch/arm/src/lpc17xx/lpc17_ssp.c - Fix a hard fault during SSP
* arch/arm/src/lpc17xx/lpc17_ssp.c: Fix a hard fault during SSP
initialization.
* configs/nucleus2g/src/up_led.c - Change how LEDs are controlled
* configs/nucleus2g/src/up_led.c: Change how LEDs are controlled
so that they can be used both for NuttX instrumentation and
by application software.
* include/net/uip/igmp.h and uip-igmp.h - Add header files ini
* include/net/uip/igmp.h and uip-igmp.h: Add header files ini
preparation for NuttX IGMP support
* net/uip/uip_igmp*.c - Add IGMP support (untested on initial
* net/uip/uip_igmp*.c: Add IGMP support (untested on initial
checkin).
* examples/igmp - Add a trivial test for IGMP (much more is needed)
* configs/nucleus2g/usbserial and usbstorage - Add USB configurations
* examples/igmp: Add a trivial test for IGMP (much more is needed)
* configs/nucleus2g/usbserial and usbstorage: Add USB configurations
for testing purposes.
* arch/arm/src/common/up_internal.h, cortexm3/up_assert.c,
*/*_vectors.S - Correct compilations errors when CONFIG_ARCH_INTERRUPTSTACK
*/*_vectors.S: Correct compilations errors when CONFIG_ARCH_INTERRUPTSTACK
is enabled (feature still not tested)
5.9 2010-08-25 Gregory Nutt <spudmonkey@racsa.co.cr>
* examples/nsh/nsh_telnetd.c - Fix compilation errors that happen
* examples/nsh/nsh_telnetd.c: Fix compilation errors that happen
when both DHCPC and TELNETD are enabled in the Nuttshell.
* graphics/nxglib/fb/nxglib_moverectangle.c - Fix a logic error
* graphics/nxglib/fb/nxglib_moverectangle.c: Fix a logic error
that caused an uninitialized variable warning. I still don't
have a test to prove that the changes are correct.
* configs/olimex-lpc2378 - Add support for the CodeSourcery toolchain
* configs/olimex-lpc2378: Add support for the CodeSourcery toolchain
under Linux (contributed by Alan Carvalho de Assis).
* arch/arm/src/lpc17xx/lpc17_gpio.c - Fix an important GPIO configuration
* arch/arm/src/lpc17xx/lpc17_gpio.c: Fix an important GPIO configuration
bug: When attempting to set no pull-up or pull-down (floating),
it would, instead, select pull-down.
* arch/arm/src/lm3s/lm3s_gpioirq.c - Fix warning for returning a value
* arch/arm/src/lm3s/lm3s_gpioirq.c: Fix warning for returning a value
from functions returning void (contributed by Tiago Maluta).
* netutils/dhcpc/dhcpc.c -- lease_time was not in host order
* examples/uip/main.c - if DHCPC is selected, this example now shows
* netutils/dhcpc/dhcpc.c: lease_time was not in host order
* examples/uip/main.c: if DHCPC is selected, this example now shows
the assigned IP address.
* arch/arm/src/lm3s and arch/arm/include/lm3s - Definitions for the
* arch/arm/src/lm3s and arch/arm/include/lm3s: Definitions for the
TI LM3S9B96 contributed by Tiago Maluta.
* arch/arm/src/lm3s/lm3s_gioirq.c - Fix a logic error in the address
* arch/arm/src/lm3s/lm3s_gioirq.c: Fix a logic error in the address
table lookup.
* arch/arm/src/lm3s/lm3s_gioirq.c - Also needs to enable the global
* arch/arm/src/lm3s/lm3s_gioirq.c: Also needs to enable the global
GPIO interrupts.
* arch/arm/src/lm3s/lm3s_internal.h and lm3s_gpio.c - Fixed the encoding
* arch/arm/src/lm3s/lm3s_internal.h and lm3s_gpio.c: Fixed the encoding
of GPIO port number that limited support for GPIO ports to 8
* sched/pg_*.c and *.c and include/nuttx/page.h - Implemented the
* sched/pg_*.c and *.c and include/nuttx/page.h: Implemented the
common, core logic for on-demand paging. See
http://www.nuttx.org/NuttXDemandPaging.html for details.
* drivers/usbdev/usbdev_serial.c - Correct compilation errors that
* drivers/usbdev/usbdev_serial.c: Correct compilation errors that
occur if CONFIG_USBDEV_DUALSPEED is selected.
* configs/ea3131/pgnsh - Add an NSH configuration with on-demand paging
* configs/ea3131/pgnsh: Add an NSH configuration with on-demand paging
enabled. This is not expected to be a functionality configuration (at
least not yet); it was created in order to debug the on-demand paging
feature.
* configs/ntosd-dm320/*/Make.defs - Codesourcery and devkitARM toolchains
* configs/ntosd-dm320/*/Make.defs: Codesourcery and devkitARM toolchains
now supported for the Neuros OSD.
* configs/ntosd-dm320 and arch/arm/src/dm320 - Add support for the
* configs/ntosd-dm320 and arch/arm/src/dm320: Add support for the
Neuros production OSD (changes contributed by bf.nuttx).
5.10 2010-09-07 Gregory Nutt <spudmonkey@racsa.co.cr>
* configs/ea3131/locked - Create logic to support a two pass build
* configs/ea3131/locked: Create logic to support a two pass build
process: The first pass forces critical logic into the locked text
region, the second pass builds the NuttX executable more-or-less as
normal.
* Makefile, arch/arm/src/Makefile, configs/ea3131 - Add logic to
* Makefile, arch/arm/src/Makefile, configs/ea3131: Add logic to
support a two-pass final link. This logic is only in place in
the arch/arm/src/Makefile for now.
* arch/arm/src/lpc17xx/lpc17_internal.h - Add missing parentheses in
* arch/arm/src/lpc17xx/lpc17_internal.h: Add missing parentheses in
macros definitions (patch submitted by Tiago Maluta).
* Documents/NuttxPortingGuide.html, configs/README.txt, etc. -
Replaced CONFIG_EXAMPLE with CONFIG_APP_DIR (see documents for
@ -1248,17 +1248,17 @@
with libapp$(LIBEXT) in your Makefiles.
- Check any other occurrences of CONFIG_EXAMPLE.
* arch/arm/src/lpc313x/lpc313x_spi.c - Fix compilation error when
* arch/arm/src/lpc313x/lpc313x_spi.c: Fix compilation error when
when CONFIG_DEBUG is enabled.
* arch/arm/src/lm3s and arch/arm/include/lm3s - Support for the
* arch/arm/src/lm3s and arch/arm/include/lm3s: Support for the
lm3s8962 contributed by Larry Arnold.
* configs/lm328962-ek - Support for the TI/Stellaris EKC-LM3S8962
* configs/lm328962-ek: Support for the TI/Stellaris EKC-LM3S8962
board (also contributed by Larry Arnold).
* arch/arm/src/lpc313x/lpc313x_boot.c - The call to lpc313x_boardinitialized()
* arch/arm/src/lpc313x/lpc313x_boot.c: The call to lpc313x_boardinitialized()
should not be conditioned on CONFIG_ARCH_LEDs being defined!
* arch/arm/src/lpc313x/ - APB0 and APB1 cannot lie in different
* arch/arm/src/lpc313x/: APB0 and APB1 cannot lie in different
sections; they are too close together.
* arch/arm/src/lpc313x/lpc13x_boot.c - Resetting all of the clocking
* arch/arm/src/lpc313x/lpc13x_boot.c: Resetting all of the clocking
had a side effect of wiping out the first 6 words of memory where the
interrupt vectors are located (and also not resetting the fractional
dividers). This is not usually noticeable because the IRQ vectors
@ -1267,43 +1267,43 @@
5.11 2010-10-01 Gregory Nutt <spudmonkey@racsa.co.cr>
* configs/ea3131/src/up_fillpage.c - Added new configuration item
* configs/ea3131/src/up_fillpage.c: Added new configuration item
CONFIG_PAGING_BINPATH. If CONFIG_PAGING_BINPATH is defined, then it
is the full path to a file on a mounted file system that contains
a binary image of the NuttX executable. Pages will be filled by
reading from offsets into this file that correspond to virtual
fault addresses. up_fillpage.c implements logic to perform page
files using the CONFIG_PAGING_BINPATH file.
* configs/mbed - Add configuration to support the mbed.org LPC1768
* configs/mbed: Add configuration to support the mbed.org LPC1768
board (Contributed by Dave Marples).
* sched/sem_wait.c and sem_waitirq.c - Eliminate a race condition
* sched/sem_wait.c and sem_waitirq.c: Eliminate a race condition
that can occur when a semaphore wait is interrupt by a signal.
(see email thread: http://tech.groups.yahoo.com/group/nuttx/message/530)
* drivers/mtd/at45db.c - Add a driver for the Atmel AT45DB161D 4Mbit
* drivers/mtd/at45db.c: Add a driver for the Atmel AT45DB161D 4Mbit
SPI FLASH part (untested on initial check-in).
* arch/arm/src/lm3s and arch/arm/include/lm3s - Corrections for the
* arch/arm/src/lm3s and arch/arm/include/lm3s: Corrections for the
lm3s8962 port contributed by Larry Arnold. That port is purported
to work correctly with these changes in place.
* examples/ostest/prioinherit.c - Need to reinitialize globals if
* examples/ostest/prioinherit.c: Need to reinitialize globals if
test is ran repeatedly in a loop.
* configs/ez80f910200zco - Updated to used ZDS-II 4.11.1
* configs/ez80f910200zco: Updated to used ZDS-II 4.11.1
5.12 2010-10-26 Gregory Nutt <spudmonkey@racsa.co.cr>
* arch/avr - Add a place to support AVR family processors.
* arch/avr/include/avr32 and arch/avr/src/avr32 - Add support for AVR32
* arch/avr: Add a place to support AVR family processors.
* arch/avr/include/avr32 and arch/avr/src/avr32: Add support for AVR32
(all of the AVR32 is a work in progress).
* arch/avr/include/at32uc3 and arch/avr/src/at32uc3 - Add support
* arch/avr/include/at32uc3 and arch/avr/src/at32uc3: Add support
for the AVR32 UC3A/B family of AVR32 MCUs.
* confgs/avr32dev1 - Add support for the Atmel AVR32DEV1 board featuring
* confgs/avr32dev1: Add support for the Atmel AVR32DEV1 board featuring
the AT32UC3B0256 MCU. This board is produced by www.mcuzone.com.
* include/stdlib.h, lib/Makefile, lib/lib_abs.c, lib/lib_labs.c,
lib_labs.c, lib_llabs.c, lib_imaxabs.c - Add abs(), labs(), llabs(), and
lib_labs.c, lib_llabs.c, lib_imaxabs.c: Add abs(), labs(), llabs(), and
imaxabs().
* Add include/inttypes.h
* arch/hc/src/mc9s12ne64 - This hcs12 port grew a few more files. But it
* arch/hc/src/mc9s12ne64: This hcs12 port grew a few more files. But it
is still a long way from complete.
* arch/*/src/*/*_sigdeliver.c - Fixed a serious error in the signal
* arch/*/src/*/*_sigdeliver.c: Fixed a serious error in the signal
trampoline logic. Essentially, interrupts are re-enabled while the
signal handler executes, but the logic to re-disable the interrupts
before returning from the signal handler trampoline was missing. Under
@ -1316,44 +1316,44 @@
5.13 2010-11-09 Gregory Nutt <spudmonkey@racsa.co.cr>
* lib/lib_strnlen.c -- Added POSIX 2008 strnlen() function. Contributed
* lib/lib_strnlen.c: Added POSIX 2008 strnlen() function. Contributed
by Michael Hrabanek.
* Fix wild, consistent naming error. For some reason, I called the at32uc3*
parts at91uc* everywhere. Fixed by changing lots of files and directories.
* configs/avr32dev1/ostest - The AVR32 port now successfully passes the
* configs/avr32dev1/ostest: The AVR32 port now successfully passes the
examples/ostest. We have a good AVR32 port!
* configs/avr32dev1/nsh - Added a configuration to support the NuttShell
* configs/avr32dev1/nsh: Added a configuration to support the NuttShell
(NSH). As of this writing, here is a problem receiving serial data (this
is, very likely, my hardware setup).
* lib/lib_open.c - Fix an error in fdopen when a valid file desciptor does
* lib/lib_open.c: Fix an error in fdopen when a valid file desciptor does
not refer to an open file.
* configs/olimex-lpc1766stk - Add support for the Olimex LPC1766-STK
* configs/olimex-lpc1766stk: Add support for the Olimex LPC1766-STK
development board. The OS test and NSH configurations (only) have been
verified.
5.14 2010-11-27 Gregory Nutt <spudmonkey@racsa.co.cr>
* configs/olimex-lpc1766stk/nettest - Add examples/nettest configuration to
* configs/olimex-lpc1766stk/nettest: Add examples/nettest configuration to
verify the LPC17xx ethernet driver currently under development.
* arch/arm/src/lpc17xx/lpc17xx_ethernet.c/.h - Began development of
* arch/arm/src/lpc17xx/lpc17xx_ethernet.c/.h: Began development of
the LPC17xx Ethernet driver. Driver in CVS functional after 2010-11-23.
* sched/timer_settime.c - Fix an error in set-up of a one-shot POSIX timer. It
* sched/timer_settime.c: Fix an error in set-up of a one-shot POSIX timer. It
was using the repititive timer value (which is zero in the one-shot case),
always resulting in a 10Ms timer! Found and fixed by Wilton Tong.
* arch/arm/src/lpc17xx/lpc17_vector.S, stm32/stm32_vector.S, lm3s/lm3s_vector.S,
sam3u/sam3u_vector.S -- Fixed a hard fault problem that can occur if certain
sam3u/sam3u_vector.S: Fixed a hard fault problem that can occur if certain
types of interrupts are pending at the time another interrupt returns
(SYSTICK). This has not been verified on all plaforms, but is a critical
fixed that is needed by all Cortex-M3 NuttX users.
* configs/olimex-lpc1766stk/thttpd - Add a THTTPD configuration for the
* configs/olimex-lpc1766stk/thttpd: Add a THTTPD configuration for the
Olimex LPC2766-STK board. Verified successfully.
* net/uip/uip_tcpappsend.c - Correct an important logic bug in some uIP state
* net/uip/uip_tcpappsend.c: Correct an important logic bug in some uIP state
data the is used to manage retransmissions. The uIP logic was incompatible
with the retransmission logic of net/send.c in one place. The final error
was that the final packet in a sequence of packets was too large! In the
THTTPD example, this would leave some garbage at the bottom of the display
(or worse). I don't know why I haven't see this bug before???
* net/uip/uip_tcpinput.c -- The change to uip_tcpappsend.c unmasked an
* net/uip/uip_tcpinput.c: The change to uip_tcpappsend.c unmasked an
additional error in the TCP sequence number handling. This sympom was that
the send() function would hang with outstanding, unacknowledged data (with
no re-transmit requests). The was due to differences in sequence number
@ -1362,78 +1362,78 @@
5.15 2010-12-12 Gregory Nutt <spudmonkey@racsa.co.cr>
* net/uip/uip_tcpaddsend.c and net/send.c -- Another place where the TCP sequence
* net/uip/uip_tcpaddsend.c and net/send.c: Another place where the TCP sequence
number problem "fixed" in 5.14 might occur.
* net/send.c -- Check if the destination IP address is in the ARP table. If
* net/send.c: Check if the destination IP address is in the ARP table. If
not, then don't consider the packet sent. It won't be, an ARP packet will go
out instead. This improves behavior, for example, on the first GET request
from a browser.
* arch/arm/src/lpc17xx/lpc17_emacram.h and lpc17_allocateheap.c -- The Ethernet
* arch/arm/src/lpc17xx/lpc17_emacram.h and lpc17_allocateheap.c: The Ethernet
logic was using all of AHB SRAM Bank0 for Ethernet packet buffers (16Kb). An
option was added to limit the amount of SRAM used for packet buffering and to
re-use any extra Bank0 memory for heap. configs/olimex-lpc1766stk/nettest
now uses only 8Kb at the beginning of Bank0; the 8Kb at the end of Bank0 is
included in the heap
* arch/arm/src/lpc17xx/lpc17_ssp.c -- Fix compilation errors when SSP1 is
* arch/arm/src/lpc17xx/lpc17_ssp.c: Fix compilation errors when SSP1 is
selected.
* configs/olimex-lpc1766stk/nsh -- Enable network and SD/MMC card support in
* configs/olimex-lpc1766stk/nsh: Enable network and SD/MMC card support in
NSH. Networking and telnetd interface as well as SPI-based microSD are
now functional.
* examples/nsh/nsh_netinit.c -- Fix NSH bug. If CONFIG_NET is selected, but
* examples/nsh/nsh_netinit.c: Fix NSH bug. If CONFIG_NET is selected, but
CONFIG_EXAMPLES_NSH_TELNETD is not selected, then the network is never
initialized and bad things happen if you try to ping.
* drivers/lcd -- Add header files for the Phillips PCF8833 LCD controller and
* drivers/lcd: Add header files for the Phillips PCF8833 LCD controller and
for the Epson S1D15G10 LCD controller. A driver for the Nokia 6100 LCD is
coming.
* include/nuttx/spi.h and almost all other SPI files -- Added an optional
* include/nuttx/spi.h and almost all other SPI files: Added an optional
cmddata() method to the SPI interface. Some devices require an additional
out-of-band bit to specify if the next word sent to the device is a command
or data. This is typical, for example, in "9-bit" displays where the 9th bit
is the CMD/DATA bit. The cmddata method provides selection of command or data.
* drivers/lcd/p14201.c -- Now uses the cmddata() method of the SPI interface.
* arch/arm/src/lpc17xx/lpc17_usbdev.c -- LPC17xx USB driver now appears to
* drivers/lcd/p14201.c: Now uses the cmddata() method of the SPI interface.
* arch/arm/src/lpc17xx/lpc17_usbdev.c: LPC17xx USB driver now appears to
to be fully functional. examples/usbstorage configuration verified (the
examples/usbserial configuration is untested).
* drivers/usbdev/usbserial.c and usbstorage.c -- All USB class drivers need
* drivers/usbdev/usbserial.c and usbstorage.c: All USB class drivers need
to call DEV_CONNECT() when they are ready to be enumerated. That is,
(1) initially when bound to the USB driver, and (2) after a USB reset.
* drivers/lcd/nokia6100.c -- A driver for the Nokia 6100 LCD. This driver
* drivers/lcd/nokia6100.c: A driver for the Nokia 6100 LCD. This driver
has not be verified as of the initial check-in.
* configs/olimex-lpc1766stk/nx -- A NX graphics configuration for the Olimex
* configs/olimex-lpc1766stk/nx: A NX graphics configuration for the Olimex
LPC1766-STK board using the Nokia 6100 LCD driver. This configuration has
not been verified as of the initial check-in.
* include/nuttx/spi.h -- the SPI_SETBITS macro was calling the setmode method.
* include/nuttx/spi.h: the SPI_SETBITS macro was calling the setmode method.
This is a very important bug-fix in some usages.
5.16 2011-01-10 Gregory Nutt <spudmonkey@racsa.co.cr>
* include/nuttx/usb -- Created new directory. Moved all usb-related header
* include/nuttx/usb: Created new directory. Moved all usb-related header
files to this new directory. Created a skeleton for a new USB host header
file
* drivers/usbhost -- Add USB host "registry" where connect devices can be
* drivers/usbhost: Add USB host "registry" where connect devices can be
matched with the correct USB class driver.
* arc/arc/src/lpc17xx/lpc17_usbhost.c -- Add a simple USB host driver for
* arc/arc/src/lpc17xx/lpc17_usbhost.c: Add a simple USB host driver for
the NXP lpc17xx.
* drivers/usbhost -- Add generic USB device enumeration logic.
* drivers/usbhost -- Add a USB host class driver for the (Bulk-Only) USB
* drivers/usbhost: Add generic USB device enumeration logic.
* drivers/usbhost: Add a USB host class driver for the (Bulk-Only) USB
Mass Storage Class.
5.17 2011-01-19 Gregory Nutt <spudmonkey@racsa.co.cr>
* include/nuttx/usb -- rename usb_storage.h to storage.h.
* arch/arm/src/lpc17xx/lpc17_usbhost.c -- Add support for low-speed devices.
* drivers/usbhost/usbhost_skeleton.c -- Template for new class drivers
* include/nuttx/usb/hid.h and drivers/usbhost/usbhost_hidkbd.c -- New
* include/nuttx/usb: rename usb_storage.h to storage.h.
* arch/arm/src/lpc17xx/lpc17_usbhost.c: Add support for low-speed devices.
* drivers/usbhost/usbhost_skeleton.c: Template for new class drivers
* include/nuttx/usb/hid.h and drivers/usbhost/usbhost_hidkbd.c: New
files for HID keyboard support.
* arch/arm/src/lpc17xx/lpc17_usbhost.c -- Will now handle multiple
* arch/arm/src/lpc17xx/lpc17_usbhost.c: Will now handle multiple
concurrent transfers on different endpoints (still only one TD per
endpoint). All methods are protected from re-entrancy; lots of re-
structuring in preparation for interrupt endpoint support.
* arch/arm/src/lpc17xx/lpc17_usbhost.c -- Add support for periodic
* arch/arm/src/lpc17xx/lpc17_usbhost.c: Add support for periodic
interrupt transfers.
* examples/hidkbd - Added a simple test for the USB host HID keyboard
* examples/hidkbd: Added a simple test for the USB host HID keyboard
class driver.
* configs/olimex-lpc1766stk/hidkbd - Added a configuration to build the
* configs/olimex-lpc1766stk/hidkbd: Added a configuration to build the
USB host HID keyboard class driver test for the LPC17xx.
* Ran the tool CppCheck (http://sourceforge.net/apps/mediawiki/cppcheck) and
fixed several errors in the code identified by the tool.
@ -1444,37 +1444,37 @@
- Lost SYNACK causes connection reset
- Fix missing UDP stats for sent/received packets
- Added support for Cygwin as development/test platform.
* configs/demo9s12ne64 - Integrate new buildroot-1.9 m8s12x toolchain.
* configs/demo9s12ne64: Integrate new buildroot-1.9 m8s12x toolchain.
* 'uname -o' is used throughout the build logic in bash scripts and also in
Make.defs files in order to distinguish between Cygwin and Linux. However,
the -o option is not standard and is not supported under, for example, OS-X or
Solaris. This was solved by changing all 'uname -o' references to the more
complex: 'uname -o 2>/dev/null || echo "Other"'
* drivers/usbhost/usbhost_enumerate.c -- Add logic to get the VID and PID. This
* drivers/usbhost/usbhost_enumerate.c: Add logic to get the VID and PID. This
is necessary in order to support vendor-specific USB devices.
* examplex/wlan, configs/olimex-lpc1766stk/wlan, drivers/usbhost/usbhost_rtl8187.c,
Add infrastructure to support RTL18187 wireless USB.
* configs/nucleus2g -- backed out USB host changes... wrong board.
* Renamed arc/hc/include/mc9s12ne64 and src/mc9s12ne64 -- m9s12. That name is
* configs/nucleus2g: backed out USB host changes... wrong board.
* Renamed arc/hc/include/mc9s12ne64 and src/mc9s12ne64 to m9s12. That name is
shorter and more general.
* The NuttX repository has been converted to SVN and can now be found here
http://nuttx.svn.sourceforge.net/viewvc/nuttx/
* configs/mbed/hidkbd -- Added USB host support for the mbed LPC1768 board; add
* configs/mbed/hidkbd: Added USB host support for the mbed LPC1768 board; add
a USB host HID keyboard configuraion.
* drivers/usbhost/hid_parser.c -- Leverages the LUFA HID parser written by
* drivers/usbhost/hid_parser.c: Leverages the LUFA HID parser written by
Dean Camera.
* examples/nsh -- Correct an usage of getopt(): If you stop calling getopt()
* examples/nsh: Correct an usage of getopt(): If you stop calling getopt()
before all parameters are parsed, you can leave getopt() in a strange state.
* include/nuttx/fb.h -- Restore missing RGB type that was accidentally removed
* include/nuttx/fb.h: Restore missing RGB type that was accidentally removed
when Nokia 6100 support was added.
* Rename arch/pjrc-8051 to arch/8051
* configs/ne64badge -- Add a configuration for the Future Electronics Group
* configs/ne64badge: Add a configuration for the Future Electronics Group
NE64 Badge development board (Freescale MC9S12NE64)
* Changes contributed by Uros Platise:
- Add support for the STM32F103RET6
- configs/vsn - Support for the ISOTEL NetClamps VSN V1.2 ready2go sensor
- configs/vsn: Support for the ISOTEL NetClamps VSN V1.2 ready2go sensor
network platform
* arch/hc, configs/ne64badge -- Development is complete for the Freescale
* arch/hc, configs/ne64badge: Development is complete for the Freescale
mc9s12ne64 on the Future Electronics Group NE64 /PoE Badge board. Howeve,
this port remains untested until I figure out this BDM / Code Warrior
and paged build thing
@ -1483,7 +1483,7 @@
5.19 2011-03-12 Gregory Nutt <spudmonkey@racsa.co.cr>
* arch/arm/stm32/stm32_idle.c -- During idle times, the STM32 now uses the
* arch/arm/stm32/stm32_idle.c: During idle times, the STM32 now uses the
WFI instruction to sleep in a reduced power mode until the next interrupt
occurs (Contributed by Uros Platise).
* NSH: 'mem' command renamed to 'free'. Output is now more similar to the
@ -1506,84 +1506,84 @@
* drivers/pipes/pipe_common.c: Driver open method was not returning an EINTR
error when it received a signal. Instead, it just re-started the wait. This
makes it impossible to kill a background pipe operation from NSH.
* include/stdint.h -- Correct some errors in conditional compilation (submitted
* include/stdint.h: Correct some errors in conditional compilation (submitted
by Johannes Hampel).
* arch/arm/lpc17xx/lp17_idle.c -- Uses the same logic as the STM32: uses the
* arch/arm/lpc17xx/lp17_idle.c: Uses the same logic as the STM32: uses the
WFI instruction to sleep in a reduced power mode until the next interrupt
occurs.
* configs/olimex-lpc1766stk -- Added an LED encoded to indicate if the LPC1766
* configs/olimex-lpc1766stk: Added an LED encoded to indicate if the LPC1766
is in sleeping.
* examples/mm -- This is a simplified version of the "built-in" memory manager
* examples/mm: This is a simplified version of the "built-in" memory manager
test of mm/mm_test.c. It is simplified because it does not have access to
the internals of the memory manager as does mm/mm_test.c, but it has the
advantage that it runs in the actual NuttX tasking environment (the
mm/mm_test.c only runs in a PC simulation environment).
* drivers/mmcsd_sdio.c/h -- Several corrections submitted by Uros Platise.
* arch/x86 - Provide support for x86 architectures. Support for the i486
* drivers/mmcsd_sdio.c/h: Several corrections submitted by Uros Platise.
* arch/x86: Provide support for x86 architectures. Support for the i486
architecture under QEMU is provided under arch/x86/include/i486,
arch/x86/include/qemu, arch/x86/src/i486, and arch/x86/src/qemu.
* configs/qemu-i486 - "Board" support configurations for verifying the QEME
* configs/qemu-i486: "Board" support configurations for verifying the QEME
i486 port.
* arch/arm/src/stm32/stm32_spi.c -- Correct base address of SPI3 (reported by
* arch/arm/src/stm32/stm32_spi.c: Correct base address of SPI3 (reported by
Uros Platise).
* drivers/mmcsd/mmcsd_sdio.c -- Correct a loop termination condition (also
* drivers/mmcsd/mmcsd_sdio.c: Correct a loop termination condition (also
reported by Uros Platise).
* drivers/mtd/ramtron.c - Driver for SPI-based RAMTRON NVRAM devices FM25V10
* drivers/mtd/ramtron.c: Driver for SPI-based RAMTRON NVRAM devices FM25V10
(and others). Contributed by Uros Platise.
* examples/nsh and tools/mkromfsimg.sh -- Add support for platform-specific
* examples/nsh and tools/mkromfsimg.sh: Add support for platform-specific
ROMFS-based NSH start-up scripts.
* drivers/uart_16550.c and include/nuttx/uart_16550.h - Support for a generic
* drivers/uart_16550.c and include/nuttx/uart_16550.h: Support for a generic
16550 UART.
* configure/qemu-i486/nsh - QEMU NSH example.
* ../apps - The apps directory add-on was created by Uros Platise. It
* configure/qemu-i486/nsh: QEMU NSH example.
* ../apps: The apps directory add-on was created by Uros Platise. It
supports a set of end-user applications than can be executed on top of
NSH. Think of it this way: In a buckled-up embedded application, your
end-user programs will probably have their own dedicated start-up logic.
But, during development, you might want to have you applications
available and executable from the NSH command line. This apps/ addon
(and NSH hooks) was contributed by Uros to accomplish just that.
* sched/sched_waitpid() and include/sys/wait.h - Provides a simple and
* sched/sched_waitpid() and include/sys/wait.h: Provides a simple and
very incomplete implementation of waitpid(). waitpid() is only available
if CONFIG_SCHED_WAITPID is defined in your configuration file.
* sched/atexit.c and sched/exit.c - The atexit function is not frequently
* sched/atexit.c and sched/exit.c: The atexit function is not frequently
used. In order to save a few bytes, it is now conditioned on
CONFIG_SCHED_ATEXIT. It your application is currently using atexit(),
you will need to add CONFIG_SCHED_ATEXT to your configuration file.
* drivers/net/slip.c - Add a SLIP driver (untested on initial check-in).
* configs/olimex-lpc1766stk/slip-httpd - An example that uses SLIP to
* drivers/net/slip.c: Add a SLIP driver (untested on initial check-in).
* configs/olimex-lpc1766stk/slip-httpd: An example that uses SLIP to
provide a serial-port based THTTPD web server.
6.0 2011-03-21 Gregory Nutt <spudmonkey@racsa.co.cr>
* lib/lib_fopen() -- fopen() was not returning the correct errno value
* lib/lib_fopen(): fopen() was not returning the correct errno value
when the underlying open() failed.
* include/net/uip/uip-arch.h -- The uIP interface has been extended
* include/net/uip/uip-arch.h: The uIP interface has been extended
slightly so that drivers can be concurrenly filling and sending
packet buffers. This capability was needed by the SLIP driver.
* drivers/net/slip.c -- Several corrections and some re-design of
* drivers/net/slip.c: Several corrections and some re-design of
of the driver.
* apps/ChangeLog.txt -- the apps/ directory now has its own ChangeLog.
* apps/ChangeLog.txt: the apps/ directory now has its own ChangeLog.
* configs/vsn:
- IDLE LED blinking fix
- Added board power off function
* arch/arm/src/stm32/stm32_gpio.c and stm32_internal.h -- Fixed
* arch/arm/src/stm32/stm32_gpio.c and stm32_internal.h: Fixed
PullUp/Down Input Configuration.
* arch/arm/src/lpc17xx/lpc17_serial.h -- Now supports Auto-RTS and
* arch/arm/src/lpc17xx/lpc17_serial.h: Now supports Auto-RTS and
Auto-CTS modes. This is needed to support SLIP.
* drivers/net/slip.c -- SLIP is now basically functional on the
* drivers/net/slip.c: SLIP is now basically functional on the
LPC17xx with some caveats as described in the TODO list under
LPC17xx.
* arch/x86/include/i486/irq.h -- Fix irqrestore() macro... it was not
* arch/x86/include/i486/irq.h: Fix irqrestore() macro... it was not
correctly re-enabling interrupts.
* arch/x86/src - Fix numerous problems with i486/QEMU context
* arch/x86/src: Fix numerous problems with i486/QEMU context
switching. Basically, the logic was missing the cases to handle
the differing stack frames when a priority change occurs and when
no priority change occurs.
* configs/qemu-i486/ostest and nsh -- The QEMU i486 port is complete.
* configs/qemu-i486/ostest and nsh: The QEMU i486 port is complete.
it now passes the OS test and supports the NuttShell (NSH).
* misc/drivers -- Created a new directory to hold non-BSD licensed
* misc/drivers: Created a new directory to hold non-BSD licensed
drivers that may be added into NuttX via an installation script.
* drivers/usbhost/usbhost_rtl8187.c -- A decision was made to
* drivers/usbhost/usbhost_rtl8187.c: A decision was made to
incorporate code taken from the Linux kernel. That changes the
licensing on this module to GPL. To avoid licensing contamination,
this driver was moved to misc/drivers/rtl8187x *prior* to adding
@ -1591,36 +1591,36 @@
where the GPL driver(s) can be re-installed into the NuttX source
tree. By re-installing the driver, you agree to the GPL licsensing
and all of its implications.
* Makefile, apps/Makefile, tools/configure.sh -- add logic to copy
* Makefile, apps/Makefile, tools/configure.sh: add logic to copy
configs/<board>/<config>/appdir to apps/.config and to simply the
application configuration logic.
* examples/nsh and apps/nshlib - Move the core NuttShell (NSH) logic
* examples/nsh and apps/nshlib: Move the core NuttShell (NSH) logic
out of the exemples directory and into the apps/ directory where
it belongs.
* apps/Makefile and configs/*/appconfig - Use '=' as the delimiter
* apps/Makefile and configs/*/appconfig: Use '=' as the delimiter
instead of '/' so that sub-directories in apps/ can be used.
* apps/vsn - Move all VSN apps to apps/vsn.
* apps/vsn: Move all VSN apps to apps/vsn.
* nuttx/examples moved to apps/examples
6.1 2011-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
* arch/arm/include/lpc17xx/irq.h and arch/arm/src/lpc17xx/lpc17_gpio*.c
-- Fix several bugs in the GPIO interrupt logic. Submited by
* arch/arm/include/lpc17xx/irq.h and arch/arm/src/lpc17xx/lpc17_gpio*.c:
Fix several bugs in the GPIO interrupt logic. Submited by
Decio Renno.
* Initialization for the CONFIG_APPS_DIR is now supported during the
earlier, 'context' build phase.
* arch/arm/src/lpc17_gpioint.c -- Finish coding of the LPC17xx GPIO
* arch/arm/src/lpc17_gpioint.c: Finish coding of the LPC17xx GPIO
interrupt logic.
* net/netdev_unregister.c -- Add capability to un-register a network
* net/netdev_unregister.c: Add capability to un-register a network
device.
* drivers/mmcsd/mmcsd_sdio.c: extra effort to correctly handle cases
without the SDcard (but one issue still exists in STM32)
* arch/arm/src/stm32/stm32_tim.*: Added basic timer support without
output PWMs and interrupt logic
* arch/arm/src/stm32/stm32_tim.*: Added basic timer support TIM1..TIM8
with output PWMs and interrupt logic
* config/vsn/src: added basic support for Sensor Interface (GPIO and
Power Output, and the sif utility program)
* fs/ -- Reorgnize header so that file systems can be built outside
PWM Power Output, and the sif utility program)
* fs/: Reorgnize header so that file systems can be built outside
of the nuttx source tree
* apps/namedapp/binfs.c -- Create a tiny filesystem that can be used
* apps/namedapp/binfs.c: Create a tiny filesystem that can be used
to show the internal named apps under /bin.

22
Documentation/NuttX.html
View file

@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: March 24, 2011</p>
<p>Last Updated: March 28, 2011</p>
</td>
</tr>
</table>
@ -2068,7 +2068,7 @@ Other memory:
</table>
<ul><pre>
nuttx-6.1 2011-03-21 Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
nuttx-6.0 2011-03-21 Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
* lib/lib_fopen() -- fopen() was not returning the correct errno value
when the underlying open() failed.
@ -2157,21 +2157,25 @@ buildroot-1.9 2011-02-10 &lt;spudmonkey@racsa.co.cr&gt;
<ul><pre>
nuttx-6.1 2011-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
* arch/arm/include/lpc17xx/irq.h and arch/arm/src/lpc17xx/lpc17_gpio*.c
-- Fix several bugs in the GPIO interrupt logic. Submited by
* arch/arm/include/lpc17xx/irq.h and arch/arm/src/lpc17xx/lpc17_gpio*.c:
Fix several bugs in the GPIO interrupt logic. Submited by
Decio Renno.
* Initialization for the CONFIG_APPS_DIR is now supported during the
earlier, 'context' build phase.
* arch/arm/src/lpc17_gpioint.c -- Finish coding of the LPC17xx GPIO
* arch/arm/src/lpc17_gpioint.c: Finish coding of the LPC17xx GPIO
interrupt logic.
* net/netdev_unregister.c -- Add capability to un-register a network
* net/netdev_unregister.c: Add capability to un-register a network
device.
* drivers/mmcsd/mmcsd_sdio.c: extra effort to correctly handle cases
without the SDcard (but one issue still exists in STM32)
* arch/arm/src/stm32/stm32_tim.*: Added basic timer support without
output PWMs and interrupt logic
* arch/arm/src/stm32/stm32_tim.*: Added basic timer support TIM1..TIM8
with output PWMs and interrupt logic
* config/vsn/src: added basic support for Sensor Interface (GPIO and
Power Output, and the sif utility program)
PWM Power Output, and the sif utility program)
* fs/: Reorgnize header so that file systems can be built outside
of the nuttx source tree
* apps/namedapp/binfs.c: Create a tiny filesystem that can be used
to show the internal named apps under /bin.
apps-6.1 2011-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;

15
arch/arm/src/stm32/chip/stm32f103re_pinmap.h
View file

@ -295,24 +295,17 @@
/* CAN */
#if defined(CONFIG_STM32_CAN1_FULL_REMAP)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
#elif defined(CONFIG_STM32_CAN1_PARTIAL_REMAP)
#if defined(CONFIG_STM32_CAN1_REMAP1)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
#elif defined(CONFIG_STM32_CAN1_REMAP2)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
#else
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
#endif
#if defined(CONFIG_STM32_CAN2_REMAP)
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
#else
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
#endif
/* SDIO */

52
arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
View file

@ -48,6 +48,8 @@
/* Alternate Pin Functions: */
/* TIMERS */
#if defined(CONFIG_STM32_TIM1_FULL_REMAP)
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN7)
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN9)
@ -183,9 +185,31 @@
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
#endif
#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM5_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM8_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM8_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM8_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM8_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM8_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM8_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM8_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM8_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM8_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM8_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
/* USART */
#if defined(CONFIG_STM32_USART1_REMAP)
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
@ -228,6 +252,8 @@
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
#endif
/* SPI */
#if defined(CONFIG_STM32_SPI1_REMAP)
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
@ -252,6 +278,8 @@
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
#endif
/* I2C */
#if defined(CONFIG_STM32_I2C1_REMAP)
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
@ -260,25 +288,25 @@
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
#endif
#if defined(CONFIG_STM32_CAN1_FULL_REMAP)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
#elif defined(CONFIG_STM32_CAN1_PARTIAL_REMAP)
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
/* CAN */
#if defined(CONFIG_STM32_CAN1_REMAP1)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
#elif defined(CONFIG_STM32_CAN1_REMAP2)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
#else
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
#endif
#if defined(CONFIG_STM32_CAN2_REMAP)
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
#else
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
#endif
/* FSMC: CF */
#define GPIO_CF_A0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN0)

302
arch/arm/src/stm32/stm32_i2c.c
View file

@ -79,7 +79,7 @@
#include "stm32_rcc.h"
#include "stm32_i2c.h"
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C1)
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2)
/************************************************************************************
* Private Types
@ -92,6 +92,9 @@ struct stm32_i2c_priv_s {
uint32_t base;
int refs;
sem_t sem;
uint8_t msgc;
FAR struct i2c_msg_s *msgv;
};
@ -103,9 +106,28 @@ struct stm32_i2c_inst_s {
uint32_t frequency;
int address;
uint16_t flags;
};
/************************************************************************************
* Private Data
************************************************************************************/
#if CONFIG_STM32_I2C1
struct stm32_i2c_priv_s stm32_i2c1_priv = {
.base = STM32_I2C1_BASE,
.refs = 0
};
#endif
#if CONFIG_STM32_I2C2
struct stm32_i2c_priv_s stm32_i2c2_priv = {
.base = STM32_I2C2_BASE,
.refs = 0
};
#endif
/************************************************************************************
* Private Functions
@ -159,7 +181,7 @@ void inline stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev)
}
static void stm32_i2c_setclock(FAR struct i2c_dev_s *inst)
static void stm32_i2c_setclock(FAR struct i2c_dev_s *inst, uint32_t frequency)
{
/* Disable Peripheral if rising time is to be changed,
* and restore state on return. */
@ -171,13 +193,13 @@ static void stm32_i2c_setclock(FAR struct i2c_dev_s *inst)
/* Update timing and control registers */
if (((struct stm32_i2c_inst_s *)inst)->frequency < 400e3) {
if (frequency < 400e3) {
/* Speed: 100 kHz
* Risetime: 1000 ns
* Duty: t_low / t_high = 1
*/
stm32_i2c_putreg(inst, STM32_I2C_CCR_OFFSET, STM32_BOARD_HCLK / 200000);
stm32_i2c_putreg(inst, STM32_I2C_CCR_OFFSET, STM32_BOARD_HCLK/200000);
stm32_i2c_putreg(inst, STM32_I2C_TRISE_OFFSET, 1 + STM32_BOARD_HCLK/1000000);
}
else {
@ -186,7 +208,7 @@ static void stm32_i2c_setclock(FAR struct i2c_dev_s *inst)
* Risetime: 1000 ns ??? \todo check rise time for 400 kHz devices
* Duty: t_low / t_high = 2
*/
stm32_i2c_putreg(inst, STM32_I2C_CCR_OFFSET, STM32_BOARD_HCLK / 1200000);
stm32_i2c_putreg(inst, STM32_I2C_CCR_OFFSET, STM32_BOARD_HCLK/1200000);
stm32_i2c_putreg(inst, STM32_I2C_TRISE_OFFSET, 1 + STM32_BOARD_HCLK/1000000);
}
@ -197,23 +219,103 @@ static void stm32_i2c_setclock(FAR struct i2c_dev_s *inst)
}
static inline void stm32_i2c_sendstart(FAR struct i2c_dev_s *inst)
{
stm32_i2c_modifyreg(inst, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_START);
}
static inline void stm32_i2c_sendstop(FAR struct i2c_dev_s *inst)
{
stm32_i2c_modifyreg(inst, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_STOP);
}
/************************************************************************************
* Interrupt Service Routines
************************************************************************************/
static int stm32_i2c_event_isr(struct stm32_i2c_priv_s * priv)
{
return OK;
}
static int stm32_i2c_error_isr(struct stm32_i2c_priv_s * priv)
{
return OK;
}
/* Decode ***************************************************************************/
#if CONFIG_STM32_I2C1
static int stm32_i2c1_event_isr(int irq, void *context)
{
return stm32_i2c_event_isr(&stm32_i2c1_priv);
}
static int stm32_i2c1_error_isr(int irq, void *context)
{
return stm32_i2c_error_isr(&stm32_i2c1_priv);
}
#endif
#if CONFIG_STM32_I2C2
static int stm32_i2c2_event_isr(int irq, void *context)
{
return stm32_i2c_event_isr(&stm32_i2c2_priv);
}
static int stm32_i2c2_error_isr(int irq, void *context)
{
return stm32_i2c_error_isr(&stm32_i2c1_priv);
}
#endif
/************************************************************************************
* Private Initialization and Deinitialization
************************************************************************************/
/** Setup the I2C hardware, ready for operation with defaults */
static int stm32_i2c_init(FAR struct i2c_dev_s *inst)
{
/* Power-up and configure GPIOs */
switch( ((struct stm32_i2c_inst_s *)inst)->priv->base ) {
#if CONFIG_STM32_I2C1
case STM32_I2C1_BASE:
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C1EN);
stm32_configgpio(GPIO_I2C1_SCL);
stm32_configgpio(GPIO_I2C1_SDA);
break;
if (stm32_configgpio(GPIO_I2C1_SCL)==ERROR) return ERROR;
if (stm32_configgpio(GPIO_I2C1_SDA)==ERROR) {
stm32_unconfiggpio(GPIO_I2C1_SCL);
return ERROR;
}
irq_attach(STM32_IRQ_I2C1EV, stm32_i2c1_event_isr);
irq_attach(STM32_IRQ_I2C1ER, stm32_i2c1_error_isr);
up_enable_irq(STM32_IRQ_I2C1EV);
up_enable_irq(STM32_IRQ_I2C1ER);
break;
#endif
#if CONFIG_STM32_I2C2
case STM32_I2C2_BASE:
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C2EN);
stm32_configgpio(GPIO_I2C2_SCL);
stm32_configgpio(GPIO_I2C2_SDA);
if (stm32_configgpio(GPIO_I2C2_SCL)==ERROR) return ERROR;
if (stm32_configgpio(GPIO_I2C2_SDA)==ERROR) {
stm32_unconfiggpio(GPIO_I2C2_SCL);
return ERROR;
}
irq_attach(STM32_IRQ_I2C2EV, stm32_i2c2_event_isr);
irq_attach(STM32_IRQ_I2C2ER, stm32_i2c2_error_isr);
up_enable_irq(STM32_IRQ_I2C2EV);
up_enable_irq(STM32_IRQ_I2C2ER);
break;
#endif
default: return ERROR;
}
@ -221,18 +323,14 @@ static int stm32_i2c_init(FAR struct i2c_dev_s *inst)
/* Set peripheral frequency, where it must be at least 2 MHz
* for 100 kHz or 4 MHz for 400 kHz. Enable interrupt generation.
*/
#if STM32_BOARD_HCLK < 4000000
# error STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 100/400 kHz operation.
#endif
stm32_i2c_putreg(inst, STM32_I2C_CR2_OFFSET,
I2C_CR2_ITERREN | I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN |
(STM32_BOARD_HCLK / 1000000)
);
stm32_i2c_setclock(inst);
stm32_i2c_setclock(inst, 100000);
/* Enable I2C */
stm32_i2c_putreg(inst, STM32_I2C_CR1_OFFSET, I2C_CR1_PE);
@ -249,17 +347,34 @@ static int stm32_i2c_deinit(FAR struct i2c_dev_s *inst)
stm32_i2c_putreg(inst, STM32_I2C_CR1_OFFSET, 0);
switch( ((struct stm32_i2c_inst_s *)inst)->priv->base ) {
#if CONFIG_STM32_I2C1
case STM32_I2C1_BASE:
stm32_unconfiggpio(GPIO_I2C1_SCL);
stm32_unconfiggpio(GPIO_I2C1_SDA);
up_disable_irq(STM32_IRQ_I2C1EV);
up_disable_irq(STM32_IRQ_I2C1ER);
irq_detach(STM32_IRQ_I2C1EV);
irq_detach(STM32_IRQ_I2C1ER);
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_I2C1EN, 0);
break;
#endif
#if CONFIG_STM32_I2C2
case STM32_I2C2_BASE:
stm32_unconfiggpio(GPIO_I2C2_SCL);
stm32_unconfiggpio(GPIO_I2C2_SDA);
up_disable_irq(STM32_IRQ_I2C1EV);
up_disable_irq(STM32_IRQ_I2C1ER);
irq_detach(STM32_IRQ_I2C1EV);
irq_detach(STM32_IRQ_I2C1ER);
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_I2C2EN, 0);
break;
#endif
default: return ERROR;
}
@ -268,24 +383,6 @@ static int stm32_i2c_deinit(FAR struct i2c_dev_s *inst)
}
/************************************************************************************
* Interrupt Service Routines
************************************************************************************/
static int stm32_i2c1_isr(int irq, void *context)
{
// ACK before return!
return OK;
}
static int stm32_i2c2_isr(int irq, void *context)
{
// ACK before return!
return OK;
}
/************************************************************************************
* Device Driver OPS - Blocking Type
************************************************************************************/
@ -294,8 +391,12 @@ uint32_t stm32_i2c_setfrequency(FAR struct i2c_dev_s *inst, uint32_t frequency)
{
stm32_i2c_sem_wait(inst);
#if STM32_BOARD_HCLK < 4000000
((struct stm32_i2c_inst_s *)inst)->frequency = 100000;
#else
((struct stm32_i2c_inst_s *)inst)->frequency = frequency;
#endif
stm32_i2c_sem_post(inst);
return ((struct stm32_i2c_inst_s *)inst)->frequency;
}
@ -306,42 +407,96 @@ int stm32_i2c_setaddress(FAR struct i2c_dev_s *inst, int addr, int nbits)
stm32_i2c_sem_wait(inst);
((struct stm32_i2c_inst_s *)inst)->address = addr;
((struct stm32_i2c_inst_s *)inst)->flags = (nbits == 10) ? I2C_M_TEN : 0;
stm32_i2c_sem_post(inst);
return OK;
}
int stm32_i2c_process(FAR struct i2c_dev_s *inst, FAR struct i2c_msg_s *msgs, int count)
{
/* The semaphore already ensures that I2C is ours, since we do not yet support
* non-blocking operation.
*/
((struct stm32_i2c_inst_s *)inst)->priv->msgv = msgs;
((struct stm32_i2c_inst_s *)inst)->priv->msgc = count;
stm32_i2c_setclock(inst, ((struct stm32_i2c_inst_s *)inst)->frequency);
stm32_i2c_sendstart(inst);
/* Trigger start condition, then the process moves into the ISR,
* until semaphore is posted.
*/
stm32_i2c_sem_wait(inst); /* wait again for the semaphore and */
stm32_i2c_sem_post(inst); /* release it immediately. */
return OK;
}
int stm32_i2c_write(FAR struct i2c_dev_s *inst, const uint8_t *buffer, int buflen)
{
stm32_i2c_sem_wait(inst);
stm32_i2c_sem_wait(inst); /* ensure that address or flags don't change meanwhile */
stm32_i2c_setclock(inst);
struct i2c_msg_s msgv = {
.addr = ((struct stm32_i2c_inst_s *)inst)->address,
.flags = ((struct stm32_i2c_inst_s *)inst)->flags,
.buffer = (uint8_t *)buffer,
.length = buflen
};
stm32_i2c_sem_post(inst);
return OK;
return stm32_i2c_process(inst, &msgv, 1);
}
int stm32_i2c_read(FAR struct i2c_dev_s *inst, uint8_t *buffer, int buflen)
{
stm32_i2c_sem_wait(inst);
stm32_i2c_sem_wait(inst); /* ensure that address or flags don't change meanwhile */
stm32_i2c_setclock(inst);
struct i2c_msg_s msgv = {
.addr = ((struct stm32_i2c_inst_s *)inst)->address,
.flags = ((struct stm32_i2c_inst_s *)inst)->flags | I2C_M_READ,
.buffer = buffer,
.length = buflen
};
stm32_i2c_sem_post(inst);
return OK;
return stm32_i2c_process(inst, &msgv, 1);
}
#ifdef CONFIG_I2C_WRITEREAD
int stm32_i2c_writeread(FAR struct i2c_dev_s *inst, const uint8_t *wbuffer, int wbuflen,
uint8_t *rbuffer, int rbuflen)
{
stm32_i2c_sem_wait(inst); /* ensure that address or flags don't change meanwhile */
struct i2c_msg_s msgv[2] = {
{
.addr = ((struct stm32_i2c_inst_s *)inst)->address,
.flags = ((struct stm32_i2c_inst_s *)inst)->flags,
.buffer = (uint8_t *)wbuffer, /* this is really ugly, sorry const ... */
.length = wbuflen
},
{
.addr = ((struct stm32_i2c_inst_s *)inst)->address,
.flags = ((struct stm32_i2c_inst_s *)inst)->flags | I2C_M_READ,
.buffer = rbuffer,
.length = rbuflen
}
};
return stm32_i2c_process(inst, msgv, 2);
}
#endif
#ifdef CONFIG_I2C_TRANSFER
int stm32_i2c_transfer(FAR struct i2c_dev_s *inst, FAR struct i2c_msg_s *msgs, int count)
{
stm32_i2c_sem_wait(inst);
stm32_i2c_sem_post(inst);
return OK;
stm32_i2c_sem_wait(inst); /* ensure that address or flags don't change meanwhile */
return stm32_i2c_process(inst, msgs, count);
}
#endif
@ -351,29 +506,23 @@ int stm32_i2c_transfer(FAR struct i2c_dev_s *inst, FAR struct i2c_msg_s *msgs, i
************************************************************************************/
struct i2c_ops_s stm32_i2c_ops = {
.setfrequency = stm32_i2c_setfrequency,
.setaddress = stm32_i2c_setaddress,
.write = stm32_i2c_write,
.read = stm32_i2c_read
.setfrequency = stm32_i2c_setfrequency,
.setaddress = stm32_i2c_setaddress,
.write = stm32_i2c_write,
.read = stm32_i2c_read,
#ifdef CONFIG_I2C_WRITEREAD
.writeread = stm32_i2c_writeread
#endif
#ifdef CONFIG_I2C_TRANSFER
, .transfer = stm32_i2c_transfer
, .transfer = stm32_i2c_transfer
#endif
#ifdef CONFIG_I2C_SLAVE
, .setownaddress = stm32_i2c_setownaddress,
.registercallback = stm32_i2c_registercallback
#endif
};
struct stm32_i2c_priv_s stm32_i2c1_priv = {
.base = STM32_I2C1_BASE,
.refs = 0
};
struct stm32_i2c_priv_s stm32_i2c2_priv = {
.base = STM32_I2C2_BASE,
.refs = 0
};
/************************************************************************************
* Public Function - Initialization
************************************************************************************/
@ -383,12 +532,25 @@ FAR struct i2c_dev_s * up_i2cinitialize(int port)
struct stm32_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */
struct stm32_i2c_inst_s * inst = NULL; /* device, single instance */
int irqs;
#if STM32_BOARD_HCLK < 4000000
# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
#endif
#if STM32_BOARD_HCLK < 2000000
# warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
return NULL;
#endif
/* Get structure and enable power */
switch(port) {
#if CONFIG_STM32_I2C1
case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break;
#endif
#if CONFIG_STM32_I2C2
case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break;
#endif
default: return NULL;
}
@ -402,6 +564,7 @@ FAR struct i2c_dev_s * up_i2cinitialize(int port)
inst->priv = priv;
inst->frequency = 100e3;
inst->address = 0;
inst->flags = 0;
/* Init private data for the first time, increment refs count,
* power-up hardware and configure GPIOs.
@ -453,5 +616,4 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * inst)
return OK;
}
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C1 */
#endif /* defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C2) */

2
arch/arm/src/stm32/stm32_i2c.h
View file

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_i2c.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without

30
arch/arm/src/stm32/stm32_rcc.c
View file

@ -164,39 +164,45 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR);
#if CONFIG_STM32_TIM2
/* Timer 2 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM2EN;
#endif
#endif
#if CONFIG_STM32_TIM3
/* Timer 3 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM3EN;
#endif
#endif
#if CONFIG_STM32_TIM4
/* Timer 4 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM4EN;
#endif
#endif
#if CONFIG_STM32_TIM5
/* Timer 5 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM5EN;
#endif
#endif
#if CONFIG_STM32_TIM6
/* Timer 6 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM6EN;
#endif
#endif
#if CONFIG_STM32_TIM7
/* Timer 7 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM7EN;
#endif
#endif
#if CONFIG_STM32_WWDG
/* Window Watchdog clock enable */
@ -242,15 +248,17 @@ static inline void rcc_enableapb1(void)
#if CONFIG_STM32_I2C1
/* I2C 1 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_I2C1EN;
#endif
#endif
#if CONFIG_STM32_I2C2
/* I2C 2 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_I2C2EN;
#endif
#endif
#if CONFIG_STM32_USB
/* USB clock enable */
@ -333,9 +341,10 @@ static inline void rcc_enableapb2(void)
#if CONFIG_STM32_TIM1
/* TIM1 Timer clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_TIM1EN;
#endif
#endif
#if CONFIG_STM32_SPI1
/* SPI 1 clock enable */
@ -345,9 +354,10 @@ static inline void rcc_enableapb2(void)
#if CONFIG_STM32_TIM8
/* TIM8 Timer clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_TIM8EN;
#endif
#endif
#if CONFIG_STM32_USART1
/* USART1 clock enable */

177
arch/arm/src/stm32/stm32_tim.c
View file

@ -59,11 +59,9 @@
#include "stm32_gpio.h"
#include "stm32_tim.h"
#define getreg16(a) (*(volatile uint16_t *)(a))
#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v))
#if defined(CONFIG_STM32_TIM5) && defined(CONFIG_STM32_TIM8)
#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM3) || \
defined(CONFIG_STM32_TIM4) || defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8)
/************************************************************************************
* Private Types
@ -74,9 +72,7 @@
struct stm32_tim_priv_s {
struct stm32_tim_ops_s *ops;
stm32_tim_mode_t mode;
uint32_t base; /** TIMn base address */
uint8_t irqno; /** TIM IRQ number */
uint32_t base; /** TIMn base address */
};
@ -205,12 +201,36 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, int (*handler)(int
ASSERT(source==0);
switch( ((struct stm32_tim_priv_s *)dev)->base ) {
#if CONFIG_STM32_TIM2
case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break;
#endif
#if CONFIG_STM32_TIM3
case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break;
#endif
#if CONFIG_STM32_TIM4
case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break;
#endif
#if CONFIG_STM32_TIM5
case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break;
#endif
#if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6
case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break;
#endif
#endif
#if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7
case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break;
#endif
#endif
#if STM32_NATIM > 0
/** \todo add support for multiple sources and callbacks */
#if CONFIG_STM32_TIM1
case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break;
#endif
#if CONFIG_STM32_TIM8
case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break;
#endif
#endif
default: return ERROR;
}
@ -381,7 +401,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
/* set GPIO */
switch( ((struct stm32_tim_priv_s *)dev)->base ) {
#if CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch(channel) {
case 0: stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break;
@ -390,7 +410,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
case 3: stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break;
}
break;
#endif
#if CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch(channel) {
case 0: stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break;
@ -399,7 +420,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
case 3: stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break;
}
break;
#endif
#if CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
switch(channel) {
case 0: stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break;
@ -408,7 +430,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
case 3: stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break;
}
break;
#endif
#if CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
switch(channel) {
case 0: stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break;
@ -417,8 +440,10 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
case 3: stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break;
}
break;
#endif
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch(channel) {
case 0: stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
@ -427,7 +452,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
case 3: stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
}
break;
#endif
#if CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
switch(channel) {
case 0: stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
@ -436,6 +462,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
case 3: stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
}
break;
#endif
#endif
default: return ERROR;
}
@ -497,26 +524,75 @@ struct stm32_tim_ops_s stm32_tim_ops = {
.ackint = &stm32_tim_ackint
};
#if CONFIG_STM32_TIM2
struct stm32_tim_priv_s stm32_tim2_priv = {
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM2_BASE,
};
#endif
#if CONFIG_STM32_TIM3
struct stm32_tim_priv_s stm32_tim3_priv = {
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM3_BASE,
};
#endif
#if CONFIG_STM32_TIM4
struct stm32_tim_priv_s stm32_tim4_priv = {
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM4_BASE,
};
#endif
#if CONFIG_STM32_TIM5
struct stm32_tim_priv_s stm32_tim5_priv = {
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM5_BASE,
};
#endif
#if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6
struct stm32_tim_priv_s stm32_tim6_priv = {
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM6_BASE,
};
#endif
#endif
#if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim7_priv = {
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM7_BASE,
};
#endif
#endif
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim1_priv = {
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM1_BASE,
};
#endif
#if CONFIG_STM32_TIM8
struct stm32_tim_priv_s stm32_tim8_priv = {
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM8_BASE,
};
#endif
#endif
@ -532,21 +608,61 @@ FAR struct stm32_tim_dev_s * stm32_tim_init(int timer)
/* Get structure and enable power */
switch(timer) {
#if CONFIG_STM32_TIM2
case 2:
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN);
break;
#endif
#if CONFIG_STM32_TIM3
case 3:
dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
break;
#endif
#if CONFIG_STM32_TIM4
case 4:
dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN);
break;
#endif
#if CONFIG_STM32_TIM5
case 5:
dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
break;
#endif
#if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6
case 6:
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN);
break;
#endif
#endif
#if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7
case 7:
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN);
break;
#endif
#endif
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM1
case 1:
dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
break;
#endif
#if CONFIG_STM32_TIM8
case 8:
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
#endif
default: return NULL;
}
@ -562,6 +678,7 @@ FAR struct stm32_tim_dev_s * stm32_tim_init(int timer)
}
/** \todo Detach interrupts, and close down all TIM Channels */
int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
{
ASSERT(dev);
@ -569,11 +686,36 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
/* Disable power */
switch( ((struct stm32_tim_priv_s *)dev)->base ) {
#if CONFIG_STM32_TIM2
case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break;
#endif
#if CONFIG_STM32_TIM3
case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break;
#endif
#if CONFIG_STM32_TIM4
case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break;
#endif
#if CONFIG_STM32_TIM5
case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break;
#endif
#if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6
case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break;
#endif
#endif
#if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7
case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break;
#endif
#endif
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM1
case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break;
#endif
#if CONFIG_STM32_TIM8
case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break;
#endif
#endif
default: return ERROR;
}
@ -585,5 +727,4 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
return OK;
}
#endif /* CONFIG_STM32_TIM5 && CONFIG_STM32_TIM8 */
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */

48
configs/stm3210e-eval/include/board.h
View file

@ -57,39 +57,47 @@
/* On-board crystal frequency is 8MHz (HSE) */
#define STM32_BOARD_XTAL 8000000ul
#define STM32_BOARD_XTAL 8000000ul
/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
#define STM32_CFGR_PLLXTPRE 0
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
#define STM32_CFGR_PLLXTPRE 0
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
/* Use the PLL and set the SYSCLK source to be the PLL */
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
/* AHB clock (HCLK) is SYSCLK (72MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* USB divider -- Divide PLL clock by 1.5 */
#define STM32_CFGR_USBPRE 0
#define STM32_CFGR_USBPRE 0
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
@ -99,16 +107,16 @@
* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
*/
#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
@ -116,9 +124,9 @@
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* LED definitions ******************************************************************/

10
configs/vsn/nsh/defconfig
View file

@ -503,6 +503,13 @@ CONFIG_PREALLOC_TIMERS=4
CONFIG_FS_FAT=y
CONFIG_FS_ROMFS=y
#
# I2C Settings
#
CONFIG_I2C_WRITEREAD=y
CONFIG_I2C_TRANSFER=y
CONFIG_I2C_SLAVE=n
#
# SPI-based MMC/SD driver
#
@ -858,3 +865,6 @@ CONFIG_HEAP_SIZE=
# Application configuration
CONFIG_APPS_DIR="../apps"
# Provide /dev/ramX and then: mount -t binfs /dev/ram0 /bin
CONFIG_APPS_BINDIR=y

24
configs/vsn/src/rtac.c
View file

@ -80,3 +80,27 @@ int rtac_waitg(int group, int time)
{
// blocking variant of rtac_exec with timeout if specified
}
/** Power optimization of base systick timer
*
* 1. Simple method to skip wake-ups:
* - ask timers about the min. period, which is Ns * systick
* - set the preload register with floor(Ns) * DEFAULT_PRELOAD
* - on wake-up call routines Ns times.
*
* 2. If intermediate ISR occuried then:
* - check how many periods have passed by reading the counter: Np
* - set the new counter value as (counter % DEFAULT_PRELOAD)
* - call timer routines Np times; the next call is as usual, starting
* at 1. point above
*
* This is okay if ISR's do not read timers, if they read timers then:
* - on ISR wake-up the code described under 2. must be called first
* (on wake-up from IDLE)
*
* BUT: the problem is that SYSTICK does not run in Stop mode but RTC
* only, so it might be better to replace SYSTICK with RTAC (this
* module) and do the job above, permitting ultra low power modes of
* 25 uA or further down to 5 uA.
*/

19
configs/vsn/src/sif.c
View file

@ -272,6 +272,25 @@ int sif_gpios_unlock(vsn_sif_state_t peripheral)
}
/****************************************************************************
* ST LIS331DL
****************************************************************************/
void st_lis331dl_open(void)
{
}
void st_lis331dl_config(void)
{
}
void st_lis331dl_getreadings(void)
{
}
/****************************************************************************
* Analog Outputs
****************************************************************************/

38
include/nuttx/i2c.h
View file

@ -1,7 +1,7 @@
/****************************************************************************
* include/nuttx/i2c.h
*
* Copyright(C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright(C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -109,12 +109,38 @@
* nbits - The number of address bits provided (7 or 10)
*
* Returned Value:
* Returns the actual frequency selected
* Returns OK on success; a negated errno on failure.
*
****************************************************************************/
#define I2C_SETADDRESS(d,f,b) ((d)->ops->setaddress(d,f,b))
/****************************************************************************
* Name: I2C_SETOWNADDRESS
*
* Description:
* Set our own I2C address. Calling this function enables Slave mode and
* disables Master mode on given instance (note that I2C is a bus, where
* multiple masters and slave may be handled by one device driver).
*
* One may register callback to be notifyed about reception. During the
* slave mode reception, the function READ and WRITE must be used to
* to handle reads and writes from a master.
*
* Input Parameters:
* dev - Device-specific state data
* address - Our own slave address; If it is 0x00, then the device driver
* listens to general call
* nbits - The number of address bits provided (7 or 10)
*
* Returned Value:
* OK on valid address and if the same address has not been assigned
* to other existance sharing the same port. Otherwise ERROR is returned.
*
****************************************************************************/
#define I2C_SETOWNADDRESS(d,f,b) ((d)->ops->setownaddress(d,f,b))
/****************************************************************************
* Name: I2C_WRITE
*
@ -192,9 +218,17 @@ struct i2c_ops_s
int (*setaddress)(FAR struct i2c_dev_s *dev, int addr, int nbits);
int (*write)(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen);
int (*read)(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen);
#ifdef CONFIG_I2C_WRITEREAD
int (*writeread)(FAR struct i2c_dev_s *inst, const uint8_t *wbuffer, int wbuflen,
uint8_t *rbuffer, int rbuflen);
#endif
#ifdef CONFIG_I2C_TRANSFER
int (*transfer)(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count);
#endif
#ifdef CONFIG_I2C_SLAVE
int (*setownaddress)(FAR struct i2c_dev_s *dev, int addr, int nbits);
int (*registercallback)(FAR struct i2c_dev_s *dev, int (*callback)(void) );
#endif
};
/* I2C transaction segment beginning with a START. A number of these can

2
include/sched.h
View file

@ -66,7 +66,7 @@
/* Non-standard Helper **********************************************************/
/* One processor family supported by NuttX has a single, fixed hardware stack.
* That is the 8051 family. So for that family only, there is a variant form
* of task_create() that does not task a stack size of a parameter. The following
* of task_create() that does not take a stack size parameter. The following
* helper macro is provided to work around the ugliness of that exception.
*/