diff --git a/arch/arm64/src/a64/a64_timer.c b/arch/arm64/src/a64/a64_timer.c
index 308c9e6318..9507a97773 100644
--- a/arch/arm64/src/a64/a64_timer.c
+++ b/arch/arm64/src/a64/a64_timer.c
@@ -36,3 +36,8 @@ void up_timer_initialize(void)
 {
   up_alarm_set_lowerhalf(arm64_oneshot_initialize());
 }
+
+void arm64_timer_secondary_init(void)
+{
+  arm64_oneshot_secondary_init();
+}
diff --git a/arch/arm64/src/bcm2711/bcm2711_timer.c b/arch/arm64/src/bcm2711/bcm2711_timer.c
index 5fe6f30b8c..6759d6f64e 100644
--- a/arch/arm64/src/bcm2711/bcm2711_timer.c
+++ b/arch/arm64/src/bcm2711/bcm2711_timer.c
@@ -35,3 +35,7 @@ void up_timer_initialize(void)
   up_alarm_set_lowerhalf(arm64_oneshot_initialize());
 }
 
+void arm64_timer_secondary_init(void)
+{
+  arm64_oneshot_secondary_init();
+}
diff --git a/arch/arm64/src/common/arm64_arch_timer.c b/arch/arm64/src/common/arm64_arch_timer.c
index 0aac7556b9..5b740f2ec8 100644
--- a/arch/arm64/src/common/arm64_arch_timer.c
+++ b/arch/arm64/src/common/arm64_arch_timer.c
@@ -72,7 +72,6 @@ struct arm64_oneshot_lowerhalf_s
   void *arg;                          /* Argument that is passed to the handler */
   uint64_t cycle_per_tick;            /* cycle per tick */
   oneshot_callback_t callback;        /* Internal handler that receives callback */
-  bool init[CONFIG_SMP_NCPUS];        /* True: timer is init */
 
   /* which cpu timer is running, -1 indicate timer stoppd */
 
@@ -274,18 +273,6 @@ static int arm64_tick_start(struct oneshot_lowerhalf_s *lower,
   priv->callback = callback;
   priv->arg = arg;
 
-  if (!priv->init[this_cpu()])
-    {
-      /* Enable int */
-
-      up_enable_irq(ARM_ARCH_TIMER_IRQ);
-
-      /* Start timer */
-
-      arm64_arch_timer_enable(true);
-      priv->init[this_cpu()] = true;
-    }
-
   priv->running = this_cpu();
 
   next_cycle =
@@ -388,7 +375,31 @@ struct oneshot_lowerhalf_s *arm64_oneshot_initialize(void)
   irq_attach(ARM_ARCH_TIMER_IRQ,
              arm64_arch_timer_compare_isr, priv);
 
+  arm64_oneshot_secondary_init();
+
   tmrinfo("oneshot_initialize ok %p \n", &priv->lh);
 
   return &priv->lh;
 }
+
+/****************************************************************************
+ * Name: arm64_arch_timer_secondary_init
+ *
+ * Description:
+ *   Initialize the ARM generic timer for secondary CPUs.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void arm64_oneshot_secondary_init(void)
+{
+  /* Enable int */
+
+  up_enable_irq(ARM_ARCH_TIMER_IRQ);
+
+  /* Start timer */
+
+  arm64_arch_timer_enable(true);
+}
diff --git a/arch/arm64/src/common/arm64_arch_timer.h b/arch/arm64/src/common/arm64_arch_timer.h
index 2b09033811..fd91d820ab 100644
--- a/arch/arm64/src/common/arm64_arch_timer.h
+++ b/arch/arm64/src/common/arm64_arch_timer.h
@@ -49,4 +49,17 @@
 
 struct oneshot_lowerhalf_s *arm64_oneshot_initialize(void);
 
+/****************************************************************************
+ * Name: arm64_oneshot_secondary_init
+ *
+ * Description:
+ *   Initialize the ARM generic timer for secondary CPUs.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void arm64_oneshot_secondary_init(void);
+
 #endif /* __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H */
diff --git a/arch/arm64/src/common/arm64_cpustart.c b/arch/arm64/src/common/arm64_cpustart.c
index 18edef3329..c41d565823 100644
--- a/arch/arm64/src/common/arm64_cpustart.c
+++ b/arch/arm64/src/common/arm64_cpustart.c
@@ -235,5 +235,7 @@ void arm64_boot_secondary_c_routine(void)
 
   arm64_gic_secondary_init();
 
+  arm64_timer_secondary_init();
+
   arm64_smp_init_top();
 }
diff --git a/arch/arm64/src/common/arm64_smp.h b/arch/arm64/src/common/arm64_smp.h
index 85a155b3a2..90082d3e95 100644
--- a/arch/arm64/src/common/arm64_smp.h
+++ b/arch/arm64/src/common/arm64_smp.h
@@ -80,6 +80,19 @@ void arm64_cpu_boot(int cpu);
 
 void arm64_enable_smp(int cpu);
 
+/****************************************************************************
+ * Name: arm64_timer_secondary_init
+ *
+ * Description:
+ *   Initialize the ARM timer for secondary CPUs.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void arm64_timer_secondary_init(void);
+
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_SMP */
 #endif /* __ARCH_ARM64_SRC_COMMON_ARM64_SMP_H */
diff --git a/arch/arm64/src/fvp-v8r/fvp_timer.c b/arch/arm64/src/fvp-v8r/fvp_timer.c
index f6b7917622..7076a4ec38 100644
--- a/arch/arm64/src/fvp-v8r/fvp_timer.c
+++ b/arch/arm64/src/fvp-v8r/fvp_timer.c
@@ -36,3 +36,8 @@ void up_timer_initialize(void)
 {
   up_alarm_set_lowerhalf(arm64_oneshot_initialize());
 }
+
+void arm64_timer_secondary_init(void)
+{
+  arm64_oneshot_secondary_init();
+}
diff --git a/arch/arm64/src/goldfish/goldfish_timer.c b/arch/arm64/src/goldfish/goldfish_timer.c
index 569a3b7619..2b6b9904f5 100644
--- a/arch/arm64/src/goldfish/goldfish_timer.c
+++ b/arch/arm64/src/goldfish/goldfish_timer.c
@@ -36,3 +36,8 @@ void up_timer_initialize(void)
 {
   up_alarm_set_lowerhalf(arm64_oneshot_initialize());
 }
+
+void arm64_timer_secondary_init(void)
+{
+  arm64_oneshot_secondary_init();
+}
diff --git a/arch/arm64/src/imx8/imx8_timer.c b/arch/arm64/src/imx8/imx8_timer.c
index d7c5080a7f..2dcd454977 100644
--- a/arch/arm64/src/imx8/imx8_timer.c
+++ b/arch/arm64/src/imx8/imx8_timer.c
@@ -36,3 +36,8 @@ void up_timer_initialize(void)
 {
   up_alarm_set_lowerhalf(arm64_oneshot_initialize());
 }
+
+void arm64_timer_secondary_init(void)
+{
+  arm64_oneshot_secondary_init();
+}
diff --git a/arch/arm64/src/imx9/imx9_timer.c b/arch/arm64/src/imx9/imx9_timer.c
index 171bd41934..25458ab164 100644
--- a/arch/arm64/src/imx9/imx9_timer.c
+++ b/arch/arm64/src/imx9/imx9_timer.c
@@ -36,3 +36,8 @@ void up_timer_initialize(void)
 {
   up_alarm_set_lowerhalf(arm64_oneshot_initialize());
 }
+
+void arm64_timer_secondary_init(void)
+{
+  arm64_oneshot_secondary_init();
+}
diff --git a/arch/arm64/src/qemu/qemu_timer.c b/arch/arm64/src/qemu/qemu_timer.c
index d7f16fde87..d663fec800 100644
--- a/arch/arm64/src/qemu/qemu_timer.c
+++ b/arch/arm64/src/qemu/qemu_timer.c
@@ -36,3 +36,8 @@ void up_timer_initialize(void)
 {
   up_alarm_set_lowerhalf(arm64_oneshot_initialize());
 }
+
+void arm64_timer_secondary_init(void)
+{
+  arm64_oneshot_secondary_init();
+}
diff --git a/arch/arm64/src/rk3399/rk3399_timer.c b/arch/arm64/src/rk3399/rk3399_timer.c
index 600c61e009..29df447af2 100644
--- a/arch/arm64/src/rk3399/rk3399_timer.c
+++ b/arch/arm64/src/rk3399/rk3399_timer.c
@@ -36,3 +36,8 @@ void up_timer_initialize(void)
 {
   up_alarm_set_lowerhalf(arm64_oneshot_initialize());
 }
+
+void arm64_timer_secondary_init(void)
+{
+  arm64_oneshot_secondary_init();
+}
diff --git a/arch/arm64/src/zynq-mpsoc/zynq_timer.c b/arch/arm64/src/zynq-mpsoc/zynq_timer.c
index 302bb71df1..f629673475 100644
--- a/arch/arm64/src/zynq-mpsoc/zynq_timer.c
+++ b/arch/arm64/src/zynq-mpsoc/zynq_timer.c
@@ -36,3 +36,8 @@ void up_timer_initialize(void)
 {
   up_alarm_set_lowerhalf(arm64_oneshot_initialize());
 }
+
+void arm64_timer_secondary_init(void)
+{
+  arm64_oneshot_secondary_init();
+}