From ac1f5d673a83d0ca54902f96a03fdf2705e2c7af Mon Sep 17 00:00:00 2001 From: Johanne Schock Date: Sun, 8 Mar 2020 13:16:33 +0100 Subject: [PATCH] Fixed formatting and comments in board.h and kinetis_k28memorymap.h Fixed clock calculation in board.h --- .../kinetis/hardware/kinetis_k28memorymap.h | 13 +--- .../arm/kinetis/freedom-k28f/include/board.h | 63 ++++++++++--------- 2 files changed, 33 insertions(+), 43 deletions(-) diff --git a/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h index 90a48d5756..c27b480002 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h @@ -51,6 +51,7 @@ ************************************************************************************/ /* Memory Map ***********************************************************************/ + /* K28 Family * * The memory map for the following parts is defined in NXP document @@ -213,17 +214,5 @@ # error "No memory map for this K28 part" #endif -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - #endif /* KINETIS_K28 */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H */ diff --git a/boards/arm/kinetis/freedom-k28f/include/board.h b/boards/arm/kinetis/freedom-k28f/include/board.h index 4f80aa7fa6..9faccd3197 100644 --- a/boards/arm/kinetis/freedom-k28f/include/board.h +++ b/boards/arm/kinetis/freedom-k28f/include/board.h @@ -1,4 +1,4 @@ -/**************************************************************************** +/******************************************************************************** * boards/arm/kinetis/freedom-k28f/include/board.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,14 +31,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************/ + ********************************************************************************/ #ifndef __BOARDS_ARM_KINETIS_FREEDOM_K28F_INCLUDE_BOARD_H #define __BOARDS_ARM_KINETIS_FREEDOM_K28F_INCLUDE_BOARD_H -/**************************************************************************** +/******************************************************************************** * Included Files - ****************************************************************************/ + ********************************************************************************/ #include @@ -49,11 +49,11 @@ # include #endif -/**************************************************************************** +/******************************************************************************** * Pre-processor Definitions - ****************************************************************************/ + ********************************************************************************/ -/* Clocking *****************************************************************/ +/* Clocking *********************************************************************/ /* The Freedom K28F uses a 12MHz external Oscillator. * The Kinetis MCU startup from an internal digitally-controlled oscillator @@ -76,8 +76,8 @@ * reference clock to the PLL. * * PLL Input frequency: PLLIN = REFCLK / PRDIV = 12 MHz / 1 = 12 MHz - * PLL Output frequency: PLLOUT = PLLIN * VDIV = 12 MHz * 25 = 300 MHz - * MCG Frequency: PLLOUT = 150 MHz = 300 MHz / + * PLL Output frequency: PLLOUT = PLLIN * VDIV = 12 MHz * 24 = 288 MHz + * MCG Frequency: PLLOUT = 144 MHz = 288 MHz / * KINETIS_MCG_PLL_INTERNAL_DIVBY * PRDIV register value is the divider minus KINETIS_MCG_C5_PRDIV_BASE. * VDIV register value is offset by KINETIS_MCG_C6_VDIV_BASE. @@ -115,9 +115,10 @@ #define BOARD_SOPT2_FREQ BOARD_MCG_FREQ /* N.B. The above BOARD_SOPT2_FREQ precludes use of USB with a 12 MHz Xtal - * Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] - * SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ] -* 48MHz = 144MHz / (2 + 1) * (1 + 0) + * Divider output clock = Divider input clock * ((USBFRAC+1) / (USBDIV+1)) + * SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ * ((USBFRAC+1) / (USBDIV+1)) + * SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ / (USBDIV+1)* (USBFRAC+1) + * 48MHz = 144MHz / (2 + 1) * (1 + 0) */ #if (BOARD_SOPT2_FREQ == 144000000L) @@ -129,9 +130,9 @@ #endif /* Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1)) - * SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)] - * 90 MHz = 180 MHz X [(0 + 1) / (1 + 1)] - * 90 MHz = 180 MHz / (1 + 1) * (0 + 1) + * SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ * ((PLLFLLFRAC+1) / (PLLFLLDIV+1)) + * SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ / (PLLFLLDIV+1) * (PLLFLLFRAC+1) + * 72MHz = 144MHz / (1 + 1) * (1 + 0) */ #define BOARD_SIM_CLKDIV3_PLLFLLFRAC 1 @@ -146,7 +147,7 @@ #define BOARD_TPM_CLKSRC SIM_SOPT2_TPMSRC_MCGCLK #define BOARD_TPM_FREQ BOARD_SIM_CLKDIV3_FREQ -/* SDHC clocking ************************************************************/ +/* SDHC clocking ****************************************************************/ /* SDCLK configurations corresponding to various modes of operation. * Formula is: @@ -162,38 +163,38 @@ */ /* Identification mode: - * Optimal 400KHz, Actual 180MHz / (32 * 15) = 375 Khz + * Optimal 400KHz, Actual 144MHz / (32 * 12) = 375 Khz */ #define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV32 -#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15) +#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(12) /* MMC normal mode: - * Optimal 20MHz, Actual 180MHz / (2 * 5) = 18 MHz + * Optimal 20MHz, Actual 144MHz / (2 * 4) = 18 MHz */ #define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 -#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(5) +#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(4) /* SD normal mode (1-bit): - * Optimal 20MHz, Actual 180MHz / (2 * 5) = 18 MHz + * Optimal 20MHz, Actual 144MHz / (2 * 4) = 18 MHz */ #define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 -#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(5) +#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(4) /* SD normal mode (4-bit): - * Optimal 25MHz, Actual 180MHz / (2 * 4) = 22.5 MHz (with DMA) + * Optimal 25MHz, Actual 144MHz / (2 * 3) = 24 MHz (with DMA) * SD normal mode (4-bit): - * Optimal 20MHz, Actual 180MHz / (2 * 4) = 22.5 MHz (no DMA) + * Optimal 25MHz, Actual 144MHz / (2 * 3) = 24 MHz (no DMA) */ #ifdef CONFIG_SDIO_DMA # define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 -# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(4) +# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) #else # define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 -# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(4) +# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) #endif /* Use the output of SIM_SOPT2[PLLFLLSEL] as the USB clock source */ @@ -228,7 +229,7 @@ #define GPIO_FTM2_CH0OUT PIN_FTM2_CH0 /* Pin 25: PTB18 */ #define GPIO_FTM2_CH1OUT PIN_FTM2_CH1 /* Pin 32: PTB19 */ -/* LED definitions **********************************************************/ +/* LED definitions **************************************************************/ /* A single LED is available driven by PTC5. The LED is grounded so bringing * PTC5 high will illuminate the LED. @@ -260,11 +261,11 @@ #define LED_ASSERTION 3 /* STATUS LED=no change */ #define LED_PANIC 3 /* STATUS LED=flashing */ -/* Button definitions *******************************************************/ +/* Button definitions ***********************************************************/ /* The freedom-k28f board has no standard GPIO contact buttons */ -/* Alternative pin resolution ***********************************************/ +/* Alternative pin resolution ***************************************************/ /* The Freedom K28F has five LPUARTs with pin availability as follows: * @@ -425,7 +426,7 @@ # define PIN_SDHC0_DCLK PIN_SDHC0_DCLK_1 #endif -/* LED definitions **********************************************************/ +/* LED definitions **************************************************************/ /* The Freedom K28F has a single RGB LED driven by the K28F as follows: * @@ -471,7 +472,7 @@ #define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ #undef LED_IDLE /* K28 is in sleep mode (Not used) */ -/* Button definitions *******************************************************/ +/* Button definitions ***********************************************************/ /* Two push buttons, SW2 and SW3, are available on FRDM-K28F board, * where SW2 is connected to PTA4 and SW3 is connected to PTD0.