diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs index 74b8c4c685..31b70c29ff 100644 --- a/arch/arm/src/sama5/Make.defs +++ b/arch/arm/src/sama5/Make.defs @@ -61,4 +61,4 @@ endif CHIP_ASRCS = -CHIP_CSRCS = sam_boot.c +CHIP_CSRCS = sam_boot.c sam_timerisr.c diff --git a/arch/arm/src/sama5/chip/sam_pinmap.h b/arch/arm/src/sama5/chip/sam_pinmap.h index 425825850c..1d303ec385 100644 --- a/arch/arm/src/sama5/chip/sam_pinmap.h +++ b/arch/arm/src/sama5/chip/sam_pinmap.h @@ -43,4 +43,3 @@ #include #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PINMAP_H */ - diff --git a/arch/arm/src/sama5/chip/sam_pit.h b/arch/arm/src/sama5/chip/sam_pit.h new file mode 100644 index 0000000000..1eb93f787a --- /dev/null +++ b/arch/arm/src/sama5/chip/sam_pit.h @@ -0,0 +1,89 @@ +/************************************************************************************ + * arch/arm/src/sama5/chip/sam_pit.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIT_H +#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/sam_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* PIT Register Offsets *************************************************************/ + +#define SAM_PIT_MR_OFFSET 0x0000 /* Mode Register */ +#define SAM_PIT_SR_OFFSET 0x0004 /* Status Register */ +#define SAM_PIT_PIVR_OFFSET 0x0008 /* Periodic Interval Value Register */ +#define SAM_PIT_PIIR_OFFSET 0x000c /* Periodic Interval Image Register */ + +/* PIT Virtual Base Address *********************************************************/ + +#define SAM_PIT_VBASE (SAM_SYSC_VADDR+SAM_PITC_OFFSET) + +/* PIT Register Addresses ***********************************************************/ + +#define SAM_PIT_MR (SAM_PIT_VBASE+SAM_PIT_MR_OFFSET) +#define SAM_PIT_SR (SAM_PIT_VBASE+SAM_PIT_SR_OFFSET) +#define SAM_PIT_PIVR (SAM_PIT_VBASE+SAM_PIT_PIVR_OFFSET) +#define SAM_PIT_PIIR (SAM_PIT_VBASE+SAM_PIT_PIIR_OFFSET) + +/* PIT Register Bit Definitions *****************************************************/ + +/* Mode Register */ + +#define PIT_MR_PIV_SHIFT (0) /* Bits 0-19: Periodic Interval Value */ +#define PIT_MR_PIV_MASK (0x000fffff) +# define PIT_MR_PIV(n) (n) +#define PIT_MR_PITEN (1 << 24) /* Bit 24: Period Interval Timer Enable */ +#define PIT_MR_PITIEN (1 << 25) /* Bit 25: Periodic Interval Timer Interrupt Enable */ + +/* Status Register */ + +#define PIT_SR_S (1 << 0) /* Bit 0: Periodic Interval Timer Status */ + +/* Periodic Interval Value Register */ +/* Periodic Interval Image Register */ + +#define PIT_CPIV_SHIFT (0) /* Bits 0-19: Current Periodic Interval Value */ +#define PIT_CPIV_MASK (0x000fffff) +#define PIT_PICNT_SHIFT (20) /* Bits 20-31: Periodic Interval Counter */ +#define PIT_PICNT_MASK (0xfff << PIT_PIVR_PICNT_SHIFT) + +#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIT_H */ diff --git a/arch/arm/src/sama5/sam_timerisr.c b/arch/arm/src/sama5/sam_timerisr.c new file mode 100644 index 0000000000..99b4d5df32 --- /dev/null +++ b/arch/arm/src/sama5/sam_timerisr.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/arm/src/sama5/sam_timerisr.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "chip/sam_pit.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ +/* The PIT counter runs at a rate of the main clock (MCK) divided by 16 */ + +#define PIT_CLOCK (BOARD_MCK_FREQUENCY >> 4) + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The PIT counts from zero and up until it reaches the overflow value set + * in the field PIV of the Mode Register (PIT MR). So an PIV value of n + * corresponds a duration of n * PIT_CLOCK + */ + +#define PIT_PIV ((PIT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK) + +/* The size of the reload field is 20 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if PIT_PIV > PIT_MR_PIV_MASK +# error PIT_PIV exceeds the maximum value +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, uint32_t *regs) +{ + /* "When CPIV and PICNT values are obtained by reading the Periodic + * Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is + * reset and the PITS is cleared, thus acknowledging the interrupt. The + * value of PICNT gives the number of periodic intervals elapsed since the + * last read of PIT_PIVR. + */ + + uint32_t picnt = getreg32(SAM_PIT_PIVR) >> PIT_PICNT_SHIFT; + + /* Process timer interrupt (multiple times if we missed an interrupt) */ + + while (picnt-- > 0) + { + sched_process_timer(); + } + + return OK; +} + +/**************************************************************************** + * Function: up_timerinit + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timerinit(void) +{ + uint32_t regval; + + /* Make sure that interrupts from the PIT are disabled */ + + up_disable_irq(SAM_IRQ_PIT); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(SAM_IRQ_PIT, (xcpt_t)up_timerisr); + + /* Set the PIT overflow value (PIV), enable the PIT, and enable + * interrupts from the PIT. + */ + + regval = PIT_PIV | PIT_MR_PITEN | PIT_MR_PITIEN; + + /* And enable the timer interrupt */ + + up_enable_irq(SAM_IRQ_PIT); +}