diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h index 06c483637f..ec22e405da 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h @@ -587,12 +587,14 @@ # define FTP_SC_PS_DIV32 (5 << FTM_SC_PS_SHIFT) /* Divide by 32 */ # define FTP_SC_PS_DIV64 (6 << FTM_SC_PS_SHIFT) /* Divide by 64 */ # define FTP_SC_PS_DIV128 (7 << FTM_SC_PS_SHIFT) /* Divide by 128 */ + #define FTM_SC_CLKS_SHIFT (3) /* Bits 3-4: Clock Source Selection */ #define FTM_SC_CLKS_MASK (0x03 << FTM_SC_CLKS_SHIFT) # define FTM_SC_CLKS_DIS (0 << FTM_SC_CLKS_SHIFT) /* No clock selected. This in effect disables the FTM counter */ # define FTM_SC_CLKS_FTM (1 << FTM_SC_CLKS_SHIFT) /* FTM input clock */ # define FTM_SC_CLKS_FIXED (2 << FTM_SC_CLKS_SHIFT) /* Fixed frequency clock */ # define FTM_SC_CLKS_EXTCLK (3 << FTM_SC_CLKS_SHIFT) /* External clock */ + #define FTM_SC_CPWMS (1 << 5) /* Bit 5: Center-Aligned PWM Select */ #define FTM_SC_RIE (1 << 6) /* Bit 6: Reload Point Interrupt Enable */ #define FTM_SC_RF (1 << 7) /* Bit 7: Reload Flag */ @@ -695,6 +697,7 @@ # define FTM_MODE_FAULTM_EVEN_MAN (1 << FTM_MODE_FAULTM_SHIFT) /* Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. */ # define FTM_MODE_FAULTM_ALL_MAN (2 << FTM_MODE_FAULTM_SHIFT) /* Fault control is enabled for all channels, and the selected mode is the manual fault clearing. */ # define FTM_MODE_FAULTM_ALL_AUTO (3 << FTM_MODE_FAULTM_SHIFT) /* Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. */ + #define FTM_MODE_FAULTIE (1 << 7) /* Bit 7: Fault Interrupt Enable */ /* Bits 8-31: Reserved */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_pwm.c b/arch/arm/src/s32k1xx/s32k1xx_pwm.c index f680686540..e8edb8cde6 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pwm.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pwm.c @@ -88,9 +88,9 @@ # define pwm_dumpgpio(p,m) #endif -/**************************************************************************** +/***************************************************************************** * Private Types - ****************************************************************************/ + *****************************************************************************/ /* This structure represents the state of one PWM timer */ @@ -443,7 +443,8 @@ static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv, cv = b16toi(info->duty * modulo + b16HALF); - pwminfo("FTM%d PCLK: %d frequency: %d FTMCLK: %d prescaler: %d modulo: %d c0v: %d\n", + pwminfo("FTM%d PCLK: %d frequency: %d FTMCLK: %d prescaler: %d modulo: %d \ + c0v: %d\n", priv->tpmid, priv->pclk, info->frequency, tpmclk, presc_values[prescaler], modulo, cv); @@ -462,55 +463,63 @@ static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv, { case 0: /* PWM Mode configuration: Channel 0 */ { - pwm_putreg(priv, S32K1XX_FTM_C0SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB); + pwm_putreg(priv, S32K1XX_FTM_C0SC_OFFSET, + FTM_CNSC_MSB | FTM_CNSC_ELSB); pwm_putreg(priv, S32K1XX_FTM_C0V_OFFSET, (uint16_t) cv); } break; case 1: /* PWM Mode configuration: Channel 1 */ { - pwm_putreg(priv, S32K1XX_FTM_C1SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB); + pwm_putreg(priv, S32K1XX_FTM_C1SC_OFFSET, + FTM_CNSC_MSB | FTM_CNSC_ELSB); pwm_putreg(priv, S32K1XX_FTM_C1V_OFFSET, (uint16_t) cv); } break; case 2: /* PWM Mode configuration: Channel 2 */ { - pwm_putreg(priv, S32K1XX_FTM_C2SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB); + pwm_putreg(priv, S32K1XX_FTM_C2SC_OFFSET, + FTM_CNSC_MSB | FTM_CNSC_ELSB); pwm_putreg(priv, S32K1XX_FTM_C2V_OFFSET, (uint16_t) cv); } break; case 3: /* PWM Mode configuration: Channel 3 */ { - pwm_putreg(priv, S32K1XX_FTM_C3SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB); + pwm_putreg(priv, S32K1XX_FTM_C3SC_OFFSET, + FTM_CNSC_MSB | FTM_CNSC_ELSB); pwm_putreg(priv, S32K1XX_FTM_C3V_OFFSET, (uint16_t) cv); } break; case 4: /* PWM Mode configuration: Channel 4 */ { - pwm_putreg(priv, S32K1XX_FTM_C4SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB); + pwm_putreg(priv, S32K1XX_FTM_C4SC_OFFSET, + FTM_CNSC_MSB | FTM_CNSC_ELSB); pwm_putreg(priv, S32K1XX_FTM_C4V_OFFSET, (uint16_t) cv); } break; case 5: /* PWM Mode configuration: Channel 5 */ { - pwm_putreg(priv, S32K1XX_FTM_C5SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB); + pwm_putreg(priv, S32K1XX_FTM_C5SC_OFFSET, + FTM_CNSC_MSB | FTM_CNSC_ELSB); pwm_putreg(priv, S32K1XX_FTM_C5V_OFFSET, (uint16_t) cv); } break; case 6: /* PWM Mode configuration: Channel 6 */ { - pwm_putreg(priv, S32K1XX_FTM_C6SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB); + pwm_putreg(priv, S32K1XX_FTM_C6SC_OFFSET, + FTM_CNSC_MSB | FTM_CNSC_ELSB); pwm_putreg(priv, S32K1XX_FTM_C6V_OFFSET, (uint16_t) cv); } break; case 7: /* PWM Mode configuration: Channel 7 */ { - pwm_putreg(priv, S32K1XX_FTM_C7SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB); + pwm_putreg(priv, S32K1XX_FTM_C7SC_OFFSET, + FTM_CNSC_MSB | FTM_CNSC_ELSB); pwm_putreg(priv, S32K1XX_FTM_C7V_OFFSET, (uint16_t) cv); } break; @@ -533,7 +542,7 @@ static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv, return OK; } -/**************************************************************************** +/***************************************************************************** * Name: pwm_setup * * Description: @@ -551,14 +560,15 @@ static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv, * AHB1 or 2 clocking for the GPIOs and timer has already been configured * by the RCC logic at power up. * - ****************************************************************************/ + *****************************************************************************/ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) { FAR struct s32k1xx_pwmtimer_s *priv = (FAR struct s32k1xx_pwmtimer_s *)dev; /* Note: The appropriate clock should for the right FTM device should - * already be enabled in the board-specific s32k1xx_periphclocks.c file. */ + * already be enabled in the board-specific s32k1xx_periphclocks.c file. + */ pwminfo("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg); pwm_dumpregs(priv, "Initially"); @@ -570,7 +580,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) return OK; } -/**************************************************************************** +/***************************************************************************** * Name: pwm_shutdown * * Description: @@ -584,7 +594,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) * Returned Value: * Zero on success; a negated errno value on failure * - ****************************************************************************/ + *****************************************************************************/ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) { @@ -605,7 +615,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) return OK; } -/**************************************************************************** +/***************************************************************************** * Name: pwm_start * * Description: @@ -618,7 +628,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) * Returned Value: * Zero on success; a negated errno value on failure * - ****************************************************************************/ + *****************************************************************************/ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info) @@ -627,7 +637,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, return pwm_timer(priv, info); } -/**************************************************************************** +/***************************************************************************** * Name: pwm_stop * * Description: @@ -644,7 +654,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, * method is also called from the timer interrupt handler when a repetition * count expires... automatically stopping the timer. * - ****************************************************************************/ + *****************************************************************************/ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) { @@ -711,7 +721,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) return OK; } -/**************************************************************************** +/***************************************************************************** * Name: pwm_ioctl * * Description: @@ -725,9 +735,10 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) * Returned Value: * Zero on success; a negated errno value on failure * - ****************************************************************************/ + *****************************************************************************/ -static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) +static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO FAR struct s32k1xx_pwmtimer_s *priv = (FAR struct s32k1xx_pwmtimer_s *)dev; @@ -739,11 +750,11 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg return -ENOTTY; } -/**************************************************************************** +/***************************************************************************** * Public Functions - ****************************************************************************/ + *****************************************************************************/ -/**************************************************************************** +/***************************************************************************** * Name: s32k1xx_pwminitialize * * Description: @@ -756,7 +767,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg * On success, a pointer to the S32K1XX lower half PWM driver is returned. * NULL is returned on any failure. * - ****************************************************************************/ + *****************************************************************************/ FAR struct pwm_lowerhalf_s *s32k1xx_pwminitialize(int timer) { diff --git a/arch/arm/src/s32k1xx/s32k1xx_pwm.h b/arch/arm/src/s32k1xx/s32k1xx_pwm.h index 746c67fefb..9ec5a00653 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pwm.h +++ b/arch/arm/src/s32k1xx/s32k1xx_pwm.h @@ -95,13 +95,13 @@ #include #include "hardware/s32k1xx_pinmux.h" -/* For each timer that is enabled for PWM usage, we need the following additional - * configuration settings: +/* For each timer that is enabled for PWM usage, we need the following + * additional configuration settings: * * CONFIG_S32K1XX_FTMx_CHANNEL - Specifies the timer output channel {0,..,7} - * PWM_FTMx_PINCFG - One of the values defined in s32k1*_pinmux.h. In the case - * where there are multiple pin selections, the correct setting must be provided - * in the arch/board/board.h file. + * PWM_FTMx_PINCFG - One of the values defined in s32k1*_pinmux.h. In the + * case where there are multiple pin selections, the correct setting must + * be provided in the arch/board/board.h file. */ #ifdef CONFIG_S32K1XX_FTM0_PWM @@ -332,7 +332,7 @@ extern "C" * On success, a pointer to the S32K1XX lower half PWM driver is returned. * NULL is returned on any failure. * - ************************************************************************************/ + *****************************************************************************/ FAR struct pwm_lowerhalf_s *s32k1xx_pwminitialize(int timer);