diff --git a/arch/tricore/src/common/tricore_csa.c b/arch/tricore/src/common/tricore_csa.c
index cec39ccb8a..340efd0d75 100644
--- a/arch/tricore/src/common/tricore_csa.c
+++ b/arch/tricore/src/common/tricore_csa.c
@@ -50,10 +50,18 @@ uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp,
 
   plcsa = (uintptr_t *)tricore_csa2addr(__mfcr(CPU_FCX));
 
+  /* DSYNC instruction should be executed immediately prior to the MTCR */
+
+  __dsync();
+
   pucsa = (uintptr_t *)tricore_csa2addr(plcsa[REG_UPCXI]);
 
   __mtcr(CPU_FCX, pucsa[REG_UPCXI]);
 
+  /* ISYNC instruction executed immediately following MTCR */
+
+  __isync();
+
   memset(pucsa, 0, XCPTCONTEXT_SIZE);
   memset(plcsa, 0, XCPTCONTEXT_SIZE);
 
diff --git a/arch/tricore/src/common/tricore_svcall.c b/arch/tricore/src/common/tricore_svcall.c
index 6628e89a51..b6e58ff14f 100644
--- a/arch/tricore/src/common/tricore_svcall.c
+++ b/arch/tricore/src/common/tricore_svcall.c
@@ -57,7 +57,13 @@ void tricore_svcall(volatile void *trap)
   uintptr_t *regs;
   uint32_t cmd;
 
-  regs = tricore_csa2addr(__mfcr(CPU_PCXI));
+  regs = (uintptr_t *)__mfcr(CPU_PCXI);
+
+  /* DSYNC instruction should be executed immediately prior to the MTCR */
+
+  __dsync();
+
+  regs = tricore_csa2addr((uintptr_t)regs);
 
   CURRENT_REGS = regs;