Make Pirelli-DLP10 a true board configuration; Calypso no compiles without errors
This commit is contained in:
Gregory Nutt
parent
ec84669a94
commit
bf21a8f790
5 changed files with 323 additions and 246 deletions
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@ -34,19 +34,16 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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/****************************************************************************
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* Prototypes for interrupt handling
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****************************************************************************/
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void calypso_kbd_irq();
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void calypso_gpio_irq();
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inline int calypso_kbd_irq(int irq, uint32_t *regs);
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/****************************************************************************
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* Initialize device, add /dev/... nodes
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****************************************************************************/
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void calypso_armio(void);
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void calypso_keypad(void);
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@ -47,30 +47,29 @@
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* HW access
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****************************************************************************/
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#define BASE_ADDR_ARMIO 0xfffe4800
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#define ARMIO_REG(x) ((void *)BASE_ADDR_ARMIO + (x))
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#define BASE_ADDR_ARMIO 0xfffe4800
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#define ARMIO_REG(x) (BASE_ADDR_ARMIO + (x))
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enum armio_reg {
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LATCH_IN = 0x00,
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LATCH_OUT = 0x02,
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IO_CNTL = 0x04,
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CNTL_REG = 0x06,
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LOAD_TIM = 0x08,
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KBR_LATCH_REG = 0x0a,
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KBC_REG = 0x0c,
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BUZZ_LIGHT_REG = 0x0e,
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LIGHT_LEVEL = 0x10,
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BUZZER_LEVEL = 0x12,
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GPIO_EVENT_MODE = 0x14,
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KBD_GPIO_INT = 0x16,
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KBD_GPIO_MASKIT = 0x18,
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GPIO_DEBOUNCING = 0x1a,
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GPIO_LATCH = 0x1c,
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LATCH_IN = 0x00,
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LATCH_OUT = 0x02,
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IO_CNTL = 0x04,
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CNTL_REG = 0x06,
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LOAD_TIM = 0x08,
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KBR_LATCH_REG = 0x0a,
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KBC_REG = 0x0c,
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BUZZ_LIGHT_REG = 0x0e,
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LIGHT_LEVEL = 0x10,
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BUZZER_LEVEL = 0x12,
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GPIO_EVENT_MODE = 0x14,
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KBD_GPIO_INT = 0x16,
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KBD_GPIO_MASKIT = 0x18,
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GPIO_DEBOUNCING = 0x1a,
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GPIO_LATCH = 0x1c,
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};
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#define KBD_INT (1<<0)
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#define GPIO_INT (1<<1)
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#define KBD_INT (1 << 0)
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#define GPIO_INT (1 << 1)
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/****************************************************************************
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* ARMIO interrupt handler
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@ -80,25 +79,25 @@ enum armio_reg {
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static int kbd_gpio_irq(int irq, uint32_t *regs)
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{
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calypso_kbd_irq();
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return 0;
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return calypso_kbd_irq(irq, regs);
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}
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/****************************************************************************
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* Initialize ARMIO
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****************************************************************************/
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void calypso_armio(void)
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{
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/* Enable ARMIO clock */
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putreg16(1<<5, ARMIO_REG(CNTL_REG));
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/* Enable ARMIO clock */
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/* Mask GPIO interrupt and keypad interrupt */
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putreg16(KBD_INT|GPIO_INT, ARMIO_REG(KBD_GPIO_MASKIT));
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putreg16(1<<5, ARMIO_REG(CNTL_REG));
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/* Attach and enable the interrupt */
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irq_attach(IRQ_KEYPAD_GPIO, (xcpt_t)kbd_gpio_irq);
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up_enable_irq(IRQ_KEYPAD_GPIO);
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/* Mask GPIO interrupt and keypad interrupt */
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putreg16(KBD_INT|GPIO_INT, ARMIO_REG(KBD_GPIO_MASKIT));
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/* Attach and enable the interrupt */
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irq_attach(IRQ_KEYPAD_GPIO, (xcpt_t)kbd_gpio_irq);
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up_enable_irq(IRQ_KEYPAD_GPIO);
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}
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@ -47,7 +47,9 @@
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#include <stdint.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/calypso/memory.h>
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#include <arch/calypso/clock.h>
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#include "arm.h"
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#include "up_arch.h"
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@ -56,21 +58,22 @@
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* Pre-processor Definitions
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****************************************************************************/
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#define BASE_ADDR_IRQ 0xfffffa00
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#define BASE_ADDR_IBOOT_EXC 0x0080001C
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#define BASE_ADDR_IRQ 0xfffffa00
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#define BASE_ADDR_IBOOT_EXC 0x0080001C
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enum irq_reg {
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IT_REG1 = 0x00,
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IT_REG2 = 0x02,
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MASK_IT_REG1 = 0x08,
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MASK_IT_REG2 = 0x0a,
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IRQ_NUM = 0x10,
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FIQ_NUM = 0x12,
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IRQ_CTRL = 0x14,
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enum irq_reg
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{
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IT_REG1 = 0x00,
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IT_REG2 = 0x02,
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MASK_IT_REG1 = 0x08,
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MASK_IT_REG2 = 0x0a,
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IRQ_NUM = 0x10,
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FIQ_NUM = 0x12,
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IRQ_CTRL = 0x14,
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};
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#define ILR_IRQ(x) (0x20 + (x*2))
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#define IRQ_REG(x) ((void *)BASE_ADDR_IRQ + (x))
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#define ILR_IRQ(x) (0x20 + (x*2))
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#define IRQ_REG(x) (BASE_ADDR_IRQ + (x))
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#ifndef ARRAY_SIZE
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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@ -87,28 +90,29 @@ extern uint32_t _exceptions;
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* Private Data
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****************************************************************************/
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static uint8_t default_irq_prio[] = {
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[IRQ_WATCHDOG] = 0xff,
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[IRQ_TIMER1] = 0xff,
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[IRQ_TIMER2] = 0xff,
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[IRQ_TSP_RX] = 0,
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[IRQ_TPU_FRAME] = 3,
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[IRQ_TPU_PAGE] = 0xff,
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[IRQ_SIMCARD] = 0xff,
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[IRQ_UART_MODEM] = 8,
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[IRQ_KEYPAD_GPIO] = 4,
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[IRQ_RTC_TIMER] = 9,
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[IRQ_RTC_ALARM_I2C] = 10,
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[IRQ_ULPD_GAUGING] = 2,
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[IRQ_EXTERNAL] = 12,
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[IRQ_SPI] = 0xff,
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[IRQ_DMA] = 0xff,
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[IRQ_API] = 0xff,
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[IRQ_SIM_DETECT] = 0,
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[IRQ_EXTERNAL_FIQ] = 7,
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[IRQ_UART_IRDA] = 2,
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[IRQ_ULPD_GSM_TIMER] = 1,
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[IRQ_GEA] = 0xff,
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static uint8_t default_irq_prio[] =
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{
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[IRQ_WATCHDOG] = 0xff,
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[IRQ_TIMER1] = 0xff,
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[IRQ_TIMER2] = 0xff,
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[IRQ_TSP_RX] = 0,
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[IRQ_TPU_FRAME] = 3,
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[IRQ_TPU_PAGE] = 0xff,
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[IRQ_SIMCARD] = 0xff,
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[IRQ_UART_MODEM] = 8,
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[IRQ_KEYPAD_GPIO] = 4,
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[IRQ_RTC_TIMER] = 9,
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[IRQ_RTC_ALARM_I2C] = 10,
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[IRQ_ULPD_GAUGING] = 2,
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[IRQ_EXTERNAL] = 12,
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[IRQ_SPI] = 0xff,
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[IRQ_DMA] = 0xff,
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[IRQ_API] = 0xff,
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[IRQ_SIM_DETECT] = 0,
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[IRQ_EXTERNAL_FIQ] = 7,
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[IRQ_UART_IRDA] = 2,
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[IRQ_ULPD_GSM_TIMER] = 1,
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[IRQ_GEA] = 0xff,
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};
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/****************************************************************************
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@ -117,53 +121,66 @@ static uint8_t default_irq_prio[] = {
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static void _irq_enable(enum irq_nr nr, int enable)
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{
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uint16_t *reg = IRQ_REG(MASK_IT_REG1);
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uint16_t val;
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uintptr_t reg = IRQ_REG(MASK_IT_REG1);
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uint16_t val;
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if (nr > 15) {
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reg = IRQ_REG(MASK_IT_REG2);
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nr -= 16;
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}
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if (nr > 15)
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{
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reg = IRQ_REG(MASK_IT_REG2);
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nr -= 16;
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}
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val = getreg16(reg);
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if (enable)
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val &= ~(1 << nr);
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else
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val |= (1 << nr);
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putreg16(val, reg);
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val = getreg16(reg);
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if (enable)
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{
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val &= ~(1 << nr);
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}
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else
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{
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val |= (1 << nr);
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}
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putreg16(val, reg);
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}
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static void set_default_priorities(void)
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{
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unsigned int i;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++) {
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uint16_t val;
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uint8_t prio = default_irq_prio[i];
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if (prio > 31)
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prio = 31;
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for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++)
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{
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uint16_t val;
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uint8_t prio = default_irq_prio[i];
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val = getreg16(IRQ_REG(ILR_IRQ(i)));
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val &= ~(0x1f << 2);
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val |= prio << 2;
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if (prio > 31)
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{
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prio = 31;
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}
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/* Make edge mode default. Hopefully causes less trouble */
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val |= 0x02;
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val = getreg16(IRQ_REG(ILR_IRQ(i)));
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val &= ~(0x1f << 2);
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val |= prio << 2;
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putreg16(val, IRQ_REG(ILR_IRQ(i)));
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}
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/* Make edge mode default. Hopefully causes less trouble */
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val |= 0x02;
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putreg16(val, IRQ_REG(ILR_IRQ(i)));
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}
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}
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/* Install the exception handlers to where the ROM loader jumps */
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static void calypso_exceptions_install(void)
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{
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uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC;
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uint32_t *exceptions_src = &_exceptions;
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int i;
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for (i = 0; i < 7; i++)
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*exceptions_dst++ = *exceptions_src++;
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uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC;
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uint32_t *exceptions_src = &_exceptions;
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int i;
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for (i = 0; i < 7; i++)
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{
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*exceptions_dst++ = *exceptions_src++;
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}
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}
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/****************************************************************************
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@ -180,27 +197,32 @@ static void calypso_exceptions_install(void)
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void up_irqinitialize(void)
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{
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/* Prepare hardware */
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calypso_exceptions_install();
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current_regs = NULL;
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/* Prepare hardware */
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/* Switch to internal ROM */
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calypso_bootrom(1);
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calypso_exceptions_install();
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current_regs = NULL;
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/* set default priorities */
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set_default_priorities();
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/* Switch to internal ROM */
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/* mask all interrupts off */
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putreg16(0xffff, IRQ_REG(MASK_IT_REG1));
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putreg16(0xffff, IRQ_REG(MASK_IT_REG2));
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calypso_bootrom(1);
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/* clear all pending interrupts */
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putreg16(0, IRQ_REG(IT_REG1));
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putreg16(0, IRQ_REG(IT_REG2));
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/* Set default priorities */
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set_default_priorities();
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/* Mask all interrupts off */
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putreg16(0xffff, IRQ_REG(MASK_IT_REG1));
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putreg16(0xffff, IRQ_REG(MASK_IT_REG2));
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/* clear all pending interrupts */
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putreg16(0, IRQ_REG(IT_REG1));
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putreg16(0, IRQ_REG(IT_REG2));
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/* Enable interrupts globally to the ARM core */
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/* enable interrupts globally to the ARM core */
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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irqrestore(SVC_MODE | PSR_F_BIT);
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irqrestore(SVC_MODE | PSR_F_BIT);
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#endif
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}
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@ -214,8 +236,10 @@ void up_irqinitialize(void)
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void up_disable_irq(int irq)
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{
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if((unsigned)irq < NR_IRQS)
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_irq_enable(irq, 0);
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if ((unsigned)irq < NR_IRQS)
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{
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_irq_enable(irq, 0);
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}
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}
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/****************************************************************************
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@ -228,8 +252,10 @@ void up_disable_irq(int irq)
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void up_enable_irq(int irq)
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{
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if((unsigned)irq < NR_IRQS)
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_irq_enable(irq, 1);
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if((unsigned)irq < NR_IRQS)
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{
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_irq_enable(irq, 1);
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}
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}
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/****************************************************************************
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@ -243,18 +269,22 @@ void up_enable_irq(int irq)
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#ifndef CONFIG_ARCH_IRQPRIO
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int up_prioritize_irq(int nr, int prio)
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{
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uint16_t val;
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uint16_t val;
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if (prio == -1)
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prio = default_irq_prio[nr];
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if (prio == -1)
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{
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prio = default_irq_prio[nr];
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}
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if (prio > 31)
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prio = 31;
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if (prio > 31)
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{
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prio = 31;
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}
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val = prio << 2;
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putreg16(val, IRQ_REG(ILR_IRQ(nr)));
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val = prio << 2;
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putreg16(val, IRQ_REG(ILR_IRQ(nr)));
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return 0; // XXX: what's the return???
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return 0;
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}
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#endif
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@ -264,25 +294,28 @@ int up_prioritize_irq(int nr, int prio)
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void up_decodeirq(uint32_t *regs)
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{
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uint8_t num, tmp;
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uint32_t *saved_regs;
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uint8_t num, tmp;
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uint32_t *saved_regs;
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/* XXX: What is this???
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* Passed to but ignored in IRQ handlers
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* Only valid meaning is apparently non-NULL == IRQ context */
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saved_regs = (uint32_t *)current_regs;
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current_regs = regs;
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/* XXX: What is this???
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* Passed to but ignored in IRQ handlers
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* Only valid meaning is apparently non-NULL == IRQ context */
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/* Detect & deliver the IRQ */
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num = getreg8(IRQ_REG(IRQ_NUM)) & 0x1f;
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irq_dispatch(num, regs);
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saved_regs = (uint32_t *)current_regs;
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current_regs = regs;
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/* Start new IRQ agreement */
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tmp = getreg8(IRQ_REG(IRQ_CTRL));
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tmp |= 0x01;
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putreg8(tmp, IRQ_REG(IRQ_CTRL));
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/* Detect & deliver the IRQ */
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current_regs = saved_regs;
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num = getreg8(IRQ_REG(IRQ_NUM)) & 0x1f;
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irq_dispatch(num, regs);
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/* Start new IRQ agreement */
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tmp = getreg8(IRQ_REG(IRQ_CTRL));
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tmp |= 0x01;
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putreg8(tmp, IRQ_REG(IRQ_CTRL));
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current_regs = saved_regs;
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}
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/****************************************************************************
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@ -291,23 +324,26 @@ void up_decodeirq(uint32_t *regs)
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void calypso_fiq(void)
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{
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uint8_t num, tmp;
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uint32_t *regs;
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uint8_t num, tmp;
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uint32_t *regs;
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/* XXX: What is this???
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* Passed to but ignored in IRQ handlers
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* Only valid meaning is apparently non-NULL == IRQ context */
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regs = (uint32_t *)current_regs;
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current_regs = (uint32_t *)#
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/* XXX: What is this???
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* Passed to but ignored in IRQ handlers
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* Only valid meaning is apparently non-NULL == IRQ context */
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/* Detect & deliver like an IRQ but we are in FIQ context */
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num = getreg8(IRQ_REG(FIQ_NUM)) & 0x1f;
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irq_dispatch(num, regs);
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regs = (uint32_t *)current_regs;
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current_regs = (uint32_t *)#
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/* Start new FIQ agreement */
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tmp = getreg8(IRQ_REG(IRQ_CTRL));
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tmp |= 0x02;
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putreg8(tmp, IRQ_REG(IRQ_CTRL));
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/* Detect & deliver like an IRQ but we are in FIQ context */
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current_regs = regs;
|
||||
num = getreg8(IRQ_REG(FIQ_NUM)) & 0x1f;
|
||||
irq_dispatch(num, regs);
|
||||
|
||||
/* Start new FIQ agreement */
|
||||
|
||||
tmp = getreg8(IRQ_REG(IRQ_CTRL));
|
||||
tmp |= 0x02;
|
||||
putreg8(tmp, IRQ_REG(IRQ_CTRL));
|
||||
|
||||
current_regs = regs;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@
|
|||
#include <arch/calypso/defines.h>
|
||||
#include <arch/calypso/memory.h>
|
||||
#include <arch/calypso/timer.h>
|
||||
#include <arch/calypso/armio.h>
|
||||
|
||||
/****************************************************************************
|
||||
* HW access
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@
|
|||
#include <nuttx/config.h>
|
||||
#include <nuttx/spi.h>
|
||||
|
||||
#include <unistd.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
|
@ -55,11 +56,11 @@ extern int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din
|
|||
|
||||
struct calypso_spidev_s
|
||||
{
|
||||
struct spi_dev_s spidev; /* External driver interface */
|
||||
int nbits; /* Number of transfered bits */
|
||||
struct spi_dev_s spidev; /* External driver interface */
|
||||
int nbits; /* Number of transfered bits */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
sem_t exclsem; /* Mutual exclusion of devices */
|
||||
sem_t exclsem; /* Mutual exclusion of devices */
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -69,13 +70,13 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
|
|||
#endif
|
||||
|
||||
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid,
|
||||
bool selected)
|
||||
bool selected)
|
||||
{
|
||||
}
|
||||
|
||||
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
|
||||
{
|
||||
return frequency;
|
||||
return frequency;
|
||||
}
|
||||
|
||||
static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
|
||||
|
|
@ -83,26 +84,29 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
|
|||
}
|
||||
|
||||
/* Osmocom wrapper */
|
||||
|
||||
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
|
||||
{
|
||||
((FAR struct calypso_spidev_s *)dev)->nbits = nbits;
|
||||
((FAR struct calypso_spidev_s *)dev)->nbits = nbits;
|
||||
}
|
||||
|
||||
static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
|
||||
FAR void *rxbuffer, size_t nwords)
|
||||
FAR void *rxbuffer, size_t nwords)
|
||||
{
|
||||
FAR struct calypso_spidev_s *priv = (FAR struct calypso_spidev_s *)dev;
|
||||
size_t i;
|
||||
FAR struct calypso_spidev_s *priv = (FAR struct calypso_spidev_s *)dev;
|
||||
size_t i;
|
||||
|
||||
for(i=0; i<nwords; i++)
|
||||
spi_xfer(0, priv->nbits, txbuffer+i, rxbuffer+i);
|
||||
for (i = 0; i < nwords; i++)
|
||||
{
|
||||
spi_xfer(0, priv->nbits, txbuffer+i, rxbuffer+i);
|
||||
}
|
||||
}
|
||||
|
||||
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
|
||||
{
|
||||
uint16_t buf = wd;
|
||||
spi_exchange(dev, &buf, &buf, 1);
|
||||
return buf;
|
||||
uint16_t buf = wd;
|
||||
spi_exchange(dev, &buf, &buf, 1);
|
||||
return buf;
|
||||
}
|
||||
|
||||
static const struct spi_ops_s g_spiops =
|
||||
|
|
@ -130,103 +134,143 @@ static const struct spi_ops_s g_spiops =
|
|||
|
||||
static struct calypso_spidev_s g_spidev =
|
||||
{
|
||||
.spidev = { &g_spiops },
|
||||
.nbits = 0,
|
||||
.spidev = { &g_spiops },
|
||||
.nbits = 0,
|
||||
};
|
||||
|
||||
void spi_init(void)
|
||||
{
|
||||
putreg16(SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS | SPI_SET1_RDWR_IRQ_DIS,
|
||||
SPI_REG(REG_SET1));
|
||||
putreg16(SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS | SPI_SET1_RDWR_IRQ_DIS,
|
||||
SPI_REG(REG_SET1));
|
||||
|
||||
putreg16(0x0001, SPI_REG(REG_SET2));
|
||||
putreg16(0x0001, SPI_REG(REG_SET2));
|
||||
}
|
||||
|
||||
int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
|
||||
{
|
||||
uint8_t bytes_per_xfer;
|
||||
uint8_t reg_status, reg_ctrl = 0;
|
||||
uint32_t tmp;
|
||||
uint8_t bytes_per_xfer;
|
||||
uint8_t reg_status, reg_ctrl = 0;
|
||||
uint32_t tmp;
|
||||
|
||||
if (bitlen == 0)
|
||||
return 0;
|
||||
if (bitlen == 0)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (bitlen > 32)
|
||||
return -1;
|
||||
if (bitlen > 32)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (dev_idx > 4)
|
||||
return -1;
|
||||
if (dev_idx > 4)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bytes_per_xfer = bitlen / 8;
|
||||
if (bitlen % 8)
|
||||
bytes_per_xfer ++;
|
||||
bytes_per_xfer = bitlen / 8;
|
||||
if (bitlen % 8)
|
||||
{
|
||||
bytes_per_xfer ++;
|
||||
}
|
||||
|
||||
reg_ctrl |= (bitlen - 1) << SPI_CTRL_NB_SHIFT;
|
||||
reg_ctrl |= (dev_idx & 0x7) << SPI_CTRL_AD_SHIFT;
|
||||
reg_ctrl |= (bitlen - 1) << SPI_CTRL_NB_SHIFT;
|
||||
reg_ctrl |= (dev_idx & 0x7) << SPI_CTRL_AD_SHIFT;
|
||||
|
||||
if (bitlen <= 8) {
|
||||
tmp = *(uint8_t *)dout;
|
||||
tmp <<= 24 + (8-bitlen); /* align to MSB */
|
||||
} else if (bitlen <= 16) {
|
||||
tmp = *(uint16_t *)dout;
|
||||
tmp <<= 16 + (16-bitlen); /* align to MSB */
|
||||
} else {
|
||||
tmp = *(uint32_t *)dout;
|
||||
tmp <<= (32-bitlen); /* align to MSB */
|
||||
}
|
||||
dbg("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
|
||||
dev_idx, bitlen, tmp);
|
||||
if (bitlen <= 8)
|
||||
{
|
||||
tmp = *(uint8_t *)dout;
|
||||
tmp <<= 24 + (8-bitlen); /* align to MSB */
|
||||
}
|
||||
else if (bitlen <= 16)
|
||||
{
|
||||
tmp = *(uint16_t *)dout;
|
||||
tmp <<= 16 + (16-bitlen); /* align to MSB */
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = *(uint32_t *)dout;
|
||||
tmp <<= (32-bitlen); /* align to MSB */
|
||||
}
|
||||
|
||||
/* fill transmit registers */
|
||||
putreg16(tmp >> 16, SPI_REG(REG_TX_MSB));
|
||||
putreg16(tmp & 0xffff, SPI_REG(REG_TX_LSB));
|
||||
dbg("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
|
||||
dev_idx, bitlen, tmp);
|
||||
|
||||
/* initiate transfer */
|
||||
if (din)
|
||||
reg_ctrl |= SPI_CTRL_RDWR;
|
||||
else
|
||||
reg_ctrl |= SPI_CTRL_WR;
|
||||
putreg16(reg_ctrl, SPI_REG(REG_CTRL));
|
||||
dbg("reg_ctrl=0x%04x ", reg_ctrl);
|
||||
/* fill transmit registers */
|
||||
|
||||
/* wait until the transfer is complete */
|
||||
while (1) {
|
||||
reg_status = getreg16(SPI_REG(REG_STATUS));
|
||||
dbg("status=0x%04x ", reg_status);
|
||||
if (din && (reg_status & SPI_STATUS_RE))
|
||||
break;
|
||||
else if (reg_status & SPI_STATUS_WE)
|
||||
break;
|
||||
}
|
||||
/* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */
|
||||
usleep(1000);
|
||||
putreg16(tmp >> 16, SPI_REG(REG_TX_MSB));
|
||||
putreg16(tmp & 0xffff, SPI_REG(REG_TX_LSB));
|
||||
|
||||
if (din) {
|
||||
tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16;
|
||||
tmp |= getreg16(SPI_REG(REG_RX_LSB));
|
||||
dbg("data_in=0x%08x ", tmp);
|
||||
/* initiate transfer */
|
||||
|
||||
if (bitlen <= 8)
|
||||
*(uint8_t *)din = tmp & 0xff;
|
||||
else if (bitlen <= 16)
|
||||
*(uint16_t *)din = tmp & 0xffff;
|
||||
else
|
||||
*(uint32_t *)din = tmp;
|
||||
}
|
||||
dbg("\n");
|
||||
if (din)
|
||||
{
|
||||
reg_ctrl |= SPI_CTRL_RDWR;
|
||||
}
|
||||
else
|
||||
{
|
||||
reg_ctrl |= SPI_CTRL_WR;
|
||||
}
|
||||
|
||||
return 0;
|
||||
putreg16(reg_ctrl, SPI_REG(REG_CTRL));
|
||||
dbg("reg_ctrl=0x%04x ", reg_ctrl);
|
||||
|
||||
/* wait until the transfer is complete */
|
||||
|
||||
while (1)
|
||||
{
|
||||
reg_status = getreg16(SPI_REG(REG_STATUS));
|
||||
dbg("status=0x%04x ", reg_status);
|
||||
if (din && (reg_status & SPI_STATUS_RE))
|
||||
{
|
||||
break;
|
||||
}
|
||||
else if (reg_status & SPI_STATUS_WE)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */
|
||||
|
||||
usleep(1000);
|
||||
|
||||
if (din)
|
||||
{
|
||||
tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16;
|
||||
tmp |= getreg16(SPI_REG(REG_RX_LSB));
|
||||
dbg("data_in=0x%08x ", tmp);
|
||||
|
||||
if (bitlen <= 8)
|
||||
{
|
||||
*(uint8_t *)din = tmp & 0xff;
|
||||
}
|
||||
else if (bitlen <= 16)
|
||||
{
|
||||
*(uint16_t *)din = tmp & 0xffff;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(uint32_t *)din = tmp;
|
||||
}
|
||||
}
|
||||
|
||||
dbg("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
{
|
||||
switch(port) {
|
||||
case 0: /* SPI master device */
|
||||
spi_init();
|
||||
return (FAR struct spi_dev_s *)&g_spidev;
|
||||
case 1: /* uWire device */
|
||||
return NULL;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
switch (port)
|
||||
{
|
||||
case 0: /* SPI master device */
|
||||
spi_init();
|
||||
return (FAR struct spi_dev_s *)&g_spidev;
|
||||
|
||||
case 1: /* uWire device */
|
||||
return NULL;
|
||||
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue