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arch/risc-v: Refine Toolchain.defs

Browse source 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2021-12-27 00:18:22 +08:00 • committed by Xiang Xiao
parent 1f87ded9c2
commit c2e8c92b25
32 changed files with 216 additions and 192 deletions
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96
arch/risc-v/Kconfig
View file

@ -12,13 +12,19 @@ choice
config ARCH_CHIP_FE310
bool "SiFive FE310"
select ARCH_RV32IM
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
---help---
SiFive FE310 processor (E31 RISC-V Core with MAC extensions).
config ARCH_CHIP_K210
bool "Kendryte K210"
select ARCH_RV64GC
select ARCH_RV64
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_MPU
select ARCH_HAVE_TESTSET
select ARCH_HAVE_MULTICPU
@ -27,21 +33,28 @@ config ARCH_CHIP_K210
config ARCH_CHIP_LITEX
bool "Enjoy Digital LITEX VEXRISCV"
select ARCH_RV32IM
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
---help---
Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
config ARCH_CHIP_BL602
bool "BouffaloLab BL602"
select ARCH_RV32IM
select ARCH_HAVE_FPU
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_F
select ARCH_RV_ISA_C
select ARCH_HAVE_RESET
---help---
BouffaloLab BL602(rv32imfc)
config ARCH_CHIP_ESP32C3
bool "Espressif ESP32-C3"
select ARCH_RV32IM
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_C
select RV32IM_HW_MULDIV
select ARCH_VECNOTIRQ
select ARCH_HAVE_RESET
@ -65,14 +78,24 @@ config ARCH_CHIP_ESP32C3
config ARCH_CHIP_C906
bool "THEAD C906"
select ARCH_RV64GC
select ARCH_RV64
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_F
select ARCH_RV_ISA_D
select ARCH_RV_ISA_C
select ARCH_HAVE_MPU
---help---
THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
config ARCH_CHIP_MPFS
bool "MicroChip Polarfire (MPFS)"
select ARCH_RV64GC
select ARCH_RV64
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_F
select ARCH_RV_ISA_D
select ARCH_RV_ISA_C
select ARCH_HAVE_MPU
select ARCH_HAVE_RESET
select ARCH_HAVE_SPI_CS_CONTROL
@ -82,13 +105,19 @@ config ARCH_CHIP_MPFS
config ARCH_CHIP_RV32M1
bool "NXP RV32M1"
select ARCH_RV32IM
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_C
---help---
NXP RV32M1 processor (RISC-V Core with PULP extensions).
config ARCH_CHIP_QEMU_RV32
bool "QEMU RV32"
select ARCH_RV32IM
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_F
select ARCH_RV_ISA_D
---help---
QEMU Generic RV32 processor
@ -100,26 +129,49 @@ config ARCH_CHIP_RISCV_CUSTOM
endchoice
config ARCH_RV32I
config ARCH_RV32
bool
default n
select ARCH_HAVE_SETJMP
config ARCH_RV32IM
bool
default n
select ARCH_HAVE_SETJMP
config ARCH_RV64GC
config ARCH_RV64
bool
default n
select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
select ARCH_HAVE_SETJMP
config ARCH_RV_ISA_M
bool
default n
config ARCH_RV_ISA_A
bool
default n
config ARCH_RV_ISA_C
bool
default n
config ARCH_RV_ISA_F
bool
default n
select ARCH_HAVE_FPU
config ARCH_RV_ISA_D
bool
default n
depends on ARCH_RV_ISA_F
select ARCH_HAVE_DPFPU
config ARCH_RV32I
bool
default n
select ARCH_HAVE_SETJMP
config ARCH_FAMILY
string
default "rv32im" if ARCH_RV32IM
default "rv64gc" if ARCH_RV64GC
default "rv32" if ARCH_RV32
default "rv64" if ARCH_RV64
config ARCH_CHIP
string
@ -136,6 +188,7 @@ config ARCH_CHIP
config ARCH_RISCV_INTXCPT_EXTENSIONS
bool "RISC-V Integer Context Extensions"
default n
depends on RV32M1_OPENISA_TOOLCHAIN
---help---
RISC-V could be customized with extensions. Some Integer Context
Registers have to be saved and restored when Contexts switch.
@ -149,11 +202,12 @@ config ARCH_RISCV_INTXCPT_EXTREGS
endif
source "arch/risc-v/src/opensbi/Kconfig"
source "arch/risc-v/src/common/Kconfig"
if ARCH_RV32IM
if ARCH_RV32
source "arch/risc-v/src/rv32im/Kconfig"
endif
if ARCH_RV64GC
if ARCH_RV64
source "arch/risc-v/src/rv64gc/Kconfig"
endif
if ARCH_CHIP_FE310

4
arch/risc-v/include/arch.h
View file

@ -37,11 +37,11 @@
#include <arch/csr.h>
#ifdef CONFIG_ARCH_RV32IM
#ifdef CONFIG_ARCH_RV32
# include <arch/rv32im/arch.h>
#endif
#ifdef CONFIG_ARCH_RV64GC
#ifdef CONFIG_ARCH_RV64
# include <arch/rv64gc/arch.h>
#endif

4
arch/risc-v/include/irq.h
View file

@ -38,11 +38,11 @@
/* Include RISC-V architecture-specific IRQ definitions */
#if defined(CONFIG_ARCH_RV32IM) || defined(CONFIG_ARCH_RV32I)
#if defined(CONFIG_ARCH_RV32)
# include <arch/rv32im/irq.h>
#endif
#if defined(CONFIG_ARCH_RV64GC)
#if defined(CONFIG_ARCH_RV64)
# include <arch/rv64gc/irq.h>
#endif

6
arch/risc-v/include/limits.h
View file

@ -54,7 +54,7 @@
/* These change on 32-bit and 64-bit platforms */
#if defined(CONFIG_ARCH_RV32IM) || defined(CONFIG_ARCH_RV32I)
#if defined(CONFIG_ARCH_RV32)
#define LONG_MIN (-LONG_MAX - 1)
#define LONG_MAX 2147483647L
@ -70,9 +70,9 @@
#define PTR_MAX 2147483647
#define UPTR_MAX 4294967295U
#endif /* defined(CONFIG_ARCH_32IM) || defined(CONFIG_ARCH_32I) */
#endif /* defined(CONFIG_ARCH_RV32) */
#if defined(CONFIG_ARCH_RV64GC)
#if defined(CONFIG_ARCH_RV64)
#define LONG_MIN (-LONG_MAX - 1)
#define LONG_MAX 9223372036854775807L

4
arch/risc-v/include/syscall.h
View file

@ -31,11 +31,11 @@
/* Include RISC-V architecture-specific syscall macros */
#ifdef CONFIG_ARCH_RV32IM
#ifdef CONFIG_ARCH_RV32
# include <arch/rv32im/syscall.h>
#endif
#ifdef CONFIG_ARCH_RV64GC
#ifdef CONFIG_ARCH_RV64
# include <arch/rv64gc/syscall.h>
#endif

10
arch/risc-v/src/Makefile
View file

@ -24,14 +24,12 @@ ifeq ($(CONFIG_OPENSBI),y)
include opensbi/Make.defs
endif
ifeq ($(CONFIG_ARCH_RV32I),y) # Base Integer support
ARCH_SUBDIR = rv32i
else ifeq ($(CONFIG_ARCH_RV32IM),y) # Integer + math support
# TODO: Merge these implementaions into one
ifeq ($(CONFIG_ARCH_RV32),y)
ARCH_SUBDIR = rv32im
else ifeq ($(CONFIG_ARCH_RV64GC),y) # GC=IMAFDC
else ifeq ($(CONFIG_ARCH_RV64),y)
ARCH_SUBDIR = rv64gc
else
ARCH_SUBDIR = rv32i # Default to base RV32I core
endif
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src

29
arch/risc-v/src/common/Kconfig Normal file
View file

@ -0,0 +1,29 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "RISC-V Common Options"
choice
prompt "Toolchain Selection"
default RISCV_TOOLCHAIN_GNU_RVGW if TOOLCHAIN_WINDOWS
default RISCV_TOOLCHAIN_GNU_RVGL if !TOOLCHAIN_WINDOWS
config RISCV_TOOLCHAIN_GNU_RVGL
bool "Generic GNU RVG toolchain under Linux (or other POSIX environment)"
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 5.2 or newer)
configured for riscv64-unknown-elf.
config RISCV_TOOLCHAIN_GNU_RVGW
bool "Generic GNU RVG toolchain under Windows"
depends on TOOLCHAIN_WINDOWS
select CYGWIN_WINTOOL if WINDOWS_CYGWIN
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 5.2 or newer)
configured for riscv64-unknown-elf.
endchoice

63
arch/risc-v/src/rv32im/Toolchain.defs → arch/risc-v/src/common/Toolchain.defs
View file

@ -1,5 +1,5 @@
############################################################################
# arch/risc-v/src/rv32im/Toolchain.defs
# arch/risc-v/src/common/Toolchain.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
@ -27,11 +27,11 @@
# command-line selection.
#
ifeq ($(filter y, $(CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL)),y)
ifeq ($(filter y, $(CONFIG_RISCV_TOOLCHAIN_GNU_RVGL)),y)
CONFIG_RISCV_TOOLCHAIN ?= GNU_RVG
endif
ifeq ($(filter y, $(CONFIG_RV32IM_TOOLCHAIN_GNU_RVGW)),y)
ifeq ($(filter y, $(CONFIG_RISCV_TOOLCHAIN_GNU_RVGW)),y)
CONFIG_RISCV_TOOLCHAIN ?= GNU_RVG
endif
@ -62,12 +62,61 @@ endif
# Generic GNU RVG toolchain
ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
# Generic GNU RVG toolchain
CROSSDEV ?= riscv64-unknown-elf-
ifeq ($(CONFIG_ARCH_FPU),y)
ARCHCPUFLAGS = -march=rv32imfc -mabi=ilp32f
else
ARCHCPUFLAGS = -march=rv32imc -mabi=ilp32
# Detect cpu ISA support flags
ifeq ($(CONFIG_ARCH_RV_ISA_M),y)
ARCHRVISAM = m
endif
ifeq ($(CONFIG_ARCH_RV_ISA_A),y)
ARCHRVISAA = a
endif
ifeq ($(CONFIG_ARCH_RV_ISA_C),y)
ARCHRVISAC = c
endif
# ARCH_FPU depends on ARCH_RV_ISA_F
ifeq ($(CONFIG_ARCH_FPU),y)
ARCHRVISAF = f
endif
# ARCH_DPFPU depends on ARCH_RV_ISA_D and ARCH_FPU
ifeq ($(CONFIG_ARCH_DPFPU),y)
ARCHRVISAD = d
endif
# Detect abi type
ifeq ($(CONFIG_ARCH_RV32),y)
ARCHTYPE = rv32
ARCHABITYPE = ilp32
else ifeq ($(CONFIG_ARCH_RV64),y)
ARCHTYPE = rv64
ARCHABITYPE = lp64
endif
# Construct arch flags
ARCHCPUFLAGS = -march=$(ARCHTYPE)i$(ARCHRVISAM)$(ARCHRVISAA)$(ARCHRVISAF)$(ARCHRVISAD)$(ARCHRVISAC)
# Construct arch abi flags
ifeq ($(CONFIG_ARCH_DPFPU),y)
ARCHCPUFLAGS += -mabi=$(ARCHABITYPE)d
else ifeq ($(CONFIG_ARCH_FPU),y)
ARCHCPUFLAGS += -mabi=$(ARCHABITYPE)f
else
ARCHCPUFLAGS += -mabi=$(ARCHABITYPE)
endif
ifeq ($(CONFIG_RV32IM_HW_MULDIV),y)
ARCHCPUFLAGS += -mdiv
else

12
arch/risc-v/src/common/riscv_internal.h
View file

@ -49,7 +49,7 @@
* only a referenced is passed to get the state from the TCB.
*/
#ifdef CONFIG_ARCH_RV64GC
#ifdef CONFIG_ARCH_RV64
#define riscv_savestate(regs) riscv_copystate(regs, (uint64_t*)CURRENT_REGS)
#define riscv_restorestate(regs) (CURRENT_REGS = regs)
#else
@ -101,7 +101,7 @@ extern "C"
#endif
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_RV64GC
#ifdef CONFIG_ARCH_RV64
#ifdef CONFIG_SMP
EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
# define CURRENT_REGS (g_current_regs[up_cpu_index()])
@ -167,7 +167,7 @@ void riscv_addregion(void);
void riscv_ack_irq(int irq);
#ifdef CONFIG_ARCH_RV64GC
#ifdef CONFIG_ARCH_RV64
void riscv_copystate(uint64_t *dest, uint64_t *src);
void riscv_copyfullstate(uint64_t *dest, uint64_t *src);
#else
@ -180,13 +180,13 @@ int riscv_swint(int irq, void *context, void *arg);
uint32_t riscv_get_newintctx(void);
#ifdef CONFIG_ARCH_FPU
#ifdef CONFIG_ARCH_RV64GC
#ifdef CONFIG_ARCH_RV64
void riscv_savefpu(uint64_t *regs);
void riscv_restorefpu(const uint64_t *regs);
#else /* !CONFIG_ARCH_RV64GC */
#else /* !CONFIG_ARCH_RV64 */
void riscv_savefpu(uint32_t *regs);
void riscv_restorefpu(const uint32_t *regs);
#endif /* CONFIG_ARCH_RV64GC */
#endif /* CONFIG_ARCH_RV64 */
#else
# define riscv_savefpu(regs)
# define riscv_restorefpu(regs)

2
arch/risc-v/src/common/riscv_interruptcontext.c
View file

@ -51,7 +51,7 @@
bool up_interrupt_context(void)
{
#ifdef CONFIG_ARCH_RV64GC
#ifdef CONFIG_ARCH_RV64
#ifdef CONFIG_SMP
irqstate_t flags = up_irq_save();
#endif

4
arch/risc-v/src/qemu-rv32/Make.defs
View file

@ -46,6 +46,10 @@ ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y)
CMN_CSRCS += riscv_tls.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += riscv_fpu.S
endif
# Specify our C code within this directory to be included
CHIP_CSRCS = qemu_rv32_start.c qemu_rv32_irq_dispatch.c qemu_rv32_irq.c
CHIP_CSRCS += qemu_rv32_idle.c qemu_rv32_timerisr.c

93
arch/risc-v/src/rv64gc/Toolchain.defs
View file

@ -1,93 +0,0 @@
############################################################################
# arch/risc-v/src/rv64gc/Toolchain.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Setup for the selected toolchain
#
# Handle old-style chip-specific toolchain names in the absence of
# a new-style toolchain specification, force the selection of a single
# toolchain and allow the selected toolchain to be overridden by a
# command-line selection.
#
ifeq ($(filter y, $(CONFIG_RV64GC_TOOLCHAIN_GNU_RVGL)),y)
CONFIG_RISCV_TOOLCHAIN ?= GNU_RVG
endif
ifeq ($(filter y, $(CONFIG_RV64GC_TOOLCHAIN_GNU_RVGW)),y)
CONFIG_RISCV_TOOLCHAIN ?= GNU_RVG
endif
#
# Supported toolchains
#
# Each toolchain definition should set:
#
# CROSSDEV The GNU toolchain triple (command prefix)
# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
# options, etc.
# MAXOPTIMIZATION The maximum optimization level that results in
# reliable code generation.
#
ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL)
else
MAXOPTIMIZATION ?= -Os
endif
ifeq ($(CONFIG_FRAME_POINTER),y)
MAXOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls
else
MAXOPTIMIZATION += -fomit-frame-pointer
endif
# Generic GNU RVG toolchain
ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
CROSSDEV ?= riscv64-unknown-elf-
endif
# Default toolchain
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E -P -x c
LD = $(CROSSDEV)ld
STRIP = $(CROSSDEV)strip --strip-unneeded
AR = $(CROSSDEV)ar rcs
NM = $(CROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
# Add the builtin library
EXTRA_LIBS += -lgcc
EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name`"}"
ifneq ($(CONFIG_LIBM),y)
EXTRA_LIBS += -lm
EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a`"}"
endif
ifeq ($(CONFIG_LIBSUPCXX),y)
EXTRA_LIBS += -lsupc++
EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a`"}"
endif

4
boards/risc-v/bl602/bl602evb/scripts/Make.defs
View file

@ -20,7 +20,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
@ -44,7 +44,7 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce
endif
ARCHCPUFLAGS = -march=rv32imafc -mabi=ilp32f -mno-relax
ARCHCPUFLAGS += -mno-relax
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fshort-enums -fno-omit-frame-pointer
ARCHCXXFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fshort-enums -fno-omit-frame-pointer -fno-exceptions -fcheck-new -std=c++17 -D__NuttX__ -pipe -nostdinc++
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef

8
boards/risc-v/c906/smartl-c906/scripts/Make.defs
View file

@ -20,7 +20,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv64gc/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
ifeq ($(CONFIG_C906_WITH_QEMU),y)
LDSCRIPT = ld-qemu.script
@ -50,11 +50,7 @@ endif
# ARCHCPUFLAGS = -march=rv64gcxthead -mabi=lp64d -mtune=c906 -mcmodel=medany
# TODO: We are not going to enable this at this time for the CI compatiblity.
ifeq ($(CONFIG_ARCH_HAVE_DPFPU),y)
ARCHCPUFLAGS = -march=rv64gc -mabi=lp64d -mcmodel=medany
else
ARCHCPUFLAGS = -march=rv64imac -mabi=lp64 -mcmodel=medany
endif
ARCHCPUFLAGS += -mcmodel=medany
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fno-omit-frame-pointer
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti

2
boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs
View file

@ -21,7 +21,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/tools/esp32c3/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
LDSCRIPT1 = $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32c3_out.ld
ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y)

3
boards/risc-v/fe310/hifive1-revb/scripts/Make.defs
View file

@ -20,7 +20,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
ifeq ($(CONFIG_ARCH_CHIP_FE310_QEMU),y)
LDSCRIPT = ld-qemu.script
@ -45,7 +45,6 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce
endif
ARCHCPUFLAGS = -march=rv32imac -mabi=ilp32
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef

4
boards/risc-v/k210/maix-bit/scripts/Make.defs
View file

@ -20,7 +20,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv64gc/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
LDSCRIPT = ld.script
@ -41,7 +41,7 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce
endif
ARCHCPUFLAGS = -march=rv64imafc -mabi=lp64f -mcmodel=medany
ARCHCPUFLAGS += -mcmodel=medany
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef

3
boards/risc-v/litex/arty_a7/scripts/Make.defs
View file

@ -20,7 +20,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
LDSCRIPT = ld.script
@ -41,7 +41,6 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce
endif
ARCHCPUFLAGS = -march=rv32ima -mabi=ilp32
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef

2
boards/risc-v/mpfs/icicle/configs/hwtest/defconfig
View file

@ -5,6 +5,7 @@
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_FPU is not set
# CONFIG_DISABLE_OS_API is not set
# CONFIG_NSH_DISABLE_LOSMART is not set
# CONFIG_SPI_CALLBACK is not set
@ -96,5 +97,4 @@ CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=20
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_OSTEST_FPUSIZE=264
CONFIG_UART1_SERIAL_CONSOLE=y

2
boards/risc-v/mpfs/icicle/configs/nsh/defconfig
View file

@ -5,6 +5,7 @@
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_FPU is not set
# CONFIG_DISABLE_OS_API is not set
# CONFIG_NSH_DISABLE_LOSMART is not set
CONFIG_ARCH="risc-v"
@ -71,5 +72,4 @@ CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=20
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_OSTEST_FPUSIZE=264
CONFIG_UART1_SERIAL_CONSOLE=y

1
boards/risc-v/mpfs/icicle/configs/opensbi/defconfig
View file

@ -5,6 +5,7 @@
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_FPU is not set
# CONFIG_DISABLE_OS_API is not set
# CONFIG_NSH_DISABLE_MW is not set
CONFIG_ARCH="risc-v"

8
boards/risc-v/mpfs/icicle/scripts/Make.defs
View file

@ -20,7 +20,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv64gc/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
ifeq ($(CONFIG_MPFS_BOOTLOADER),y)
ifeq ($(CONFIG_MPFS_OPENSBI),y)
@ -54,11 +54,7 @@ endif
# ARCHCPUFLAGS = -march=rv64gcxthead -mabi=lp64d -mcmodel=medany
# TODO: We are not going to enable this at this time for the CI compatiblity.
ifeq ($(CONFIG_ARCH_HAVE_DPFPU),y)
ARCHCPUFLAGS = -march=rv64gc -mabi=lp64d -mcmodel=medany
else
ARCHCPUFLAGS = -march=rv64imac -mabi=lp64 -mcmodel=medany
endif
ARCHCPUFLAGS += -mcmodel=medany
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fno-omit-frame-pointer
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti

8
boards/risc-v/mpfs/m100pfsevp/configs/nsh/defconfig
View file

@ -5,11 +5,12 @@
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_FPU is not set
# CONFIG_DISABLE_OS_API is not set
# CONFIG_NSH_DISABLE_LOSMART is not set
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="m100pfsevp"
CONFIG_ARCH_BOARD_M100PFSEVP_MPFS=y
CONFIG_ARCH_BOARD="icicle"
CONFIG_ARCH_BOARD_ICICLE_MPFS=y
CONFIG_ARCH_CHIP="mpfs"
CONFIG_ARCH_CHIP_MPFS=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -33,7 +34,7 @@ CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_FLOATINGPOINT=y
CONFIG_LIBC_HOSTNAME="m100pfsevp"
CONFIG_LIBC_HOSTNAME="icicle"
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
CONFIG_MEMSET_64BIT=y
@ -71,5 +72,4 @@ CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=20
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_OSTEST_FPUSIZE=264
CONFIG_UART1_SERIAL_CONSOLE=y

8
boards/risc-v/mpfs/m100pfsevp/scripts/Make.defs
View file

@ -20,7 +20,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv64gc/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
ifeq ($(CONFIG_MPFS_BOOTLOADER),y)
LDSCRIPT = ld-envm.script
@ -50,11 +50,7 @@ endif
# ARCHCPUFLAGS = -march=rv64gcxthead -mabi=lp64d -mcmodel=medany
# TODO: We are not going to enable this at this time for the CI compatiblity.
ifeq ($(CONFIG_ARCH_HAVE_DPFPU),y)
ARCHCPUFLAGS = -march=rv64gc -mabi=lp64d -mcmodel=medany
else
ARCHCPUFLAGS = -march=rv64imac -mabi=lp64 -mcmodel=medany
endif
ARCHCPUFLAGS += -mcmodel=medany
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fno-omit-frame-pointer
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti

5
boards/risc-v/qemu-rv32/rv32-virt/scripts/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# boards/risc-v/rv32m1/rv32m1-vega/scripts/Make.defs
# boards/risc-v/qemu-rv32/rv32-virt/scripts/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
@ -20,7 +20,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
ifeq ($(CONFIG_ARCH_CHIP_QEMU_RV32),y)
LDSCRIPT = ld.script
@ -43,7 +43,6 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce
endif
ARCHCPUFLAGS = -march=rv32imc -mabi=ilp32
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef

7
boards/risc-v/rv32m1/rv32m1-vega/scripts/Make.defs
View file

@ -20,7 +20,7 @@
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
ifeq ($(CONFIG_RV32M1_OPENISA_TOOLCHAIN),y)
CROSSDEV = riscv32-unknown-elf-
@ -49,17 +49,14 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce
endif
ARCHCPURV32IM = -march=rv32imc -mabi=ilp32
ifeq ($(CONFIG_RV32M1_OPENISA_TOOLCHAIN),y)
ifdef CONFIG_ARCH_RISCV_INTXCPT_EXTREGS
ifeq ($(filter 0 1 2 3 4 5 , $(CONFIG_ARCH_RISCV_INTXCPT_EXTREGS)),)
ARCHCPURV32IM = -march=rv32imcxpulpv2
ARCHCPUFLAGS = -march=rv32imcxpulpv2
endif
endif
endif
ARCHCPUFLAGS = $(ARCHCPURV32IM)
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef

2
libs/libc/machine/risc-v/Kconfig
View file

@ -3,7 +3,7 @@
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_RV64GC
if ARCH_RV64
source "libs/libc/machine/risc-v/rv64/Kconfig"
endif

4
libs/libc/machine/risc-v/Make.defs
View file

@ -20,10 +20,10 @@
include $(TOPDIR)/libs/libc/machine/risc-v/common/Make.defs
ifeq ($(CONFIG_ARCH_RV64GC),y)
ifeq ($(CONFIG_ARCH_RV64),y)
include $(TOPDIR)/libs/libc/machine/risc-v/rv64/Make.defs
endif
ifeq ($(CONFIG_ARCH_RV32IM),y)
ifeq ($(CONFIG_ARCH_RV32),y)
include $(TOPDIR)/libs/libc/machine/risc-v/rv32/Make.defs
endif

2
tools/README.txt
View file

@ -1030,7 +1030,7 @@ testbuild.sh
stm32f429i-disco:nsh,CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL
arduino-due:nsh,CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL
/arm,CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL
/risc-v,CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL
/risc-v,CONFIG_RISCV_TOOLCHAIN_GNU_RVGL
The first value is the usual configuration description of the form
<board-name>:<configuration-name> or /<folder-name> and must correspond to a

2
tools/ci/testlist/all.dat
View file

@ -19,7 +19,7 @@
/mips,CONFIG_MIPS32_TOOLCHAIN_PINGUINOL
/risc-v,CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL
/risc-v,CONFIG_RISCV_TOOLCHAIN_GNU_RVGL
/sim

4
tools/ci/testlist/macos.dat
View file

@ -17,9 +17,9 @@
# RISC-V
/risc-v/bl602/bl602evb/configs/wifi,CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL
/risc-v/bl602/bl602evb/configs/wifi,CONFIG_RISCV_TOOLCHAIN_GNU_RVGL
/risc-v/esp32c3/esp32c3-devkit/configs/wapi,CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL
/risc-v/esp32c3/esp32c3-devkit/configs/wapi,CONFIG_RISCV_TOOLCHAIN_GNU_RVGL
# ARM

2
tools/ci/testlist/risc-v.dat
View file

@ -1 +1 @@
/risc-v,CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL
/risc-v,CONFIG_RISCV_TOOLCHAIN_GNU_RVGL