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mpfs/mpfs_irq.c: Enable interrupts on all harts

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Instead of enabling an interrupt on the calling hart, enable it on every
hart. This should balance the interrupt load some, especially in cases
where the interrupt source is enabled only once (which will almost
certainly happen on CPU 0 only).

Signed-off-by: Ville Juven <ville.juven@unikie.com>
This commit is contained in:
Ville Juven 2025-02-10 14:18:43 +02:00 • committed by CeDeROM
parent af0aa78cbc
commit c57c95755d
1 changed files with 14 additions and 13 deletions
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27
arch/risc-v/src/mpfs/mpfs_irq.c
View file

@ -125,9 +125,7 @@ void up_disable_irq(int irq)
PANIC();
}
/* Disable the irq on all harts, we don't know on which it was
* enabled
*/
/* Disable the irq on all harts */
for (i = 0; i < CONFIG_SMP_NCPUS; i++)
{
@ -157,6 +155,7 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
int extirq;
int i;
if (irq == RISCV_IRQ_SOFT)
{
@ -173,19 +172,21 @@ void up_enable_irq(int irq)
else if (irq >= MPFS_IRQ_EXT_START)
{
extirq = irq - MPFS_IRQ_EXT_START;
/* Set enable bit for the irq */
uintptr_t iebase = mpfs_plic_get_iebase(up_cpu_index());
if (0 <= extirq && extirq <= NR_IRQS - MPFS_IRQ_EXT_START)
{
modifyreg32(iebase + (4 * (extirq / 32)), 0, 1 << (extirq % 32));
}
else
if (extirq < 0 || extirq > NR_IRQS - MPFS_IRQ_EXT_START)
{
PANIC();
}
/* Enable the irq on all harts */
for (i = 0; i < CONFIG_SMP_NCPUS; i++)
{
uintptr_t iebase = mpfs_plic_get_iebase(riscv_cpuid_to_hartid(i));
/* Set enable bit for the irq */
modifyreg32(iebase + (4 * (extirq / 32)), 0, 1 << (extirq % 32));
}
}
}