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Use small lock to protect resources related to irq in arch ARM.

Browse source 
Signed-off-by: wangzhi16 <wangzhi16@xiaomi.com>
This commit is contained in:
wangzhi16 2025-01-22 16:08:04 +08:00 • committed by Xiang Xiao
parent 919ed2e3d4
commit c754019f5a
54 changed files with 614 additions and 237 deletions
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44
arch/arm/src/a1x/a1x_irq.c
View file

@ -31,7 +31,7 @@
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
@ -40,6 +40,12 @@
#include "a1x_pio.h"
#include "a1x_irq.h"
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_irq_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -53,14 +59,10 @@
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void a1x_dumpintc(const char *msg, int irq)
static void a1x_dumpintc_nolock(const char *msg, int irq)
{
irqstate_t flags;
/* Dump some relevant ARMv7 register contents */
flags = enter_critical_section();
irqinfo("ARMv7 (%s, irq=%d):\n", msg, irq);
irqinfo(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
@ -95,10 +97,20 @@ static void a1x_dumpintc(const char *msg, int irq)
getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
getreg32(A1X_INTC_PRIO4));
}
leave_critical_section(flags);
static void a1x_dumpintc(const char *msg, int irq)
{
irqstate_t flags;
flags = spin_lock_irqsave(&g_irq_lock);
a1x_dumpintc_nolock(msg, irq);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define a1x_dumpintc_nolock(msg, irq)
# define a1x_dumpintc(msg, irq)
#endif
@ -297,7 +309,7 @@ void up_disable_irq(int irq)
{
/* These operations must be atomic */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
/* Make sure that the interrupt is disabled. */
@ -313,8 +325,8 @@ void up_disable_irq(int irq)
regval |= INTC_MASK(irq);
putreg32(regval, regaddr);
a1x_dumpintc("disable", irq);
leave_critical_section(flags);
a1x_dumpintc_nolock("disable", irq);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#ifdef CONFIG_A1X_PIO_IRQ
@ -345,7 +357,7 @@ void up_enable_irq(int irq)
{
/* These operations must be atomic */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
/* Make sure that the interrupt is enabled. */
@ -361,8 +373,8 @@ void up_enable_irq(int irq)
regval &= ~INTC_MASK(irq);
putreg32(regval, regaddr);
a1x_dumpintc("enable", irq);
leave_critical_section(flags);
a1x_dumpintc_nolock("enable", irq);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#ifdef CONFIG_A1X_PIO_IRQ
@ -398,7 +410,7 @@ int up_prioritize_irq(int irq, int priority)
{
/* These operations must be atomic */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
/* Set the new priority */
@ -408,8 +420,8 @@ int up_prioritize_irq(int irq, int priority)
regval |= INTC_PRIO(irq, priority);
putreg32(regval, regaddr);
a1x_dumpintc("prioritize", irq);
leave_critical_section(flags);
a1x_dumpintc_nolock("prioritize", irq);
spin_unlock_irqrestore(&g_irq_lock, flags);
return OK;
}

2
arch/arm/src/am335x/am335x_irq.c
View file

@ -41,8 +41,10 @@
* Private Data
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
#endif
/****************************************************************************
* Public Data

14
arch/arm/src/at32/at32_irq.c
View file

@ -31,7 +31,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -62,6 +62,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -79,7 +87,7 @@ static void at32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -123,7 +131,7 @@ static void at32_dumpnvic(const char *msg, int irq)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define at32_dumpnvic(msg, irq)

24
arch/arm/src/efm32/efm32_gpioirq.c
View file

@ -31,7 +31,7 @@
#include <assert.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include "arm_internal.h"
#include "hardware/efm32_gpio.h"
@ -44,6 +44,12 @@
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_gpioirq_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -198,7 +204,7 @@ void efm32_gpioirq(gpio_pinset_t pinset)
/* Make sure that the pin interrupt is disabled */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
regval = getreg32(EFM32_GPIO_IEN);
regval &= ~bit;
putreg32(regval, EFM32_GPIO_IEN);
@ -248,7 +254,7 @@ void efm32_gpioirq(gpio_pinset_t pinset)
}
putreg32(regval, EFM32_GPIO_EXTIFALL);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
}
/****************************************************************************
@ -270,11 +276,11 @@ void efm32_gpioirqenable(int irq)
uint32_t regval;
uint32_t bit;
bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
regval = getreg32(EFM32_GPIO_IEN);
regval |= bit;
putreg32(regval, EFM32_GPIO_IEN);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
#else
bitband_set_peripheral(EFM32_GPIO_IEN, (irq - EFM32_IRQ_EXTI0), 1);
#endif
@ -301,11 +307,11 @@ void efm32_gpioirqdisable(int irq)
uint32_t bit;
bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
regval = getreg32(EFM32_GPIO_IEN);
regval &= ~bit;
putreg32(regval, EFM32_GPIO_IEN);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
#else
bitband_set_peripheral(EFM32_GPIO_IEN, (irq - EFM32_IRQ_EXTI0), 0);
#endif
@ -332,11 +338,11 @@ void efm32_gpioirqclear(int irq)
uint32_t bit;
bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
regval = getreg32(EFM32_GPIO_IFC);
regval |= bit;
putreg32(regval, EFM32_GPIO_IFC);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
#else
bitband_set_peripheral(EFM32_GPIO_IFC, (irq - EFM32_IRQ_EXTI0), 1);
#endif

14
arch/arm/src/efm32/efm32_irq.c
View file

@ -31,7 +31,7 @@
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/armv7-m/nvicpri.h>
@ -61,6 +61,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Function
****************************************************************************/
@ -78,7 +86,7 @@ static void efm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -126,7 +134,7 @@ static void efm32_dumpnvic(const char *msg, int irq)
#endif
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define efm32_dumpnvic(msg, irq)

14
arch/arm/src/eoss3/eoss3_irq.c
View file

@ -31,7 +31,7 @@
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/armv7-m/nvicpri.h>
@ -60,6 +60,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -77,7 +85,7 @@ static void eoss3_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -107,7 +115,7 @@ static void eoss3_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define eoss3_dumpnvic(msg, irq)

14
arch/arm/src/gd32f4/gd32f4xx_irq.c
View file

@ -31,7 +31,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -62,6 +62,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -79,7 +87,7 @@ static void gd32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -133,7 +141,7 @@ static void gd32_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define gd32_dumpnvic(msg, irq)

8
arch/arm/src/imx9/imx9_gpioirq.c
View file

@ -33,7 +33,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include "arm_internal.h"
#include "imx9_gpio.h"
@ -64,6 +64,8 @@ struct imx9_portisr_s
static struct imx9_portisr_s g_isrtab[IMX9_GPIO_NPORTS];
static spinlock_t g_gpioirq_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -204,12 +206,12 @@ int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg)
/* Atomically change the handler */
irqstate_t flags = enter_critical_section();
irqstate_t flags = spin_lock_irqsave(&g_gpioirq_lock);
g_isrtab[port].pins[pin].isr = isr;
g_isrtab[port].pins[pin].arg = arg;
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return OK;
}

14
arch/arm/src/imx9/imx9_irq.c
View file

@ -32,7 +32,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -65,6 +65,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -82,7 +90,7 @@ static void imx9_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -210,7 +218,7 @@ static void imx9_dumpnvic(const char *msg, int irq)
# warning Missing logic
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define imx9_dumpnvic(msg, irq)

14
arch/arm/src/imxrt/imxrt_irq.c
View file

@ -31,7 +31,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -64,6 +64,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -81,7 +89,7 @@ static void imxrt_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -209,7 +217,7 @@ static void imxrt_dumpnvic(const char *msg, int irq)
# warning Missing logic
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define imxrt_dumpnvic(msg, irq)

14
arch/arm/src/kinetis/kinetis_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -59,6 +59,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -76,7 +84,7 @@ static void kinetis_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -139,7 +147,7 @@ static void kinetis_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ116_119_PRIORITY));
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define kinetis_dumpnvic(msg, irq)

14
arch/arm/src/kinetis/kinetis_pinirq.c
View file

@ -31,7 +31,7 @@
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
@ -95,6 +95,12 @@ static struct kinetis_pinirq_s g_portdisrs[32];
static struct kinetis_pinirq_s g_porteisrs[32];
#endif
/* Spinlock */
#ifdef HAVE_PORTINTS
static spinlock_t g_pinirq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -297,7 +303,7 @@ int kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
/* Get the table associated with this port */
DEBUGASSERT(port < KINETIS_NPORTS);
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_pinirq_lock);
switch (port)
{
#ifdef CONFIG_KINETIS_PORTAINTS
@ -326,7 +332,7 @@ int kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
break;
#endif
default:
leave_critical_section(flags);
spin_unlock_irqrestore(&g_pinirq_lock, flags);
return -EINVAL;
}
@ -337,7 +343,7 @@ int kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
/* And return the old PIN isr address */
leave_critical_section(flags);
spin_unlock_irqrestore(&g_pinirq_lock, flags);
return OK;
#else
return -ENOSYS;

14
arch/arm/src/kl/kl_gpioirq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
@ -89,6 +89,12 @@ static struct g_portisrs_s g_portaisrs[32];
static struct g_portisrs_s g_portdisrs[32];
#endif
/* Spinlock */
#ifdef HAVE_PORTINTS
static spinlock_t g_gpioirq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -251,7 +257,7 @@ int kl_gpioirqattach(uint32_t pinset, xcpt_t pinisr, void *pinarg)
/* Get the table associated with this port */
DEBUGASSERT(port < KL_NPORTS);
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
switch (port)
{
#ifdef CONFIG_KL_PORTAINTS
@ -265,7 +271,7 @@ int kl_gpioirqattach(uint32_t pinset, xcpt_t pinisr, void *pinarg)
break;
#endif
default:
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return NULL;
}
@ -276,7 +282,7 @@ int kl_gpioirqattach(uint32_t pinset, xcpt_t pinisr, void *pinarg)
/* And return the old PIN isr address */
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return OK;
#else

14
arch/arm/src/kl/kl_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -48,6 +48,14 @@
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -65,7 +73,7 @@ static void kl_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
@ -89,7 +97,7 @@ static void kl_dumpnvic(const char *msg, int irq)
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else

8
arch/arm/src/lc823450/lc823450_irq.c
View file

@ -30,7 +30,6 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/board.h>
@ -124,7 +123,7 @@ static void lc823450_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_lc823450_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
@ -166,7 +165,7 @@ static void lc823450_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_lc823450_irq_lock, flags);
}
#else
# define lc823450_dumpnvic(msg, irq)
@ -186,7 +185,6 @@ static void lc823450_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG
static int lc823450_nmi(int irq, void *context, void *arg)
{
enter_critical_section();
irqinfo("PANIC!!! NMI received\n");
PANIC();
return 0;
@ -194,7 +192,6 @@ static int lc823450_nmi(int irq, void *context, void *arg)
static int lc823450_pendsv(int irq, void *context, void *arg)
{
enter_critical_section();
irqinfo("PANIC!!! PendSV received\n");
PANIC();
return 0;
@ -202,7 +199,6 @@ static int lc823450_pendsv(int irq, void *context, void *arg)
static int lc823450_reserved(int irq, void *context, void *arg)
{
enter_critical_section();
irqinfo("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;

14
arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -60,6 +60,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -77,7 +85,7 @@ static void lpc17_40_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -111,7 +119,7 @@ static void lpc17_40_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define lpc17_40_dumpnvic(msg, irq)

15
arch/arm/src/lpc214x/lpc214x_irq.c
View file

@ -29,12 +29,19 @@
#include <stdint.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include "arm.h"
#include "chip.h"
#include "arm_internal.h"
#include "lpc214x_vic.h"
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_irq_lock = SP_UNLOCKED;
/****************************************************************************
* Public Functions
****************************************************************************/
@ -116,7 +123,7 @@ void up_enable_irq(int irq)
{
/* Disable all interrupts */
irqstate_t flags = enter_critical_section();
irqstate_t flags = spin_lock_irqsave(&g_irq_lock);
/* Enable the irq by setting the corresponding bit in the VIC
* Interrupt Enable register.
@ -124,7 +131,7 @@ void up_enable_irq(int irq)
uint32_t val = vic_getreg(LPC214X_VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), LPC214X_VIC_INTENABLE_OFFSET);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
}
@ -147,7 +154,7 @@ void up_attach_vector(int irq, int vector, vic_vector_t handler)
/* Disable all interrupts */
irqstate_t flags = enter_critical_section();
irqstate_t flags = spin_lock_irqsave(&g_irq_lock);
/* Save the vector address */
@ -158,7 +165,7 @@ void up_attach_vector(int irq, int vector, vic_vector_t handler)
vic_putreg(((irq << LPC214X_VECTCNTL_IRQSHIFT) |
LPC214X_VECTCNTL_ENABLE),
LPC214X_VIC_VECTCNTL0_OFFSET + offset);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
}
#endif

15
arch/arm/src/lpc2378/lpc23xx_irq.c
View file

@ -46,6 +46,7 @@
#include <errno.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include "arm.h"
#include "chip.h"
@ -53,6 +54,12 @@
#include "lpc2378.h"
#include "lpc23xx_vic.h"
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_irq_lock = SP_UNLOCKED;
/****************************************************************************
* Public Functions
****************************************************************************/
@ -153,7 +160,7 @@ void up_enable_irq(int irq)
{
/* Disable all interrupts */
irqstate_t flags = enter_critical_section();
irqstate_t flags = spin_lock_irqsave(&g_irq_lock);
/* Enable the irq by setting the corresponding bit in the VIC Interrupt
* Enable register.
@ -161,7 +168,7 @@ void up_enable_irq(int irq)
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
}
@ -239,7 +246,7 @@ void up_attach_vector(int irq, int vector, vic_vector_t handler)
/* Disable all interrupts */
irqstate_t flags = enter_critical_section();
irqstate_t flags = spin_lock_irqsave(&g_irq_lock);
/* Save the vector address */
@ -250,7 +257,7 @@ void up_attach_vector(int irq, int vector, vic_vector_t handler)
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
}
#endif

14
arch/arm/src/lpc43xx/lpc43_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -60,6 +60,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -77,7 +85,7 @@ static void lpc43_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -117,7 +125,7 @@ static void lpc43_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define lpc43_dumpnvic(msg, irq)

18
arch/arm/src/lpc54xx/lpc54_gpioirq.c
View file

@ -30,7 +30,7 @@
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include "arm_internal.h"
#include "hardware/lpc54_syscon.h"
@ -71,6 +71,10 @@ static const uint8_t g_pinirq[MAX_PININT] =
LPC54_IRQ_PININT4, LPC54_IRQ_PININT5, LPC54_IRQ_PININT6, LPC54_IRQ_PININT7
};
/* Spinlock */
static spinlock_t g_gpioirq_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -86,7 +90,7 @@ static const uint8_t g_pinirq[MAX_PININT] =
static int lpc54_alloc_pinint(lpc54_pinset_t pinset)
{
irqstate_t flags = enter_critical_section();
irqstate_t flags = spin_lock_irqsave(&g_gpioirq_lock);
int pin;
/* REVISIT: This is overlying complex in the current design. There is
@ -102,12 +106,12 @@ static int lpc54_alloc_pinint(lpc54_pinset_t pinset)
if ((g_pinints & mask) == 0)
{
g_pinints |= mask;
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return pin;
}
}
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return -ENOSPC;
}
@ -284,7 +288,7 @@ int lpc54_gpio_irqno(lpc54_pinset_t pinset)
int portpin = pinset & GPIO_PORTPIN_MASK;
int i;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
/* Find the PININT index that as the assignment to the this port and pin */
@ -295,12 +299,12 @@ int lpc54_gpio_irqno(lpc54_pinset_t pinset)
regval = getreg32(regaddr) & GPIO_PORTPIN_MASK;
if (regval == portpin)
{
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return (int)g_pinirq[i];
}
}
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return -ENOENT;
}

14
arch/arm/src/lpc54xx/lpc54_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -59,6 +59,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -76,7 +84,7 @@ static void lpc54_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -116,7 +124,7 @@ static void lpc54_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define lpc54_dumpnvic(msg, irq)

14
arch/arm/src/max326xx/common/max326_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -59,6 +59,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -76,7 +84,7 @@ static void max326_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -117,7 +125,7 @@ static void max326_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define max326_dumpnvic(msg, irq)

14
arch/arm/src/mx8mp/mx8mp_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -60,6 +60,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -77,7 +85,7 @@ static void mx8mp_dump_nvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -147,7 +155,7 @@ static void mx8mp_dump_nvic(const char *msg, int irq)
irqinfo(" %08x %08x\n",
getreg32(NVIC_IRQ144_147_PRIORITY),
getreg32(NVIC_IRQ148_151_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define mx8mp_dump_nvic(msg, irq)

14
arch/arm/src/nrf52/nrf52_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -61,6 +61,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -78,7 +86,7 @@ static void nrf52_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -118,7 +126,7 @@ static void nrf52_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define nrf52_dumpnvic(msg, irq)

14
arch/arm/src/nrf53/nrf53_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv8-m/nvicpri.h>
@ -61,6 +61,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -78,7 +86,7 @@ static void nrf53_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -118,7 +126,7 @@ static void nrf53_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define nrf53_dumpnvic(msg, irq)

14
arch/arm/src/nrf91/nrf91_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv8-m/nvicpri.h>
@ -61,6 +61,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -78,7 +86,7 @@ static void nrf91_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -118,7 +126,7 @@ static void nrf91_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define nrf91_dumpnvic(msg, irq)

14
arch/arm/src/nuc1xx/nuc_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -48,6 +48,14 @@
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -65,7 +73,7 @@ static void nuc_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
@ -89,7 +97,7 @@ static void nuc_dumpnvic(const char *msg, int irq)
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else

14
arch/arm/src/rp2040/rp2040_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -52,6 +52,14 @@
# define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE)
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Public Data
****************************************************************************/
@ -95,7 +103,7 @@ static void rp2040_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
@ -119,7 +127,7 @@ static void rp2040_dumpnvic(const char *msg, int irq)
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else

14
arch/arm/src/rp23xx/rp23xx_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -52,6 +52,14 @@
# define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE)
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Public Data
****************************************************************************/
@ -95,7 +103,7 @@ static void rp23xx_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER0: %08x ICER0: %08x\n",
@ -137,7 +145,7 @@ static void rp23xx_dumpnvic(const char *msg, int irq)
irqinfo(" SHPR3: %08x\n",
getreg32(NVIC_SYSH12_15_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else

14
arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -49,6 +49,14 @@
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -279,7 +287,7 @@ void s32k11x_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
@ -303,7 +311,7 @@ void s32k11x_dumpnvic(const char *msg, int irq)
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else

14
arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -59,6 +59,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -76,7 +84,7 @@ static void s32k14x_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -151,7 +159,7 @@ static void s32k14x_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ152_155_PRIORITY),
getreg32(NVIC_IRQ156_159_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define s32k14x_dumpnvic(msg, irq)

14
arch/arm/src/s32k1xx/s32k1xx_pinirq.c
View file

@ -31,7 +31,7 @@
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
@ -95,6 +95,12 @@ static struct s32k1xx_pinirq_s g_portdisrs[32];
static struct s32k1xx_pinirq_s g_porteisrs[32];
#endif
/* Spinlock */
#ifdef HAVE_PORTINTS
static spinlock_t g_pinirq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -297,7 +303,7 @@ int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
/* Get the table associated with this port */
DEBUGASSERT(port < S32K1XX_NPORTS);
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_pinirq_lock);
switch (port)
{
#ifdef CONFIG_S32K1XX_PORTAINTS
@ -326,7 +332,7 @@ int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
break;
#endif
default:
leave_critical_section(flags);
spin_unlock_irqrestore(&g_pinirq_lock, flags);
return -EINVAL;
}
@ -337,7 +343,7 @@ int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
/* And return the old PIN isr address */
leave_critical_section(flags);
spin_unlock_irqrestore(&g_pinirq_lock, flags);
return OK;
#else
return -ENOSYS;

14
arch/arm/src/s32k3xx/s32k3xx_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -64,6 +64,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -81,7 +89,7 @@ static void s32k3xx_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -156,7 +164,7 @@ static void s32k3xx_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ152_155_PRIORITY),
getreg32(NVIC_IRQ156_159_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define s32k3xx_dumpnvic(msg, irq)

12
arch/arm/src/s32k3xx/s32k3xx_pinirq.c
View file

@ -31,7 +31,7 @@
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
@ -75,6 +75,8 @@ static struct s32k3xx_pinirq_s g_eirqisrs[32];
static struct s32k3xx_pinirq_s g_wkpuisrs[60];
#endif
static spinlock_t g_pinirq_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -280,12 +282,12 @@ int s32k3xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
/* Attach the interrupt handler */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_pinirq_lock);
g_eirqisrs[index].handler = pinisr;
g_eirqisrs[index].arg = arg;
leave_critical_section(flags);
spin_unlock_irqrestore(&g_pinirq_lock, flags);
return OK;
}
#endif /* CONFIG_S32K3XX_EIRQINTS */
@ -299,12 +301,12 @@ int s32k3xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
/* Attach the interrupt handler */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_pinirq_lock);
g_wkpuisrs[index].handler = pinisr;
g_wkpuisrs[index].arg = arg;
leave_critical_section(flags);
spin_unlock_irqrestore(&g_pinirq_lock, flags);
return OK;
}
#endif /* CONFIG_S32K3XX_WKPUINTS */

14
arch/arm/src/sam34/sam_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -62,6 +62,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -79,7 +87,7 @@ static void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -137,7 +145,7 @@ static void sam_dumpnvic(const char *msg, int irq)
# warning Missing logic
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define sam_dumpnvic(msg, irq)

29
arch/arm/src/sama5/sam_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -92,6 +92,12 @@ static const uint32_t g_h64mxpids[3] =
};
#endif
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_irq_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -107,9 +113,6 @@ static const uint32_t g_h64mxpids[3] =
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void sam_dumpaic(const char *msg, uintptr_t base, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("AIC (%s, base=%08x irq=%d):\n", msg, base, irq);
/* Select the register set associated with this irq */
@ -151,8 +154,6 @@ static void sam_dumpaic(const char *msg, uintptr_t base, int irq)
getreg32(base + SAM_AIC_DCR_OFFSET),
getreg32(base + SAM_AIC_WPMR_OFFSET),
getreg32(base + SAM_AIC_WPSR_OFFSET));
leave_critical_section(flags);
}
#else
# define sam_dumpaic(msg, base, irq)
@ -670,7 +671,7 @@ static void sam_disable_irq(uintptr_t base, int irq)
{
/* These operations must be atomic */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
/* Select the register set associated with this irq */
@ -680,7 +681,7 @@ static void sam_disable_irq(uintptr_t base, int irq)
putreg32(AIC_IDCR_INTD, base + SAM_AIC_IDCR_OFFSET);
sam_dumpaic("disable", base, irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#ifdef CONFIG_SAMA5_PIO_IRQ
else
@ -722,7 +723,7 @@ static void sam_enable_irq(uintptr_t base, int irq)
{
/* These operations must be atomic */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
/* Select the register set associated with this irq */
@ -732,7 +733,7 @@ static void sam_enable_irq(uintptr_t base, int irq)
putreg32(AIC_IECR_INTEN, base + SAM_AIC_IECR_OFFSET);
sam_dumpaic("enable", base, irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#ifdef CONFIG_SAMA5_PIO_IRQ
else
@ -781,7 +782,7 @@ static int sam_prioritize_irq(uint32_t base, int irq, int priority)
{
/* These operations must be atomic */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
/* Select the register set associated with this irq */
@ -802,7 +803,7 @@ static int sam_prioritize_irq(uint32_t base, int irq, int priority)
putreg32(AIC_WPMR_WPKEY | AIC_WPMR_WPEN, base + SAM_AIC_WPMR_OFFSET);
sam_dumpaic("prioritize", base, irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
return OK;
@ -844,7 +845,7 @@ static void _sam_irq_srctype(uintptr_t base, int irq,
/* These operations must be atomic */
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
/* Select the register set associated with this irq */
@ -865,7 +866,7 @@ static void _sam_irq_srctype(uintptr_t base, int irq,
putreg32(AIC_WPMR_WPKEY | AIC_WPMR_WPEN, base + SAM_AIC_WPMR_OFFSET);
sam_dumpaic("srctype", base, irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
void sam_irq_srctype(int irq, enum sam_srctype_e srctype)

14
arch/arm/src/samd2l2/sam_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -48,6 +48,14 @@
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -270,7 +278,7 @@ void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
@ -294,7 +302,7 @@ void sam_dumpnvic(const char *msg, int irq)
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else

14
arch/arm/src/samd5e5/sam_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -62,6 +62,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -79,7 +87,7 @@ static void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -175,7 +183,7 @@ static void sam_dumpnvic(const char *msg, int irq)
# warning Missing logic
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define sam_dumpnvic(msg, irq)

14
arch/arm/src/samv7/sam_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -64,6 +64,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -81,7 +89,7 @@ static void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -139,7 +147,7 @@ static void sam_dumpnvic(const char *msg, int irq)
# warning Missing logic
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define sam_dumpnvic(msg, irq)

16
arch/arm/src/stm32/stm32_irq.c
View file

@ -31,7 +31,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -62,6 +62,16 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -79,7 +89,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -123,7 +133,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define stm32_dumpnvic(msg, irq)

14
arch/arm/src/stm32f0l0g0/stm32_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -49,6 +49,14 @@
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -66,7 +74,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
@ -90,7 +98,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else

14
arch/arm/src/stm32f7/stm32_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -63,6 +63,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -80,7 +88,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08" PRIx32 " VECTAB: %08" PRIx32 "\n",
@ -159,7 +167,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
# warning Missing logic
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define stm32_dumpnvic(msg, irq)

14
arch/arm/src/stm32h5/stm32_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv8-m/nvicpri.h>
@ -59,6 +59,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -76,7 +84,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -105,7 +113,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define stm32_dumpnvic(msg, irq)

14
arch/arm/src/stm32h7/stm32_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
@ -63,6 +63,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -80,7 +88,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -154,7 +162,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
/* TODO: Make sure this covers all interrupts that are available. */
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define stm32_dumpnvic(msg, irq)

14
arch/arm/src/stm32l4/stm32l4_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -59,6 +59,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -76,7 +84,7 @@ static void stm32l4_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -120,7 +128,7 @@ static void stm32l4_dumpnvic(const char *msg, int irq)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define stm32l4_dumpnvic(msg, irq)

14
arch/arm/src/stm32l5/stm32l5_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv8-m/nvicpri.h>
@ -59,6 +59,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -76,7 +84,7 @@ static void stm32l5_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -105,7 +113,7 @@ static void stm32l5_dumpnvic(const char *msg, int irq)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define stm32l5_dumpnvic(msg, irq)

14
arch/arm/src/stm32u5/stm32_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv8-m/nvicpri.h>
@ -59,6 +59,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -76,7 +84,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -105,7 +113,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define stm32_dumpnvic(msg, irq)

14
arch/arm/src/stm32wb/stm32wb_irq.c
View file

@ -30,7 +30,7 @@
#include <debug.h>
#include <assert.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include "arm_internal.h"
@ -60,6 +60,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -77,7 +85,7 @@ static void stm32wb_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -121,7 +129,7 @@ static void stm32wb_dumpnvic(const char *msg, int irq)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define stm32wb_dumpnvic(msg, irq)

14
arch/arm/src/stm32wl5/stm32wl5_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -59,6 +59,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -76,7 +84,7 @@ static void stm32wl5_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -120,7 +128,7 @@ static void stm32wl5_dumpnvic(const char *msg, int irq)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define stm32wl5_dumpnvic(msg, irq)

10
arch/arm/src/tiva/cc13xx/cc13xx_gpioirq.c
View file

@ -26,7 +26,7 @@
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <stdint.h>
#include <string.h>
@ -61,6 +61,10 @@ struct gpio_handler_s
static struct gpio_handler_s g_gpio_inthandler[TIVA_NIRQ_PINS];
/* Spinlock */
static spinlock_t g_gpioirq_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -176,7 +180,7 @@ int tiva_gpioirqattach(pinconfig_t pinconfig, xcpt_t isr, void *arg)
if (dio < TIVA_NDIO)
{
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
/* If the new ISR is NULL, then the ISR is being detached.
* In this case, disable the ISR and direct any interrupts
@ -199,7 +203,7 @@ int tiva_gpioirqattach(pinconfig_t pinconfig, xcpt_t isr, void *arg)
tiva_gpioirqenable(pinconfig);
}
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
}
return OK;

78
arch/arm/src/tiva/common/lmxx_tm4c_gpioirq.c
View file

@ -26,7 +26,7 @@
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <inttypes.h>
#include <stdint.h>
@ -70,6 +70,10 @@ struct gpio_handler_s
static struct gpio_handler_s g_gpioportirqvector[TIVA_NIRQ_PINS];
/* Spinlock */
static spinlock_t g_gpioirq_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -287,11 +291,11 @@ static int tiva_gpioporthandler(uint8_t port, void *context)
static int tiva_gpioahandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTA >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -300,11 +304,11 @@ static int tiva_gpioahandler(int irq, void *context, void *arg)
static int tiva_gpiobhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTB >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -313,11 +317,11 @@ static int tiva_gpiobhandler(int irq, void *context, void *arg)
static int tiva_gpiochandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTC >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -326,11 +330,11 @@ static int tiva_gpiochandler(int irq, void *context, void *arg)
static int tiva_gpiodhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTD >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -339,11 +343,11 @@ static int tiva_gpiodhandler(int irq, void *context, void *arg)
static int tiva_gpioehandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTE >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -352,11 +356,11 @@ static int tiva_gpioehandler(int irq, void *context, void *arg)
static int tiva_gpiofhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTF >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -365,11 +369,11 @@ static int tiva_gpiofhandler(int irq, void *context, void *arg)
static int tiva_gpioghandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTG >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -378,11 +382,11 @@ static int tiva_gpioghandler(int irq, void *context, void *arg)
static int tiva_gpiohhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTH >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -391,11 +395,11 @@ static int tiva_gpiohhandler(int irq, void *context, void *arg)
static int tiva_gpiojhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTJ >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -404,11 +408,11 @@ static int tiva_gpiojhandler(int irq, void *context, void *arg)
static int tiva_gpiokhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTK >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -417,11 +421,11 @@ static int tiva_gpiokhandler(int irq, void *context, void *arg)
static int tiva_gpiolhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTL >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -430,11 +434,11 @@ static int tiva_gpiolhandler(int irq, void *context, void *arg)
static int tiva_gpiomhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTM >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -443,11 +447,11 @@ static int tiva_gpiomhandler(int irq, void *context, void *arg)
static int tiva_gpionhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTN >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -456,11 +460,11 @@ static int tiva_gpionhandler(int irq, void *context, void *arg)
static int tiva_gpiophandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTP >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -469,11 +473,11 @@ static int tiva_gpiophandler(int irq, void *context, void *arg)
static int tiva_gpioqhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTQ >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -482,11 +486,11 @@ static int tiva_gpioqhandler(int irq, void *context, void *arg)
static int tiva_gpiorhandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTR >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -495,11 +499,11 @@ static int tiva_gpiorhandler(int irq, void *context, void *arg)
static int tiva_gpioshandler(int irq, void *context, void *arg)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
up_disable_irq(irq);
int ret = tiva_gpioporthandler((GPIO_PORTS >> GPIO_PORT_SHIFT), context);
up_enable_irq(irq);
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
return ret;
}
#endif
@ -646,7 +650,7 @@ int tiva_gpioirqattach(pinconfig_t pinconfig, xcpt_t isr, void *arg)
if (port < TIVA_NPORTS)
{
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_gpioirq_lock);
/* If the new ISR is NULL, then the ISR is being detached.
* In this case, disable the ISR and direct any interrupts
@ -670,7 +674,7 @@ int tiva_gpioirqattach(pinconfig_t pinconfig, xcpt_t isr, void *arg)
tiva_gpioirqenable(pinconfig);
}
leave_critical_section(flags);
spin_unlock_irqrestore(&g_gpioirq_lock, flags);
}
return OK;

14
arch/arm/src/tiva/common/tiva_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -60,6 +60,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -77,7 +85,7 @@ static void tiva_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
@ -188,7 +196,7 @@ static void tiva_dumpnvic(const char *msg, int irq)
#if TIVA_IRQ_NEXTINT > 159
# warning Missing output
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define tiva_dumpnvic(msg, irq)

12
arch/arm/src/tms570/tms570_gioirq.c
View file

@ -34,7 +34,7 @@
#include <nuttx/init.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <arch/board/board.h>
#include "arm_internal.h"
@ -43,6 +43,12 @@
#ifdef CONFIG_TMS570_GIO_IRQ
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_irq_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
@ -132,7 +138,7 @@ void tms570_gioirq(gio_pinset_t pinset)
if ((pinset & GIO_MODE_MASK) == GIO_INPUT && port < TMS570_NIRQPORTS)
{
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
switch (pinset & GIO_INT_MASK)
{
case GIO_INT_NONE:
@ -182,7 +188,7 @@ void tms570_gioirq(gio_pinset_t pinset)
break;
}
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
}

14
arch/arm/src/xmc4/xmc4_irq.c
View file

@ -30,7 +30,7 @@
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/spinlock.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
@ -58,6 +58,14 @@
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Private Data
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static spinlock_t g_irq_lock = SP_UNLOCKED;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -75,7 +83,7 @@ static void xmc4_dump_nvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
flags = spin_lock_irqsave(&g_irq_lock);
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
@ -138,7 +146,7 @@ static void xmc4_dump_nvic(const char *msg, int irq)
getreg32(NVIC_IRQ116_119_PRIORITY));
#endif
leave_critical_section(flags);
spin_unlock_irqrestore(&g_irq_lock, flags);
}
#else
# define xmc4_dump_nvic(msg, irq)