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arch/arch/src/samv7: add support for PIC32CZ CA70 series

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PIC32CZ CA70 family is pin to pin and binary compatible with
SAMV70/SAME70 families, therefore the support is placed in samv7
directory. The only difference is larger RAM memory compared to SAM
families.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit is contained in:
Michal Lenc 2025-07-23 09:34:55 +02:00 • committed by Xiang Xiao
parent e745b8ec7f
commit cbfaf4224a
9 changed files with 200 additions and 5 deletions
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123
arch/arm/include/samv7/chip.h
View file

@ -375,6 +375,129 @@
# define SAMV7_NACC 1 /* 1 Analog comparator */
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
/* PIC32CZCA70 - 2048 Kbytes FLASH / 512 Kbytes SRAM
*
* These microcontrollers are fully pin-to-pin compatible with
* SAME70/S70/V70/V71 family of microcontrollers, but they offer
* enhanced memory capabilities. The code written for SAM series
* should be binary compatible with PIC32CZ CA70/MC70 series.
*
* NOTE: CA80/CA90 is not compatible, these are completely different chips.
*/
#elif defined(CONFIG_ARCH_CHIP_PIC32CZCA70)
# define SAMV7_FLASH_SIZE (2048*1024)
# define SAMV7_SRAM_SIZE (512*1024)
# define SAMV7_BSRAM_SIZE (1*1024)
#if defined(CONFIG_ARCH_CHIP_PIC32CZCA70064)
/* Peripherals */
# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
# define SAMV7_NADC12 5 /* 5 12-bit ADC channels */
# define SAMV7_NDAC12 1 /* 1 12-bit DAC channels */
# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
# define SAMV7_NTCCHIO 3 /* 3 Timer/counter channels I/O */
# define SAMV7_NUSART 0 /* No USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 0 /* No Quad SPI */
# define SAMV7_NQSPI_SPI 1 /* QSPI functions in SPI mode only */
# define SAMV7_NSPI 0 /* No SPI */
# define SAMV7_NTWIHS 2 /* 2 TWIHS */
# define SAMV7_NHSMCI4 0 /* No 4-bit HSMCI port */
# define SAMV7_NCAN 1 /* 1 CAN port */
# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
# define SAMV7_NEMACMII 0 /* No Ethernet MAC MII interface */
# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
# define SAMV7_NISI12 0 /* No 12-bit ISI interface */
# define SAMV7_NISI8 1 /* 1 8-bit ISI interface */
# define SAMV7_NSSC 1 /* 1 SSC */
# define SAMV7_NUDPHS 0 /* No USB high speed device */
# define SAMV7_NUHPHS 0 /* No USB high speed embedded Mini-Host */
# define SAMV7_NUDPFS 1 /* 1 USB full speed device */
# define SAMV7_NUHPFS 1 /* 1 USB full speed embedded host */
# define SAMV7_NACC 1 /* 1 Analog comparator */
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
#elif defined(CONFIG_ARCH_CHIP_PIC32CZCA70100)
/* Peripherals */
# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
# define SAMV7_NADC12 10 /* 10 12-bit ADC channels */
# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
# define SAMV7_NTCCHIO 9 /* 9 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 1 /* 1 Quad SPI */
# define SAMV7_NQSPI_SPI 0 /* QSPI functions in SPI mode only */
# define SAMV7_NSPI 1 /* 1 SPI, SPI0 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
# define SAMV7_NCAN 2 /* 2 CAN ports */
# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
# define SAMV7_NSSC 1 /* 1 SSC */
# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
# define SAMV7_NUDPFS 0 /* No USB full speed device */
# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
# define SAMV7_NACC 1 /* 1 Analog comparator */
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
#elif defined(CONFIG_ARCH_CHIP_PIC32CZCA70144)
/* Peripherals */
# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
# define SAMV7_NEBI 1 /* Have External Bus Interface (EBI) */
# define SAMV7_NSDRAMC 1 /* Have SDRAM controller (SDRAMC) */
# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
# define SAMV7_NADC12 24 /* 24 12-bit ADC channels */
# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
# define SAMV7_NTCCHIO 36 /* 36 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 1 /* 1 Quad SPI */
# define SAMV7_NQSPI_SPI 0 /* QSPI functions in SPI mode only */
# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
# define SAMV7_NCAN 2 /* 2 CAN ports */
# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
# define SAMV7_NSSC 1 /* 1 SSC */
# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
# define SAMV7_NUDPFS 0 /* No USB full speed device */
# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
# define SAMV7_NACC 1 /* 1 Analog comparator */
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
#else
# error "Unknown package of PIC32CZCA70 chip"
#endif
#else
# error "Unknown SAMV7 chip type"
#endif

2
arch/arm/include/samv7/irq.h
View file

@ -65,7 +65,7 @@
#define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_SAMV71)
#if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_PIC32CZCA70)
# include <arch/samv7/samv71_irq.h>
#elif defined(CONFIG_ARCH_CHIP_SAME70)
# include <arch/samv7/same70_irq.h>

59
arch/arm/src/samv7/Kconfig
View file

@ -121,6 +121,50 @@ config ARCH_CHIP_SAMV71J21
select SAMV7_MEM_FLASH_2048
select SAMV7_MEM_RAM_384
config ARCH_CHIP_PIC32CZCA70064
bool "PIC32CZ CA70 064"
select ARCH_CHIP_PIC32CZCA70
select SAMV7_MEM_FLASH_2048
select SAMV7_MEM_RAM_512
select SAMV7_QSPI_IS_SPI
select SAMV7_HAVE_USBFS
select SAMV7_HAVE_ISI8
config ARCH_CHIP_PIC32CZCA70100
bool "PIC32CZ CA70 100"
select ARCH_CHIP_PIC32CZCA70
select SAMV7_MEM_FLASH_2048
select SAMV7_MEM_RAM_512
select SAMV7_QSPI_IS_SPI
select SAMV7_HAVE_MCAN1
select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SPI0
select SAMV7_HAVE_TWIHS2
select SAMV7_HAVE_USBHS
select SAMV7_HAVE_USART0
select SAMV7_HAVE_USART1
select SAMV7_HAVE_USART2
config ARCH_CHIP_PIC32CZCA70144
bool "PIC32CZ CA70 144"
select ARCH_CHIP_PIC32CZCA70
select SAMV7_MEM_FLASH_2048
select SAMV7_MEM_RAM_512
select SAMV7_QSPI_IS_SPI
select SAMV7_HAVE_MCAN1
select SAMV7_HAVE_DAC1 if !SAMV7_EMAC0
select SAMV7_HAVE_EBI
select SAMV7_HAVE_HSMCI0
select SAMV7_HAVE_SDRAMC
select SAMV7_HAVE_SPI0
select SAMV7_HAVE_SPI1
select SAMV7_HAVE_TWIHS2
select SAMV7_HAVE_USBHS
select SAMV7_HAVE_USART0
select SAMV7_HAVE_USART1
select SAMV7_HAVE_USART2
endchoice # Atmel SAMV7 Chip Selection
config ARCH_CHIP_SAME70
@ -226,6 +270,16 @@ config ARCH_CHIP_SAMV71J
select SAMV7_HAVE_USBFS
select SAMV7_HAVE_ISI8
config ARCH_CHIP_PIC32CZCA70
bool
default n
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU # REVISIT
select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM
select ARMV7M_HAVE_DTCM
# Chip Capabilities
config SAMV7_MEM_FLASH_512
@ -254,10 +308,15 @@ config SAMV7_MEM_RAM_384
bool
default n
config SAMV7_MEM_RAM_512
bool
default n
config ARCH_CHIP_SAMV7_MEM_RAM
hex
default 0x40000 if SAMV7_MEM_RAM_256
default 0x60000 if SAMV7_MEM_RAM_384
default 0x80000 if SAMV7_MEM_RAM_512
config SAMV7_MCAN
bool

2
arch/arm/src/samv7/hardware/sam_memorymap.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_SAMV71)
#if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_PIC32CZCA70)
# include "hardware/samv71_memorymap.h"
#elif defined(CONFIG_ARCH_CHIP_SAME70)
# include "hardware/same70_memorymap.h"

2
arch/arm/src/samv7/hardware/sam_pinmap.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_SAMV71)
#if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_PIC32CZCA70)
# include "hardware/samv71_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_SAME70)
# include "hardware/same70_pinmap.h"

6
arch/arm/src/samv7/sam_emac.c
View file

@ -4770,13 +4770,19 @@ int sam_emac_initialize(int intf)
* If both emacs are enabled, this code will be run twice, which
* should not be a problem as the result will be the same each time
* it is run.
*
* PIC32CZ CA70 family is always a revision B, therefore it has 6 queues.
*/
#ifdef CONFIG_ARCH_CHIP_PIC32CZCA70
g_emac_nqueues = EMAC_NQUEUES_REVB;
#else
regval = getreg32(SAM_CHIPID_CIDR);
if (((regval & CHIPID_CIDR_VERSION_MASK) >> CHIPID_CIDR_VERSION_SHIFT) > 0)
{
g_emac_nqueues = EMAC_NQUEUES_REVB; /* Change to Rev. B with 6 queues */
}
#endif
#if defined(CONFIG_SAMV7_EMAC0)
if (intf == EMAC0_INTF)

3
arch/arm/src/samv7/sam_hsmci.c
View file

@ -82,7 +82,8 @@
/* System Bus Interfaces */
#if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_SAME70)
#if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_SAME70) || \
defined(CONFIG_ARCH_CHIP_PIC32CZCA70)
# define HSMCI_SYSBUS_IF DMACH_FLAG_PERIPHAHB_AHB_IF1
# define MEMORY_SYSBUS_IF DMACH_FLAG_MEMAHB_AHB_IF0
#else

6
arch/arm/src/samv7/sam_mcan.c
View file

@ -4380,8 +4380,14 @@ struct can_dev_s *sam_mcan_initialize(int port)
/* Get the revision of the chip (A or B) */
#ifdef CONFIG_ARCH_CHIP_PIC32CZCA70
/* PIC32CZ CA70 series always have revision B MCAN */
priv->rev = 1;
#else
regval = getreg32(SAM_CHIPID_CIDR);
priv->rev = regval & CHIPID_CIDR_VERSION_MASK;
#endif
/* Set the initial bit timing. This might change subsequently
* due to IOCTL command processing.

2
arch/arm/src/samv7/sam_periphclks.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_SAMV71)
#if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_PIC32CZCA70)
# include "samv71_periphclks.h"
#elif defined(CONFIG_ARCH_CHIP_SAME70)
# include "same70_periphclks.h"