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risc-v/esp32-c3: Adds systimer support and make rt_timer rely on it

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This commit is contained in:
Sara Souza 2021-07-08 16:37:55 -03:00 • committed by Xiang Xiao
parent 3c393d6dfc
commit cdbfacc1fe
5 changed files with 294 additions and 64 deletions
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7
arch/risc-v/src/esp32c3/Kconfig
View file

@ -151,7 +151,9 @@ config ESP32C3_CPU_FREQ_MHZ
config ESP32C3_RT_TIMER
bool "Real-time Timer"
default n
select ESP32C3_TIMER0
select ESP32C3_TIMER
---help---
Real-time Timer is relying upon the Systimer 1.
config ESP32C3_DISABLE_STDC_ATOMIC
bool "Disable standard C atomic"
@ -166,7 +168,6 @@ config ESP32C3_WIRELESS
bool
default n
select ESP32C3_RT_TIMER
select ESP32C3_TIMER0
menu "ESP32-C3 Peripheral Support"
@ -309,7 +310,6 @@ config ESP32C3_WIRELESS
select NET
select ARCH_PHY_INTERRUPT
select ESP32C3_RT_TIMER
select ESP32C3_TIMER0
---help---
Enable Wireless support
@ -876,7 +876,6 @@ config ESP32C3_AUTO_SLEEP
default n
select PM
select ESP32C3_RT_TIMER
select ESP32C3_TIMER0
select ESP32C3_TICKLESS
---help---
Enable ESP32-C3 Auto-sleep

41
arch/risc-v/src/esp32c3/esp32c3_rt_timer.c
View file

@ -57,8 +57,10 @@
#define RT_TIMER_TASK_PRIORITY CONFIG_ESP32C3_RT_TIMER_TASK_PRIORITY
#define RT_TIMER_TASK_STACK_SIZE CONFIG_ESP32C3_RT_TIMER_TASK_STACK_SIZE
#define ESP32C3_TIMER_PRESCALER (APB_CLK_FREQ / (1000 * 1000))
#define ESP32C3_RT_TIMER 0 /* Timer 0 */
#define CYCLES_PER_USEC 16 /* Timer running at 16 MHz*/
#define USEC_TO_CYCLES(u) ((u) * CYCLES_PER_USEC)
#define CYCLES_TO_USEC(c) ((c) / CYCLES_PER_USEC)
#define ESP32C3_RT_TIMER ESP32C3_SYSTIM /* Systimer 1 */
/****************************************************************************
* Private Data
@ -113,6 +115,7 @@ static void start_rt_timer(FAR struct rt_timer_s *timer,
/* Calculate the timer's alarm value */
ESP32C3_TIM_GETCTR(tim, &counter);
counter = CYCLES_TO_USEC(counter);
timer->timeout = timeout;
timer->alarm = timer->timeout + counter;
@ -156,7 +159,7 @@ static void start_rt_timer(FAR struct rt_timer_s *timer,
{
/* Reset the hardware timer alarm */
ESP32C3_TIM_SETALRVL(tim, timer->alarm);
ESP32C3_TIM_SETALRVL(tim, USEC_TO_CYCLES(timer->alarm));
ESP32C3_TIM_SETALRM(tim, true);
}
}
@ -228,7 +231,7 @@ static void stop_rt_timer(FAR struct rt_timer_s *timer)
list);
alarm = next_timer->alarm;
ESP32C3_TIM_SETALRVL(tim, alarm);
ESP32C3_TIM_SETALRVL(tim, USEC_TO_CYCLES(alarm));
ESP32C3_TIM_SETALRM(tim, true);
}
}
@ -420,6 +423,7 @@ static int rt_timer_isr(int irq, void *context, void *arg)
timer = container_of(s_runlist.next, struct rt_timer_s, list);
ESP32C3_TIM_GETCTR(tim, &counter);
counter = CYCLES_TO_USEC(counter);
if (timer->alarm <= counter)
{
/* Remove the first timer from the running list and add it to
@ -443,7 +447,7 @@ static int rt_timer_isr(int irq, void *context, void *arg)
timer = container_of(s_runlist.next, struct rt_timer_s, list);
alarm = timer->alarm;
ESP32C3_TIM_SETALRVL(tim, alarm);
ESP32C3_TIM_SETALRVL(tim, USEC_TO_CYCLES(alarm));
}
}
@ -577,7 +581,7 @@ void rt_timer_delete(FAR struct rt_timer_s *timer)
* Name: rt_timer_time_us
*
* Description:
* Get time of the RT timer in microseconds.
* Get current counter value of the RT timer in microseconds.
*
* Input Parameters:
* None
@ -593,6 +597,7 @@ uint64_t IRAM_ATTR rt_timer_time_us(void)
struct esp32c3_tim_dev_s *tim = s_esp32c3_tim_dev;
ESP32C3_TIM_GETCTR(tim, &counter);
counter = CYCLES_TO_USEC(counter);
return counter;
}
@ -601,7 +606,7 @@ uint64_t IRAM_ATTR rt_timer_time_us(void)
* Name: rt_timer_get_alarm
*
* Description:
* Get the timestamp when the next timeout is expected to occur.
* Get the remaining time to the next timeout.
*
* Input Parameters:
* None
@ -621,7 +626,9 @@ uint64_t IRAM_ATTR rt_timer_get_alarm(void)
flags = enter_critical_section();
ESP32C3_TIM_GETCTR(tim, &counter);
counter = CYCLES_TO_USEC(counter);
ESP32C3_TIM_GETALRVL(tim, &alarm_value);
alarm_value = CYCLES_TO_USEC(alarm_value);
if (alarm_value <= counter)
{
@ -659,8 +666,9 @@ void IRAM_ATTR rt_timer_calibration(uint64_t time_us)
flags = enter_critical_section();
ESP32C3_TIM_GETCTR(tim, &counter);
counter = CYCLES_TO_USEC(counter);
counter += time_us;
ESP32C3_TIM_SETCTR(tim, counter);
ESP32C3_TIM_SETCTR(tim, USEC_TO_CYCLES(counter));
ESP32C3_TIM_RLD_NOW(tim);
leave_critical_section(flags);
}
@ -715,19 +723,18 @@ int esp32c3_rt_timer_init(void)
flags = enter_critical_section();
/* ESP32-C3 hardware timer configuration:
* - 1 counter = 1us
* - Counter increase mode
* - Non-reload mode
* 1 count = 1/16 us
* Clear the counter.
* Set the ISR.
* Enable timeout interrupt.
* Start the counter.
* NOTE: No interrupt will be triggered
* until ESP32C3_TIM_SETALRM is set.
*/
ESP32C3_TIM_SETPRE(tim, ESP32C3_TIMER_PRESCALER);
ESP32C3_TIM_SETMODE(tim, ESP32C3_TIM_MODE_UP);
ESP32C3_TIM_SETARLD(tim, false);
ESP32C3_TIM_CLEAR(tim);
ESP32C3_TIM_SETISR(tim, rt_timer_isr, NULL);
ESP32C3_TIM_ENABLEINT(tim);
ESP32C3_TIM_START(tim);
leave_critical_section(flags);
@ -756,6 +763,8 @@ void esp32c3_rt_timer_deinit(void)
flags = enter_critical_section();
ESP32C3_TIM_STOP(s_esp32c3_tim_dev);
ESP32C3_TIM_DISABLEINT(s_esp32c3_tim_dev);
ESP32C3_TIM_SETISR(s_esp32c3_tim_dev, NULL, NULL);
esp32c3_tim_deinit(s_esp32c3_tim_dev);
s_esp32c3_tim_dev = NULL;

307
arch/risc-v/src/esp32c3/esp32c3_tim.c
View file

@ -36,6 +36,8 @@
#include "esp32c3_tim.h"
#include "esp32c3_irq.h"
#include "esp32c3_gpio.h"
#include "hardware/esp32c3_system.h"
#include "hardware/esp32c3_systimer.h"
/****************************************************************************
* Private Types
@ -114,6 +116,28 @@ struct esp32c3_tim_ops_s esp32c3_tim_ops =
.checkint = esp32c3_tim_checkint
};
struct esp32c3_tim_ops_s esp32c3_systim_ops =
{
.start = esp32c3_tim_start,
.stop = esp32c3_tim_stop,
.clear = esp32c3_tim_clear,
.setmode = NULL,
.getcounter = esp32c3_tim_getcounter,
.setclksrc = NULL,
.setpre = NULL,
.setcounter = esp32c3_tim_setcounter,
.reloadnow = esp32c3_tim_reload_now,
.getalarmvalue = esp32c3_tim_getalarmvalue,
.setalarmvalue = esp32c3_tim_setalarmvalue,
.setalarm = esp32c3_tim_setalarm,
.setautoreload = NULL,
.setisr = esp32c3_tim_setisr,
.enableint = esp32c3_tim_enableint,
.disableint = esp32c3_tim_disableint,
.ackint = esp32c3_tim_ackint,
.checkint = esp32c3_tim_checkint
};
#ifdef CONFIG_ESP32C3_TIMER0
/* TIMER0 */
@ -142,6 +166,20 @@ struct esp32c3_tim_priv_s g_esp32c3_tim1_priv =
};
#endif
#ifdef CONFIG_ESP32C3_RT_TIMER
/* SYSTIMER */
struct esp32c3_tim_priv_s g_esp32c3_tim2_priv =
{
.ops = &esp32c3_systim_ops,
.id = ESP32C3_SYSTIM,
.periph = ESP32C3_PERIPH_SYSTIMER_T2 , /* Peripheral ID */
.irq = ESP32C3_IRQ_SYSTIMER_T2, /* Interrupt ID */
.cpuint = -ENOMEM, /* CPU interrupt assigned to this timer */
.inuse = false,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -162,7 +200,17 @@ static void esp32c3_tim_start(FAR struct esp32c3_tim_dev_s *dev)
struct esp32c3_tim_priv_s *priv;
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
modifyreg32(TIMG_T0CONFIG_REG(priv->id), TIMG_T0_EN_M, TIMG_T0_EN_M);
if (priv->id == ESP32C3_SYSTIM)
{
/* Start counter 1 */
modifyreg32(SYS_TIMER_SYSTIMER_CONF_REG, 0,
SYS_TIMER_TIMER_UNIT1_WORK_EN_M);
}
else
{
modifyreg32(TIMG_T0CONFIG_REG(priv->id), TIMG_T0_EN_M, TIMG_T0_EN_M);
}
}
/****************************************************************************
@ -181,7 +229,17 @@ static void esp32c3_tim_stop(FAR struct esp32c3_tim_dev_s *dev)
struct esp32c3_tim_priv_s *priv;
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
modifyreg32(TIMG_T0CONFIG_REG(priv->id), TIMG_T0_EN_M, 0);
if (priv->id == ESP32C3_SYSTIM)
{
/* Stop counter 1 */
modifyreg32(SYS_TIMER_SYSTIMER_CONF_REG,
SYS_TIMER_TIMER_UNIT1_WORK_EN_M, 0);
}
else
{
modifyreg32(TIMG_T0CONFIG_REG(priv->id), TIMG_T0_EN_M, 0);
}
}
/****************************************************************************
@ -304,22 +362,49 @@ static void esp32c3_tim_getcounter(FAR struct esp32c3_tim_dev_s *dev,
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
*value = 0;
if (priv->id == ESP32C3_SYSTIM)
{
/* Trigger an update event */
/* Dummy value (0 or 1) to latch the counter value to read it */
modifyreg32(SYS_TIMER_SYSTIMER_UNIT1_OP_REG, 0,
SYS_TIMER_TIMER_UNIT1_UPDATE_M);
putreg32(BIT(0), TIMG_T0UPDATE_REG(priv->id));
/* Wait until the value is valid */
/* Read value */
while ((getreg32(SYS_TIMER_SYSTIMER_UNIT1_OP_REG) &
SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M) !=
SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M);
value_32 = getreg32(TIMG_T0HI_REG(priv->id)); /* High 32 bits */
/* Finally read the counter 1 value */
/* Discard the top 10 bits */
value_32 = getreg32(SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG);
value_32 &= LOW_22_MASK;
*value |= (uint64_t)value_32;
*value <<= SHIFT_32;
value_32 = getreg32(TIMG_T0LO_REG(priv->id)); /* Low 32 bits */
*value |= (uint64_t)value_32;
/* Discard the top 12 bits */
value_32 &= LOW_20_MASK;
*value |= (uint64_t)value_32;
*value <<= SHIFT_32;
value_32 = getreg32(SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG);
*value |= (uint64_t)value_32;
}
else
{
/* Dummy value (0 or 1) to latch the counter value to read it */
putreg32(BIT(0), TIMG_T0UPDATE_REG(priv->id));
/* Read value */
value_32 = getreg32(TIMG_T0HI_REG(priv->id)); /* High 32 bits */
/* Discard the top 10 bits */
value_32 &= LOW_22_MASK;
*value |= (uint64_t)value_32;
*value <<= SHIFT_32;
value_32 = getreg32(TIMG_T0LO_REG(priv->id)); /* Low 32 bits */
*value |= (uint64_t)value_32;
}
}
/****************************************************************************
@ -342,18 +427,34 @@ static void esp32c3_tim_setcounter(FAR struct esp32c3_tim_dev_s *dev,
uint64_t value)
{
uint64_t low_64 = value & LOW_32_MASK;
/* Get only the low 22 bits. */
uint64_t high_64 = (value >> SHIFT_32) & LOW_22_MASK;
uint64_t high_64;
struct esp32c3_tim_priv_s *priv;
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
/* Set the counter value */
if (priv->id == ESP32C3_SYSTIM)
{
high_64 = (value >> SHIFT_32) & LOW_20_MASK;
putreg32((uint32_t)low_64, TIMG_T0LOADLO_REG(priv->id));
putreg32((uint32_t)high_64, TIMG_T0LOADHI_REG(priv->id));
/* Set the counter 1 value */
putreg32((uint32_t)low_64, SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG);
putreg32((uint32_t)high_64, SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG);
/* Synchronize */
putreg32(SYS_TIMER_TIMER_UNIT1_LOAD_M,
SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG);
}
else
{
high_64 = (value >> SHIFT_32) & LOW_22_MASK;
/* Set the counter value */
putreg32((uint32_t)low_64, TIMG_T0LOADLO_REG(priv->id));
putreg32((uint32_t)high_64, TIMG_T0LOADHI_REG(priv->id));
}
}
/****************************************************************************
@ -374,9 +475,19 @@ static void esp32c3_tim_reload_now(FAR struct esp32c3_tim_dev_s *dev)
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
/* Dummy value to trigger reloading */
if (priv->id == ESP32C3_SYSTIM)
{
/* Load immediately */
putreg32(BIT(0), TIMG_T0LOAD_REG(priv->id));
putreg32(SYS_TIMER_TIMER_UNIT1_LOAD_M,
SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG);
}
else
{
/* Dummy value to trigger reloading */
putreg32(BIT(0), TIMG_T0LOAD_REG(priv->id));
}
}
/****************************************************************************
@ -396,22 +507,37 @@ static void esp32c3_tim_getalarmvalue(FAR struct esp32c3_tim_dev_s *dev,
{
uint32_t value_32;
struct esp32c3_tim_priv_s *priv;
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
*value = 0;
if (priv->id == ESP32C3_SYSTIM)
{
/* Read value */
/* Read value */
value_32 = getreg32(SYS_TIMER_SYSTIMER_TARGET2_HI_REG); /* High 32 bits */
value_32 = getreg32(TIMG_T0ALARMHI_REG(priv->id)); /* High 32 bits */
/* Get only the 20 low bits. */
/* Get only the 22 low bits. */
value_32 &= LOW_20_MASK;
*value |= (uint64_t)value_32;
*value <<= SHIFT_32;
value_32 = getreg32(SYS_TIMER_SYSTIMER_TARGET2_LO_REG); /* Low 32 bits */
*value |= (uint64_t)value_32;
}
else
{
/* Read value */
value_32 &= LOW_22_MASK;
*value |= (uint64_t)value_32;
*value <<= SHIFT_32;
value_32 = getreg32(TIMG_T0ALARMLO_REG(priv->id)); /* Low 32 bits */
*value |= (uint64_t)value_32;
value_32 = getreg32(TIMG_T0ALARMHI_REG(priv->id)); /* High 32 bits */
/* Get only the 22 low bits. */
value_32 &= LOW_22_MASK;
*value |= (uint64_t)value_32;
*value <<= SHIFT_32;
value_32 = getreg32(TIMG_T0ALARMLO_REG(priv->id)); /* Low 32 bits */
*value |= (uint64_t)value_32;
}
}
/****************************************************************************
@ -428,18 +554,37 @@ static void esp32c3_tim_getalarmvalue(FAR struct esp32c3_tim_dev_s *dev,
****************************************************************************/
static void esp32c3_tim_setalarmvalue(FAR struct esp32c3_tim_dev_s *dev,
uint64_t value)
uint64_t value)
{
struct esp32c3_tim_priv_s *priv;
uint64_t low_64 = value & LOW_32_MASK;
uint64_t high_64 = (value >> SHIFT_32) & LOW_22_MASK;
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
/* Set an alarm value */
if (priv->id == ESP32C3_SYSTIM)
{
uint64_t low_64 = value & LOW_32_MASK;
uint64_t high_64 = (value >> SHIFT_32) & LOW_20_MASK;
putreg32((uint32_t)low_64, TIMG_T0ALARMLO_REG(priv->id));
putreg32((uint32_t)high_64, TIMG_T0ALARMHI_REG(priv->id));
/* Set an alarm value */
putreg32((uint32_t)low_64, SYS_TIMER_SYSTIMER_TARGET2_LO_REG);
putreg32((uint32_t)high_64, SYS_TIMER_SYSTIMER_TARGET2_HI_REG);
/* Synchronize */
putreg32(SYS_TIMER_TIMER_COMP2_LOAD_M,
SYS_TIMER_SYSTIMER_COMP2_LOAD_REG);
}
else
{
uint64_t low_64 = value & LOW_32_MASK;
uint64_t high_64 = (value >> SHIFT_32) & LOW_22_MASK;
/* Set an alarm value */
putreg32((uint32_t)low_64, TIMG_T0ALARMLO_REG(priv->id));
putreg32((uint32_t)high_64, TIMG_T0ALARMHI_REG(priv->id));
}
}
/****************************************************************************
@ -462,13 +607,33 @@ static void esp32c3_tim_setalarm(FAR struct esp32c3_tim_dev_s *dev,
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
if (enable)
if (priv->id == ESP32C3_SYSTIM)
{
modifyreg32(TIMG_T0CONFIG_REG(priv->id), 0, TIMG_T0_ALARM_EN_M);
if (enable)
{
/* Enable Comparator 2 */
modifyreg32(SYS_TIMER_SYSTIMER_CONF_REG, 0,
SYS_TIMER_TARGET2_WORK_EN_M);
}
else
{
/* Disable Comparator 2 */
modifyreg32(SYS_TIMER_SYSTIMER_CONF_REG,
SYS_TIMER_TARGET2_WORK_EN_M, 0);
}
}
else
{
modifyreg32(TIMG_T0CONFIG_REG(priv->id), TIMG_T0_ALARM_EN_M, 0);
if (enable)
{
modifyreg32(TIMG_T0CONFIG_REG(priv->id), 0, TIMG_T0_ALARM_EN_M);
}
else
{
modifyreg32(TIMG_T0CONFIG_REG(priv->id), TIMG_T0_ALARM_EN_M, 0);
}
}
}
@ -617,7 +782,15 @@ static void esp32c3_tim_enableint(FAR struct esp32c3_tim_dev_s *dev)
struct esp32c3_tim_priv_s *priv;
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
modifyreg32(TIMG_INT_ENA_TIMERS_REG(priv->id), 0, TIMG_T0_INT_ENA_M);
if (priv->id == ESP32C3_SYSTIM)
{
modifyreg32(SYS_TIMER_SYSTIMER_INT_ENA_REG, 0,
SYS_TIMER_TARGET2_INT_ENA_M);
}
else
{
modifyreg32(TIMG_INT_ENA_TIMERS_REG(priv->id), 0, TIMG_T0_INT_ENA_M);
}
}
/****************************************************************************
@ -636,7 +809,15 @@ static void esp32c3_tim_disableint(FAR struct esp32c3_tim_dev_s *dev)
struct esp32c3_tim_priv_s *priv;
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
modifyreg32(TIMG_INT_ENA_TIMERS_REG(priv->id), TIMG_T0_INT_ENA_M, 0);
if (priv->id == ESP32C3_SYSTIM)
{
modifyreg32(SYS_TIMER_SYSTIMER_INT_ENA_REG,
SYS_TIMER_TARGET2_INT_ENA_M, 0);
}
else
{
modifyreg32(TIMG_INT_ENA_TIMERS_REG(priv->id), TIMG_T0_INT_ENA_M, 0);
}
}
/****************************************************************************
@ -655,7 +836,15 @@ static void esp32c3_tim_ackint(FAR struct esp32c3_tim_dev_s *dev)
struct esp32c3_tim_priv_s *priv;
DEBUGASSERT(dev);
priv = (FAR struct esp32c3_tim_priv_s *)dev;
modifyreg32(TIMG_INT_CLR_TIMERS_REG(priv->id), 0, TIMG_T0_INT_CLR_M);
if (priv->id == ESP32C3_SYSTIM)
{
modifyreg32(SYS_TIMER_SYSTIMER_INT_CLR_REG, 0,
SYS_TIMER_TARGET2_INT_CLR_M);
}
else
{
modifyreg32(TIMG_INT_CLR_TIMERS_REG(priv->id), 0, TIMG_T0_INT_CLR_M);
}
}
/****************************************************************************
@ -676,11 +865,23 @@ static int esp32c3_tim_checkint(FAR struct esp32c3_tim_dev_s *dev)
{
struct esp32c3_tim_priv_s *priv = (struct esp32c3_tim_priv_s *)dev;
uint32_t reg_value;
int ret;
DEBUGASSERT(dev != NULL);
if (priv->id == ESP32C3_SYSTIM)
{
reg_value = getreg32(SYS_TIMER_SYSTIMER_INT_ST_REG);
ret = (reg_value & SYS_TIMER_TARGET2_INT_ST_M) >>
SYS_TIMER_TARGET2_INT_ST_S;
}
else
{
reg_value = getreg32(TIMG_INT_ST_TIMERS_REG(priv->id));
ret = (reg_value & TIMG_T0_INT_ST_M) >>
TIMG_T0_INT_ST_S;
}
reg_value = getreg32(TIMG_INT_ST_TIMERS_REG(priv->id));
return ((reg_value & TIMG_T0_INT_ST_V) >> TIMG_T0_INT_ST_S);
return ret;
}
/****************************************************************************
@ -728,6 +929,24 @@ FAR struct esp32c3_tim_dev_s *esp32c3_tim_init(int timer)
}
#endif
#ifdef CONFIG_ESP32C3_RT_TIMER
case 2:
{
tim = &g_esp32c3_tim2_priv;
/* Clock and reset of systimer peripheral is already performed
* either in esp32c3_timerisr.c or in esp32c3_tickless.c.
* Set comparator 2 to use counter 1 and set the mode
* to oneshot mode, i.e., disable periodic mode.
*/
modifyreg32(SYS_TIMER_SYSTIMER_TARGET2_CONF_REG,
SYS_TIMER_TARGET2_PERIOD_MODE_M,
SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M);
break;
}
#endif
default:
{
tmrerr("ERROR: unsupported TIMER %d\n", timer);

1
arch/risc-v/src/esp32c3/esp32c3_tim.h
View file

@ -65,6 +65,7 @@ enum esp32c3_tim_inst_e
{
ESP32C3_TIMER0 = 0, /* Timer 0 from Timer Group 0 */
ESP32C3_TIMER1, /* Timer 0 from Timer Group 1 */
ESP32C3_SYSTIM, /* SYSTIMER 1 */
};
/* Timer mode */

2
arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h
View file

@ -73,6 +73,8 @@
#define LOW_32_MASK 0xffffffff
#define LOW_22_MASK 0x003fffff
#define LOW_20_MASK 0x000fffff
#define LOW_26_MASK 0x03ffffff
#define SHIFT_32 32
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)