Merge remote-tracking branch 'origin/master' into bas24
This commit is contained in:
Gregory Nutt
commit
cf8304f47f
17 changed files with 436 additions and 117 deletions
67
README.txt
67
README.txt
|
|
@ -63,6 +63,11 @@ Installing Cygwin
|
|||
of the Cygwin utilities that you will need to build NuttX. The
|
||||
build will fail in numerous places because of missing packages.
|
||||
|
||||
NOTE: You don't really have to install EVERYTHING but I cannot
|
||||
answer the question "Then what should I install?" I don't know
|
||||
the answer to that and so will continue to recommend installing
|
||||
EVERYTHING.
|
||||
|
||||
After installing Cygwin, you will get lots of links for installed
|
||||
tools and shells. I use the RXVT native shell. It is fast and reliable
|
||||
and does not require you to run the Cygwin X server (which is neither
|
||||
|
|
@ -70,6 +75,10 @@ Installing Cygwin
|
|||
instructions assume that you are at a bash command line prompt in
|
||||
either Linux or in Cygwin shell.
|
||||
|
||||
UPDATE: The last time I installed EVERTHING, the download was
|
||||
about 5GiB. The server I selected was also very slow so it took
|
||||
over a day to do the whole install!
|
||||
|
||||
Download and Unpack
|
||||
-------------------
|
||||
|
||||
|
|
@ -110,7 +119,7 @@ Semi-Optional apps/ Package
|
|||
nuttx/ apps/
|
||||
|
||||
This is important because the NuttX build will expect to find the
|
||||
apps directory in that (default) location. )That default location
|
||||
apps directory in that (default) location. That default location
|
||||
can be changed by editing your NuttX configuration file, but that
|
||||
is another story).
|
||||
|
||||
|
|
@ -134,10 +143,20 @@ Installation Directories with Spaces in the Path
|
|||
Downloading from Repositories
|
||||
-----------------------------
|
||||
|
||||
The current NuttX du jour is available in from a GIT repository. Download
|
||||
instructions are available here:
|
||||
Cloning the Repository
|
||||
|
||||
https://sourceforge.net/p/nuttx/git
|
||||
The current NuttX du jour is available in from a GIT repository. Cloning
|
||||
instructions are available here:
|
||||
|
||||
https://sourceforge.net/p/nuttx/git
|
||||
|
||||
Cloning NuttX Inside Cygwin
|
||||
|
||||
If you are cloning the NuttX repository, it is recommended to avoid
|
||||
automatic end of lines conversions by git. These conversions may break
|
||||
some scripts like configure.sh. Before cloning, do the following:
|
||||
|
||||
git config --global core.autocrlf false
|
||||
|
||||
Notes about Header Files
|
||||
------------------------
|
||||
|
|
@ -528,7 +547,7 @@ SHELLS
|
|||
|
||||
In this case, bash is probably available and the #!/bin/bash at the
|
||||
beginning of the file should do the job. If any scripts with #!/bin/sh
|
||||
fail, try changing that ti #!/bin/bash and let me know about the change.
|
||||
fail, try changing that to #!/bin/bash and let me know about the change.
|
||||
|
||||
2. FreeBSD with the Bourne Shell and no bash shell.
|
||||
|
||||
|
|
@ -848,7 +867,7 @@ General Pre-built Toolchain Issues
|
|||
There may be incompatibilities with header files, libraries, and compiler
|
||||
built-in functions at detailed below. For the most part, these issues
|
||||
are handled in the existing make logic. But if you are breaking new ground,
|
||||
then you may incounter these:
|
||||
then you may encounter these:
|
||||
|
||||
4. Header Files. Most pre-built toolchains will build with a foreign C
|
||||
library (usually newlib, but maybe uClibc or glibc if you are using a
|
||||
|
|
@ -891,6 +910,42 @@ General Pre-built Toolchain Issues
|
|||
your toolchain since they will be using different versions of
|
||||
binutils and possibly different ABIs.
|
||||
|
||||
Building Original Linux Boards in Cygwin
|
||||
|
||||
Some default board configurations are set to build under Linux and others
|
||||
to build under Windows with Cygwin. Various default toolchains may also
|
||||
be used in each configuration. It is possible to change the default
|
||||
setup. Here, for example, is what you must do in order to compile a
|
||||
default Linux configuration in the Cygwin environment using the
|
||||
CodeSourceery for Windows toolchain. After instantiating a "canned"
|
||||
NuttX configuration, run the target 'menuconfig' and set the following
|
||||
items:
|
||||
|
||||
Build Setup->Build Host Platform->Windows
|
||||
Build Setup->Windows Build Environment->Cygwin
|
||||
System Type->Toolchain Selection->CodeSourcery GNU Toolchain under Windows
|
||||
|
||||
In Windows 7 it may be required to open the Cygwin shell as Administrator
|
||||
("Run As" option, right button) you find errors like "Permission denied".
|
||||
|
||||
Recovering from Bad Configurations
|
||||
|
||||
Many people make the mistake of configuring NuttX with the "canned"
|
||||
configuration and then just typing 'make' with disastrous consequences;
|
||||
the build may fail with mysterious, uninterpretable, and irrecoverable
|
||||
build errors. If, for example, you do this with an unmodified Linux
|
||||
configuration in a Windows/Cgwin environment, you will corrupt the
|
||||
build environment. The environment will be corrupted because of POSIX vs
|
||||
Windows path issues and with issues related to symbolic links. If you
|
||||
make the mistake of doing this, the easiest way to recover is to just
|
||||
start over: Do 'make distclean' to remove every trace of the corrupted
|
||||
configuration, reconfigure from scratch, and make certain that the set
|
||||
the configuration correctly for your platform before attempting to make
|
||||
again.
|
||||
|
||||
Just fixing the configuration file after you have instantiated the bad
|
||||
configuration with 'make' is not enough.
|
||||
|
||||
DOCUMENTATION
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@
|
|||
#define EFM32_USART0_BASE 0x4000c000 /* USART0 base address */
|
||||
#define EFM32_USART1_BASE 0x4000c400 /* USART1 base address */
|
||||
#define EFM32_USART2_BASE 0x4000c800 /* USART2 base address */
|
||||
#define EFM32_UART0_BASE 0x4000e00 /* UART0 base address */
|
||||
#define EFM32_UART0_BASE 0x4000e000 /* UART0 base address */
|
||||
#define EFM32_TIMER0_BASE 0x40010000 /* TIMER0 base address */
|
||||
#define EFM32_TIMER1_BASE 0x40010400 /* TIMER1 base address */
|
||||
#define EFM32_TIMER2_BASE 0x40010800 /* TIMER2 base address */
|
||||
|
|
|
|||
|
|
@ -166,7 +166,7 @@ static void efm32_enable_lfxo(void)
|
|||
{
|
||||
/* Enable the LFXO */
|
||||
|
||||
putreg32(CMU_OSCENCMD_LFRCOEN, EFM32_CMU_OSCENCMD);
|
||||
putreg32(CMU_OSCENCMD_LFXOEN, EFM32_CMU_OSCENCMD);
|
||||
efm32_statuswait(CMU_STATUS_LFXORDY);
|
||||
}
|
||||
|
||||
|
|
@ -610,6 +610,7 @@ static inline uint32_t efm32_lfaclk_config(uint32_t lfaclksel, bool ulfrco,
|
|||
case CMU_LFCLKSEL_LFA_LFRCO:
|
||||
{
|
||||
efm32_enable_lfrco();
|
||||
lfaclk = BOARD_LFRCO_FREQUENCY;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -266,7 +266,7 @@ static inline void efm32_setmode(uintptr_t base, uint8_t pin, uint8_t mode)
|
|||
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~((uint32_t)15 << shift);
|
||||
regval |= ~((uint32_t)mode << shift);
|
||||
regval |= (uint32_t)mode << shift;
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -51,6 +51,8 @@
|
|||
#include "chip/efm32_usart.h"
|
||||
#include "chip/efm32_leuart.h"
|
||||
#include "chip/efm32_cmu.h"
|
||||
|
||||
#include "efm32_gpio.h"
|
||||
#include "efm32_lowputc.h"
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -204,17 +206,16 @@ static void efm32_uart_setbaud(uintptr_t base, uint32_t baud)
|
|||
clkdiv = 0;
|
||||
}
|
||||
|
||||
DEBUGASSERT(clkdiv <= _USART_CLKDIV_MASK);
|
||||
/* Set up the selected oversampling and baud divisor */
|
||||
|
||||
/* Set up the selected oversampling and baud */
|
||||
|
||||
regval = getreg32(base + EFM32_USART_CTRL_OFFSET);
|
||||
regval &= ~_USART_CTRL_OVS_MASK;
|
||||
regval |= ovs;
|
||||
regval = getreg32(base + EFM32_USART_CTRL_OFFSET);
|
||||
regval &= ~_USART_CTRL_OVS_MASK;
|
||||
regval |= ovs;
|
||||
putreg32(regval, base + EFM32_USART_CTRL_OFFSET);
|
||||
|
||||
putreg32((uint32_t)clkdiv & _USART_CLKDIV_DIV_MASK,
|
||||
base + EFM32_USART_CLKDIV_OFFSET);
|
||||
regval = (uint32_t)clkdiv << _USART_CLKDIV_DIV_SHIFT;
|
||||
DEBUGASSERT((regval & _USART_CLKDIV_MASK) == regval);
|
||||
putreg32(regval, base + EFM32_USART_CLKDIV_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -342,9 +343,71 @@ void efm32_lowsetup(void)
|
|||
putreg32(regval, EFM32_CMU_LFBCLKEN0);
|
||||
#endif /* HAVE_LEUART_DEVICE */
|
||||
|
||||
/* Set location in the ROUTE register */
|
||||
#if defined(HAVE_UART_DEVICE) || defined(HAVE_SPI_DEVICE)
|
||||
/* Enable output on U[S]ART output pins */
|
||||
|
||||
#ifdef CONFIG_EFM32_USART0
|
||||
efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_USART0_RX_GPIO);
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_USART0_TX_GPIO);
|
||||
#ifdef CONFIG_EFM32_USART0_ISSPI
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_USART0_CLK_GPIO);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EFM32_USART1
|
||||
efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_USART1_RX_GPIO);
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_USART1_TX_GPIO);
|
||||
#ifdef CONFIG_EFM32_USART1_ISSPI
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_USART1_CLK_GPIO);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EFM32_USART2
|
||||
efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_USART2_RX_GPIO);
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_USART2_TX_GPIO);
|
||||
#ifdef CONFIG_EFM32_USART2_ISSPI
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_USART2_CLK_GPIO);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EFM32_UART0
|
||||
efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_UART0_RX_GPIO);
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_UART0_TX_GPIO);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EFM32_UART1
|
||||
efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_UART1_RX_GPIO);
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_UART1_TX_GPIO);
|
||||
#endif
|
||||
#endif /* HAVE_UART_DEVICE */
|
||||
|
||||
#ifdef HAVE_LEUART_DEVICE
|
||||
/* Enable output on LEUART output pins */
|
||||
|
||||
#ifdef CONFIG_EFM32_LEUART0
|
||||
efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_LEUART0_RX_GPIO);
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_LEUART0_TX_GPIO);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EFM32_LEUART1
|
||||
efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_LEUART1_RX_GPIO);
|
||||
efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR |
|
||||
GPIO_DRIVE_STANDARD | BOARD_LEUART1_TX_GPIO);
|
||||
#endif
|
||||
#endif /* HAVE_LEUART_DEVICE */
|
||||
|
||||
#if defined(HAVE_UART_DEVICE) || defined(HAVE_SPI_DEVICE)
|
||||
/* Set location in the U[S]ART ROUTE registers */
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
#ifdef CONFIG_EFM32_USART0
|
||||
regval = (USART_ROUTE_RXPEN | USART_ROUTE_TXPEN |
|
||||
(BOARD_USART0_ROUTE_LOCATION << _USART_ROUTE_LOCATION_SHIFT));
|
||||
|
|
@ -386,13 +449,15 @@ void efm32_lowsetup(void)
|
|||
#endif /* HAVE_UART_DEVICE */
|
||||
|
||||
#ifdef HAVE_LEUART_DEVICE
|
||||
#ifdef CONFIG_EFM32_UART0
|
||||
/* Set location in the LEUART ROUTE registers */
|
||||
|
||||
#ifdef CONFIG_EFM32_LEUART0
|
||||
regval = (LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN |
|
||||
(BOARD_LEUART0_ROUTE_LOCATION << _LEUART_ROUTE_LOCATION_SHIFT));
|
||||
putreg32(regval, EFM32_LEUART0_ROUTE);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EFM32_UART1
|
||||
#ifdef CONFIG_EFM32_LEUART1
|
||||
regval = (LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN |
|
||||
(BOARD_LEUART1_ROUTE_LOCATION << _LEUART_ROUTE_LOCATION_SHIFT));
|
||||
putreg32(regval, EFM32_LEUART1_ROUTE);
|
||||
|
|
|
|||
|
|
@ -1546,7 +1546,7 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
|
|||
* 1. USART GPIO pins were configured in efm32_lowsetup(). Chip select
|
||||
* pins must be configured by board specific logic before
|
||||
* efm32_spi_initialize() is called.
|
||||
* 2. Clocking for the USART as also enabled in up_lowsetup();
|
||||
* 2. Clocking for the USART as also enabled in efm32_lowsetup();
|
||||
*/
|
||||
|
||||
/* Set bits for synchronous mode */
|
||||
|
|
|
|||
|
|
@ -51,15 +51,23 @@
|
|||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "efm32_config.h"
|
||||
#include "efm32_lowputc.h"
|
||||
#include "efm32_clockconfig.h"
|
||||
#include "efm32_start.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
# include "nvic.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
static inline void efm32_fpuconfig(void);
|
||||
#endif
|
||||
#ifdef CONFIG_DEBUG_STACK
|
||||
static void go_os_start(void *pv, unsigned int nbytes)
|
||||
__attribute__ ((naked,no_instrument_function,noreturn));
|
||||
|
|
@ -81,7 +89,7 @@ static void go_os_start(void *pv, unsigned int nbytes)
|
|||
# if defined(CONFIG_ARMV7M_ITMSYSLOG)
|
||||
# define showprogress(c) (void)syslog_putc(c)
|
||||
# elif defined(HAVE_UART_CONSOLE) || defined(HAVE_LEUART_CONSOLE)
|
||||
# define showprogress(c) up_lowputc(c)
|
||||
# define showprogress(c) efm32_lowputc(c)
|
||||
# else
|
||||
# define showprogress(c)
|
||||
# endif
|
||||
|
|
@ -89,6 +97,96 @@ static void go_os_start(void *pv, unsigned int nbytes)
|
|||
# define showprogress(c)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: efm32_fpuconfig
|
||||
*
|
||||
* Description:
|
||||
* Configure the FPU. Relative bit settings:
|
||||
*
|
||||
* CPACR: Enables access to CP10 and CP11
|
||||
* CONTROL.FPCA: Determines whether the FP extension is active in the
|
||||
* current context:
|
||||
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
|
||||
* processor sets this bit to 1 on successful completion of any FP
|
||||
* instruction.
|
||||
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
|
||||
* done, the processor reserves space on the stack for the FP state,
|
||||
* but does not save that state information to the stack.
|
||||
*
|
||||
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
|
||||
* - the CPACR permits access to CP10 and CP11, that give access to the FP
|
||||
* extension, or
|
||||
* - the CONTROL.FPCA bit is set to 1
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
#ifdef CONFIG_ARMV7M_CMNVECTOR
|
||||
|
||||
static inline void efm32_fpuconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set CONTROL.FPCA so that we always get the extended context frame
|
||||
* with the volatile FP registers stacked above the basic context.
|
||||
*/
|
||||
|
||||
regval = getcontrol();
|
||||
regval |= (1 << 2);
|
||||
setcontrol(regval);
|
||||
|
||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
||||
* are going to turn on CONTROL.FPCA for all contexts.
|
||||
*/
|
||||
|
||||
regval = getreg32(NVIC_FPCCR);
|
||||
regval &= ~((1 << 31) | (1 << 30));
|
||||
putreg32(regval, NVIC_FPCCR);
|
||||
|
||||
/* Enable full access to CP10 and CP11 */
|
||||
|
||||
regval = getreg32(NVIC_CPACR);
|
||||
regval |= ((3 << (2*10)) | (3 << (2*11)));
|
||||
putreg32(regval, NVIC_CPACR);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void efm32_fpuconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Clear CONTROL.FPCA so that we do not get the extended context frame
|
||||
* with the volatile FP registers stacked in the saved context.
|
||||
*/
|
||||
|
||||
regval = getcontrol();
|
||||
regval &= ~(1 << 2);
|
||||
setcontrol(regval);
|
||||
|
||||
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
|
||||
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
|
||||
* are going to keep CONTROL.FPCA off for all contexts.
|
||||
*/
|
||||
|
||||
regval = getreg32(NVIC_FPCCR);
|
||||
regval &= ~((1 << 31) | (1 << 30));
|
||||
putreg32(regval, NVIC_FPCCR);
|
||||
|
||||
/* Enable full access to CP10 and CP11 */
|
||||
|
||||
regval = getreg32(NVIC_CPACR);
|
||||
regval |= ((3 << (2*10)) | (3 << (2*11)));
|
||||
putreg32(regval, NVIC_CPACR);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
# define efm32_fpuconfig()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: go_os_start
|
||||
*
|
||||
|
|
@ -149,6 +247,7 @@ void __start(void)
|
|||
/* Configure the uart so that we can get debug output as soon as possible */
|
||||
|
||||
efm32_clockconfig();
|
||||
efm32_fpuconfig();
|
||||
efm32_lowsetup();
|
||||
showprogress('A');
|
||||
|
||||
|
|
@ -179,7 +278,6 @@ void __start(void)
|
|||
/* Perform early serial initialization */
|
||||
|
||||
up_earlyserialinit();
|
||||
|
||||
showprogress('D');
|
||||
|
||||
/* For the case of the separate user-/kernel-space build, perform whatever
|
||||
|
|
@ -193,6 +291,11 @@ void __start(void)
|
|||
showprogress('E');
|
||||
#endif
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
efm32_boardinitialize();
|
||||
showprogress('F');
|
||||
|
||||
/* Then start NuttX */
|
||||
|
||||
showprogress('\r');
|
||||
|
|
|
|||
|
|
@ -370,11 +370,11 @@
|
|||
#if defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
#define TC_CMR_SBSMPLR_SHIFT (20) /* Bits 20-22: Loading Edge Subsampling Ratio */
|
||||
#define TC_CMR_SBSMPLR_MASK (7 << TC_CMR_SBSMPLR_SHIFT)
|
||||
# define TC_CMR_SBSMPLR_ ONE (0 << TC_CMR_SBSMPLR_SHIFT) /* Load on each selected edge */
|
||||
# define TC_CMR_SBSMPLR_ HALF (1 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 2 selected edges */
|
||||
# define TC_CMR_SBSMPLR_ 4TH (2 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 4 selected edges */
|
||||
# define TC_CMR_SBSMPLR_ 8TH (3 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 8 selected edges */
|
||||
# define TC_CMR_SBSMPLR_ 16TH (4 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 16 selected edges */
|
||||
# define TC_CMR_SBSMPLR_ONE (0 << TC_CMR_SBSMPLR_SHIFT) /* Load on each selected edge */
|
||||
# define TC_CMR_SBSMPLR_HALF (1 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 2 selected edges */
|
||||
# define TC_CMR_SBSMPLR_4TH (2 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 4 selected edges */
|
||||
# define TC_CMR_SBSMPLR_8TH (3 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 8 selected edges */
|
||||
# define TC_CMR_SBSMPLR_16TH (4 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 16 selected edges */
|
||||
#endif
|
||||
|
||||
/* TC Channel Mode Register -- Waveform mode only */
|
||||
|
|
|
|||
|
|
@ -2547,6 +2547,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, enum pm_state_e pmstate)
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if USE_EARLYSERIALINIT
|
||||
void up_earlyserialinit(void)
|
||||
{
|
||||
#ifdef HAVE_UART
|
||||
|
|
@ -2569,6 +2570,7 @@ void up_earlyserialinit(void)
|
|||
#endif
|
||||
#endif /* HAVE UART */
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_serialinit
|
||||
|
|
|
|||
|
|
@ -16,11 +16,20 @@ README
|
|||
• On-board SEGGER J-Link USB emulator
|
||||
• ARM 20 pin JTAG/SWD standard Debug in/out connector
|
||||
|
||||
CONTENTS
|
||||
=======
|
||||
|
||||
• Status
|
||||
• LEDs
|
||||
• Serial Console
|
||||
• Using the J-Link GDB Server
|
||||
• Configurations
|
||||
|
||||
STATUS
|
||||
======
|
||||
|
||||
My board is on order and has not arrived as of this writing. So no debug
|
||||
has yet been done. So the status is code-complete but untested.
|
||||
Testing has just begun. So the status is code-complete but only
|
||||
partially tested.
|
||||
|
||||
LEDs
|
||||
====
|
||||
|
|
@ -45,7 +54,7 @@ LEDs
|
|||
include/board.h and src/efm32_autoleds.c. The LEDs are used to
|
||||
encode OS-related events as follows:
|
||||
|
||||
SYMBOL Meaning LED1* LED2 LED3 LED4
|
||||
SYMBOL Meaning LED0* LED1 LED2 LED3
|
||||
----------------- ----------------------- ------ ----- ----- ------
|
||||
LED_STARTED NuttX has been started ON OFF OFF OFF
|
||||
LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF
|
||||
|
|
@ -57,14 +66,14 @@ LEDs
|
|||
LED_PANIC The system has crashed N/C N/C N/C ON
|
||||
LED_IDLE STM32 is is sleep mode (Optional, not used)
|
||||
|
||||
* If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot
|
||||
* If LED0, LED1, LED2 are statically on, then NuttX probably failed to boot
|
||||
and these LEDs will give you some indication of where the failure was
|
||||
** The normal state is LED3 ON and LED1 faintly glowing. This faint glow
|
||||
** The normal state is LED2 ON and LED3 faintly glowing. This faint glow
|
||||
is because of timer interrupt that result in the LED being illuminated
|
||||
on a small proportion of the time.
|
||||
*** LED2 may also flicker normally if signals are processed.
|
||||
*** LED1 may also flicker normally if signals are processed.
|
||||
|
||||
Serial Console
|
||||
SERIAL CONSOLE
|
||||
==============
|
||||
|
||||
Pin Availability
|
||||
|
|
@ -133,8 +142,58 @@ Serial Console
|
|||
send commands to the BC. When EFM_BC_EN is low, EFM_BC_TX and EFM_BC_RX
|
||||
can be used by other applications.
|
||||
|
||||
Configurations
|
||||
USING THE J-LINK GDB SERVER
|
||||
===========================
|
||||
|
||||
1. Star the J-Link GDB server. You should see the start-up confiration
|
||||
window. SelectL
|
||||
|
||||
a. Target device = EFM32G880F128
|
||||
b. Select Target interface = SWD
|
||||
|
||||
2. Press OK. The GDB server should start and the last message in the Log
|
||||
output should be "Waiting for GDB connection".
|
||||
|
||||
3. In a terminal window, start GDB:
|
||||
|
||||
arm-none-eabi-gdb
|
||||
|
||||
4. Connect to the J-Link GDB serer:
|
||||
|
||||
(gdb) target remote local host
|
||||
|
||||
5. Load and run nuttx
|
||||
|
||||
(gdb) mon halt
|
||||
(gdb) load nuttx
|
||||
(gdb) mon reset go
|
||||
|
||||
I had to tinker with the setup a few times repeating the same steps above
|
||||
before things finally began to work. Don't know why.
|
||||
|
||||
To debug code already burned into FLASH:
|
||||
|
||||
1. Start the GDB server as above.
|
||||
|
||||
2. In a terminal window, start GDB:
|
||||
|
||||
arm-none-eabi-gdb
|
||||
|
||||
3. Connect to the J-Link GDB serer:
|
||||
|
||||
(gdb) target remote local host
|
||||
|
||||
3. Load the nuttx symbol file, reset, and debug
|
||||
|
||||
(gdb) mon halt
|
||||
(gdb) file nuttx
|
||||
(gdb) mon reset
|
||||
(gdb) s
|
||||
...
|
||||
|
||||
CONFIGURATIONS
|
||||
==============
|
||||
|
||||
Each EFM32 Gecko Starter Kit configuration is maintained in a sub-directory
|
||||
and can be selected as follow:
|
||||
|
||||
|
|
|
|||
|
|
@ -172,37 +172,32 @@
|
|||
|
||||
/* LED index values for use with efm32_setled() */
|
||||
|
||||
#define BOARD_LED1 0
|
||||
#define BOARD_LED2 1
|
||||
#define BOARD_LED3 2
|
||||
#define BOARD_LED4 3
|
||||
#define BOARD_LED0 0
|
||||
#define BOARD_LED1 1
|
||||
#define BOARD_LED2 2
|
||||
#define BOARD_LED3 3
|
||||
#define BOARD_NLEDS 4
|
||||
|
||||
#define BOARD_LED_GREEN BOARD_LED1
|
||||
#define BOARD_LED_ORANGE BOARD_LED2
|
||||
#define BOARD_LED_RED BOARD_LED3
|
||||
#define BOARD_LED_BLUE BOARD_LED4
|
||||
|
||||
/* LED bits for use with efm32_setleds() */
|
||||
|
||||
#define BOARD_LED0_BIT (1 << BOARD_LED0)
|
||||
#define BOARD_LED1_BIT (1 << BOARD_LED1)
|
||||
#define BOARD_LED2_BIT (1 << BOARD_LED2)
|
||||
#define BOARD_LED3_BIT (1 << BOARD_LED3)
|
||||
#define BOARD_LED4_BIT (1 << BOARD_LED4)
|
||||
|
||||
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on
|
||||
* board the EFM32 Gecko Starter Kit. The following definitions describe
|
||||
* how NuttX controls the LEDs in this configuration:
|
||||
*/
|
||||
|
||||
#define LED_STARTED 0 /* LED1 */
|
||||
#define LED_HEAPALLOCATE 1 /* LED2 */
|
||||
#define LED_IRQSENABLED 2 /* LED1 + LED2 */
|
||||
#define LED_STACKCREATED 3 /* LED3 */
|
||||
#define LED_INIRQ 4 /* LED1 + LED3 */
|
||||
#define LED_SIGNAL 5 /* LED2 + LED3 */
|
||||
#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
|
||||
#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
|
||||
#define LED_STARTED 0 /* LED0 */
|
||||
#define LED_HEAPALLOCATE 1 /* LED1 */
|
||||
#define LED_IRQSENABLED 2 /* LED0 + LED1 */
|
||||
#define LED_STACKCREATED 3 /* LED2 */
|
||||
#define LED_INIRQ 4 /* LED0 + LED2 */
|
||||
#define LED_SIGNAL 5 /* LED1 + LED3 */
|
||||
#define LED_ASSERTION 6 /* LED0 + LED2 + LED2 */
|
||||
#define LED_PANIC 7 /* N/C + N/C + N/C + LED3 */
|
||||
|
||||
/* Pin routing **************************************************************/
|
||||
/* UART0:
|
||||
|
|
@ -211,6 +206,8 @@
|
|||
* U0_TX #1 PE0 **AVAILABLE at TP129**
|
||||
*/
|
||||
|
||||
#define BOARD_UART0_RX_GPIO (GPIO_PORTE|GPIO_PIN1)
|
||||
#define BOARD_UART0_TX_GPIO (GPIO_PORTE|GPIO_PIN0)
|
||||
#define BOARD_UART0_ROUTE_LOCATION _USART_ROUTE_LOCATION_LOC1
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -139,9 +139,11 @@ CONFIG_EFM32_HAVE_USART2=y
|
|||
CONFIG_EFM32_HAVE_UART0=y
|
||||
# CONFIG_EFM32_HAVE_UART1 is not set
|
||||
CONFIG_EFM32_HAVE_LEUART1=y
|
||||
# CONFIG_EFM32_USART is not set
|
||||
# CONFIG_EFM32_USART_ISUART is not set
|
||||
# CONFIG_EFM32_USART_ISSPI is not set
|
||||
CONFIG_EFM32_UART=y
|
||||
# CONFIG_EFM32_LEUART is not set
|
||||
# CONFIG_EFM32_DMA is not set
|
||||
# CONFIG_EFM32_USART0 is not set
|
||||
# CONFIG_EFM32_USART1 is not set
|
||||
# CONFIG_EFM32_USART2 is not set
|
||||
|
|
@ -399,6 +401,7 @@ CONFIG_ARCH_HAVE_UART0=y
|
|||
#
|
||||
CONFIG_MCU_SERIAL=y
|
||||
CONFIG_STANDARD_SERIAL=y
|
||||
# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
# CONFIG_OTHER_SERIAL_CONSOLE is not set
|
||||
# CONFIG_NO_SERIAL_CONSOLE is not set
|
||||
|
|
|
|||
|
|
@ -78,13 +78,13 @@
|
|||
* value to the LED.
|
||||
*/
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\
|
||||
#define GPIO_LED0 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_LED2 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\
|
||||
#define GPIO_LED1 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_LED3 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\
|
||||
#define GPIO_LED2 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_LED4 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\
|
||||
#define GPIO_LED3 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN3)
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -72,10 +72,10 @@
|
|||
|
||||
/* The following definitions map the encoded LED setting to GPIO settings */
|
||||
|
||||
#define EFM32F4_LED1 (1 << 0)
|
||||
#define EFM32F4_LED2 (1 << 1)
|
||||
#define EFM32F4_LED3 (1 << 2)
|
||||
#define EFM32F4_LED4 (1 << 3)
|
||||
#define EFM32_LED0 (1 << 0)
|
||||
#define EFM32_LED1 (1 << 1)
|
||||
#define EFM32_LED2 (1 << 2)
|
||||
#define EFM32_LED3 (1 << 3)
|
||||
|
||||
#define ON_SETBITS_SHIFT (0)
|
||||
#define ON_CLRBITS_SHIFT (4)
|
||||
|
|
@ -92,45 +92,45 @@
|
|||
#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v))
|
||||
#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v))
|
||||
|
||||
#define LED_STARTED_ON_SETBITS ((EFM32F4_LED1) << ON_SETBITS_SHIFT)
|
||||
#define LED_STARTED_ON_CLRBITS ((EFM32F4_LED2|EFM32F4_LED3|EFM32F4_LED4) << ON_CLRBITS_SHIFT)
|
||||
#define LED_STARTED_ON_SETBITS ((EFM32_LED0) << ON_SETBITS_SHIFT)
|
||||
#define LED_STARTED_ON_CLRBITS ((EFM32_LED1|EFM32_LED2|EFM32_LED3) << ON_CLRBITS_SHIFT)
|
||||
#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT)
|
||||
#define LED_STARTED_OFF_CLRBITS ((EFM32F4_LED1|EFM32F4_LED2|EFM32F4_LED3|EFM32F4_LED4) << OFF_CLRBITS_SHIFT)
|
||||
#define LED_STARTED_OFF_CLRBITS ((EFM32_LED0|EFM32_LED1|EFM32_LED2|EFM32_LED3) << OFF_CLRBITS_SHIFT)
|
||||
|
||||
#define LED_HEAPALLOCATE_ON_SETBITS ((EFM32F4_LED2) << ON_SETBITS_SHIFT)
|
||||
#define LED_HEAPALLOCATE_ON_CLRBITS ((EFM32F4_LED1|EFM32F4_LED3|EFM32F4_LED4) << ON_CLRBITS_SHIFT)
|
||||
#define LED_HEAPALLOCATE_OFF_SETBITS ((EFM32F4_LED1) << OFF_SETBITS_SHIFT)
|
||||
#define LED_HEAPALLOCATE_OFF_CLRBITS ((EFM32F4_LED2|EFM32F4_LED3|EFM32F4_LED4) << OFF_CLRBITS_SHIFT)
|
||||
#define LED_HEAPALLOCATE_ON_SETBITS ((EFM32_LED1) << ON_SETBITS_SHIFT)
|
||||
#define LED_HEAPALLOCATE_ON_CLRBITS ((EFM32_LED0|EFM32_LED2|EFM32_LED3) << ON_CLRBITS_SHIFT)
|
||||
#define LED_HEAPALLOCATE_OFF_SETBITS ((EFM32_LED0) << OFF_SETBITS_SHIFT)
|
||||
#define LED_HEAPALLOCATE_OFF_CLRBITS ((EFM32_LED1|EFM32_LED2|EFM32_LED3) << OFF_CLRBITS_SHIFT)
|
||||
|
||||
#define LED_IRQSENABLED_ON_SETBITS ((EFM32F4_LED1|EFM32F4_LED2) << ON_SETBITS_SHIFT)
|
||||
#define LED_IRQSENABLED_ON_CLRBITS ((EFM32F4_LED3|EFM32F4_LED4) << ON_CLRBITS_SHIFT)
|
||||
#define LED_IRQSENABLED_OFF_SETBITS ((EFM32F4_LED2) << OFF_SETBITS_SHIFT)
|
||||
#define LED_IRQSENABLED_OFF_CLRBITS ((EFM32F4_LED1|EFM32F4_LED3|EFM32F4_LED4) << OFF_CLRBITS_SHIFT)
|
||||
#define LED_IRQSENABLED_ON_SETBITS ((EFM32_LED0|EFM32_LED1) << ON_SETBITS_SHIFT)
|
||||
#define LED_IRQSENABLED_ON_CLRBITS ((EFM32_LED2|EFM32_LED3) << ON_CLRBITS_SHIFT)
|
||||
#define LED_IRQSENABLED_OFF_SETBITS ((EFM32_LED1) << OFF_SETBITS_SHIFT)
|
||||
#define LED_IRQSENABLED_OFF_CLRBITS ((EFM32_LED0|EFM32_LED2|EFM32_LED3) << OFF_CLRBITS_SHIFT)
|
||||
|
||||
#define LED_STACKCREATED_ON_SETBITS ((EFM32F4_LED3) << ON_SETBITS_SHIFT)
|
||||
#define LED_STACKCREATED_ON_CLRBITS ((EFM32F4_LED1|EFM32F4_LED2|EFM32F4_LED4) << ON_CLRBITS_SHIFT)
|
||||
#define LED_STACKCREATED_OFF_SETBITS ((EFM32F4_LED1|EFM32F4_LED2) << OFF_SETBITS_SHIFT)
|
||||
#define LED_STACKCREATED_OFF_CLRBITS ((EFM32F4_LED3|EFM32F4_LED4) << OFF_CLRBITS_SHIFT)
|
||||
#define LED_STACKCREATED_ON_SETBITS ((EFM32_LED2) << ON_SETBITS_SHIFT)
|
||||
#define LED_STACKCREATED_ON_CLRBITS ((EFM32_LED0|EFM32_LED1|EFM32_LED3) << ON_CLRBITS_SHIFT)
|
||||
#define LED_STACKCREATED_OFF_SETBITS ((EFM32_LED0|EFM32_LED1) << OFF_SETBITS_SHIFT)
|
||||
#define LED_STACKCREATED_OFF_CLRBITS ((EFM32_LED2|EFM32_LED3) << OFF_CLRBITS_SHIFT)
|
||||
|
||||
#define LED_INIRQ_ON_SETBITS ((EFM32F4_LED1) << ON_SETBITS_SHIFT)
|
||||
#define LED_INIRQ_ON_SETBITS ((EFM32_LED0) << ON_SETBITS_SHIFT)
|
||||
#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT)
|
||||
#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT)
|
||||
#define LED_INIRQ_OFF_CLRBITS ((EFM32F4_LED1) << OFF_CLRBITS_SHIFT)
|
||||
#define LED_INIRQ_OFF_CLRBITS ((EFM32_LED0) << OFF_CLRBITS_SHIFT)
|
||||
|
||||
#define LED_SIGNAL_ON_SETBITS ((EFM32F4_LED2) << ON_SETBITS_SHIFT)
|
||||
#define LED_SIGNAL_ON_SETBITS ((EFM32_LED1) << ON_SETBITS_SHIFT)
|
||||
#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT)
|
||||
#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT)
|
||||
#define LED_SIGNAL_OFF_CLRBITS ((EFM32F4_LED2) << OFF_CLRBITS_SHIFT)
|
||||
#define LED_SIGNAL_OFF_CLRBITS ((EFM32_LED1) << OFF_CLRBITS_SHIFT)
|
||||
|
||||
#define LED_ASSERTION_ON_SETBITS ((EFM32F4_LED4) << ON_SETBITS_SHIFT)
|
||||
#define LED_ASSERTION_ON_SETBITS ((EFM32_LED3) << ON_SETBITS_SHIFT)
|
||||
#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT)
|
||||
#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT)
|
||||
#define LED_ASSERTION_OFF_CLRBITS ((EFM32F4_LED4) << OFF_CLRBITS_SHIFT)
|
||||
#define LED_ASSERTION_OFF_CLRBITS ((EFM32_LED3) << OFF_CLRBITS_SHIFT)
|
||||
|
||||
#define LED_PANIC_ON_SETBITS ((EFM32F4_LED4) << ON_SETBITS_SHIFT)
|
||||
#define LED_PANIC_ON_SETBITS ((EFM32_LED3) << ON_SETBITS_SHIFT)
|
||||
#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT)
|
||||
#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT)
|
||||
#define LED_PANIC_OFF_CLRBITS ((EFM32F4_LED4) << OFF_CLRBITS_SHIFT)
|
||||
#define LED_PANIC_OFF_CLRBITS ((EFM32_LED3) << OFF_CLRBITS_SHIFT)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
|
|
@ -169,48 +169,48 @@ static const uint16_t g_ledbits[8] =
|
|||
|
||||
static inline void led_clrbits(unsigned int clrbits)
|
||||
{
|
||||
if ((clrbits & EFM32F4_LED1) != 0)
|
||||
if ((clrbits & EFM32_LED0) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED0, false);
|
||||
}
|
||||
|
||||
if ((clrbits & EFM32_LED1) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED1, false);
|
||||
}
|
||||
|
||||
if ((clrbits & EFM32F4_LED2) != 0)
|
||||
if ((clrbits & EFM32_LED2) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED2, false);
|
||||
}
|
||||
|
||||
if ((clrbits & EFM32F4_LED3) != 0)
|
||||
if ((clrbits & EFM32_LED3) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED3, false);
|
||||
}
|
||||
|
||||
if ((clrbits & EFM32F4_LED4) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED4, false);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void led_setbits(unsigned int setbits)
|
||||
{
|
||||
if ((setbits & EFM32F4_LED1) != 0)
|
||||
if ((setbits & EFM32_LED0) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED0, true);
|
||||
}
|
||||
|
||||
if ((setbits & EFM32_LED1) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED1, true);
|
||||
}
|
||||
|
||||
if ((setbits & EFM32F4_LED2) != 0)
|
||||
if ((setbits & EFM32_LED2) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED2, true);
|
||||
}
|
||||
|
||||
if ((setbits & EFM32F4_LED3) != 0)
|
||||
if ((setbits & EFM32_LED3) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED3, true);
|
||||
}
|
||||
|
||||
if ((setbits & EFM32F4_LED4) != 0)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED4, true);
|
||||
}
|
||||
}
|
||||
|
||||
static void led_setonoff(unsigned int bits)
|
||||
|
|
@ -229,12 +229,12 @@ static void led_setonoff(unsigned int bits)
|
|||
|
||||
void board_led_initialize(void)
|
||||
{
|
||||
/* Configure LED1-4 GPIOs for output */
|
||||
/* Configure LED0-4 GPIOs for output */
|
||||
|
||||
efm32_configgpio(GPIO_LED0);
|
||||
efm32_configgpio(GPIO_LED1);
|
||||
efm32_configgpio(GPIO_LED2);
|
||||
efm32_configgpio(GPIO_LED3);
|
||||
efm32_configgpio(GPIO_LED4);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@
|
|||
|
||||
static gpio_pinset_t g_ledcfg[BOARD_NLEDS] =
|
||||
{
|
||||
GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4
|
||||
GPIO_LED0, GPIO_LED1, GPIO_LED2, GPIO_LED3
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -193,12 +193,12 @@ static int led_pm_prepare(struct pm_callback_s *cb , enum pm_state_e pmstate)
|
|||
|
||||
void efm32_ledinit(void)
|
||||
{
|
||||
/* Configure LED1-4 GPIOs for output */
|
||||
/* Configure LED0-4 GPIOs for output */
|
||||
|
||||
efm32_configgpio(GPIO_LED0);
|
||||
efm32_configgpio(GPIO_LED1);
|
||||
efm32_configgpio(GPIO_LED2);
|
||||
efm32_configgpio(GPIO_LED3);
|
||||
efm32_configgpio(GPIO_LED4);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -219,10 +219,10 @@ void efm32_setled(int led, bool ledon)
|
|||
|
||||
void efm32_setleds(uint8_t ledset)
|
||||
{
|
||||
efm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0);
|
||||
efm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0);
|
||||
efm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0);
|
||||
efm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0);
|
||||
efm32_gpiowrite(GPIO_LED0, (ledset & BOARD_LED0_BIT) != 0);
|
||||
efm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0);
|
||||
efm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0);
|
||||
efm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -237,6 +237,8 @@
|
|||
* U0_TX #1 PE0 **AVAILABLE at EXT-18**
|
||||
*/
|
||||
|
||||
#define BOARD_UART0_RX_GPIO (GPIO_PORTE|GPIO_PIN1)
|
||||
#define BOARD_UART0_TX_GPIO (GPIO_PORTE|GPIO_PIN0)
|
||||
#define BOARD_UART0_ROUTE_LOCATION _USART_ROUTE_LOCATION_LOC1
|
||||
|
||||
/* LEUART1:
|
||||
|
|
@ -245,6 +247,8 @@
|
|||
* LEU1_TX #0 PC6 LEU1_TX to DB-9 connector
|
||||
*/
|
||||
|
||||
#define BOARD_LEUART1_RX_GPIO (GPIO_PORTC|GPIO_PIN7)
|
||||
#define BOARD_LEUART1_TX_GPIO (GPIO_PORTC|GPIO_PIN6)
|
||||
#define BOARD_LEUART1_ROUTE_LOCATION _LEUART_ROUTE_LOCATION_LOC0
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ CONFIG_ARCH="arm"
|
|||
# CONFIG_ARCH_CHIP_C5471 is not set
|
||||
# CONFIG_ARCH_CHIP_CALYPSO is not set
|
||||
# CONFIG_ARCH_CHIP_DM320 is not set
|
||||
# CONFIG_ARCH_CHIP_EFM32 is not set
|
||||
# CONFIG_ARCH_CHIP_IMX is not set
|
||||
# CONFIG_ARCH_CHIP_KINETIS is not set
|
||||
# CONFIG_ARCH_CHIP_KL is not set
|
||||
|
|
@ -120,7 +121,7 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
|
|||
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set
|
||||
# CONFIG_SERIAL_TERMIOS is not set
|
||||
# CONFIG_ARMV7M_ITMSYSLOG is not set
|
||||
|
||||
#
|
||||
# STM32 Configuration Options
|
||||
|
|
@ -188,6 +189,7 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
|
|||
# CONFIG_ARCH_CHIP_STM32F303VB is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F303VC is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F401RE is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F411RE is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F405RG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F405VG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F405ZG is not set
|
||||
|
|
@ -219,6 +221,7 @@ CONFIG_ARCH_CHIP_STM32F407VG=y
|
|||
# CONFIG_STM32_STM32F30XX is not set
|
||||
CONFIG_STM32_STM32F40XX=y
|
||||
# CONFIG_STM32_STM32F401 is not set
|
||||
# CONFIG_STM32_STM32F411 is not set
|
||||
# CONFIG_STM32_STM32F405 is not set
|
||||
CONFIG_STM32_STM32F407=y
|
||||
# CONFIG_STM32_STM32F427 is not set
|
||||
|
|
@ -259,6 +262,10 @@ CONFIG_STM32_HAVE_CAN1=y
|
|||
CONFIG_STM32_HAVE_CAN2=y
|
||||
CONFIG_STM32_HAVE_RNG=y
|
||||
CONFIG_STM32_HAVE_ETHMAC=y
|
||||
CONFIG_STM32_HAVE_SPI2=y
|
||||
CONFIG_STM32_HAVE_SPI3=y
|
||||
# CONFIG_STM32_HAVE_SPI4 is not set
|
||||
# CONFIG_STM32_HAVE_SPI5 is not set
|
||||
# CONFIG_STM32_ADC1 is not set
|
||||
# CONFIG_STM32_ADC2 is not set
|
||||
# CONFIG_STM32_ADC3 is not set
|
||||
|
|
@ -340,7 +347,15 @@ CONFIG_STM32_USART=y
|
|||
# CONFIG_STM32_SPI_DMA is not set
|
||||
|
||||
#
|
||||
# USB Host Configuration
|
||||
# USB FS Host Configuration
|
||||
#
|
||||
|
||||
#
|
||||
# USB HS Host Configuration
|
||||
#
|
||||
|
||||
#
|
||||
# USB Host Debug Configuration
|
||||
#
|
||||
|
||||
#
|
||||
|
|
@ -424,6 +439,7 @@ CONFIG_NSH_MMCSDMINOR=0
|
|||
#
|
||||
# Board-Specific Options
|
||||
#
|
||||
# CONFIG_STM32F4DISBB is not set
|
||||
|
||||
#
|
||||
# RTOS Features
|
||||
|
|
@ -453,6 +469,9 @@ CONFIG_PREALLOC_TIMERS=4
|
|||
#
|
||||
# Tasks and Scheduling
|
||||
#
|
||||
# CONFIG_INIT_NONE is not set
|
||||
CONFIG_INIT_ENTRYPOINT=y
|
||||
# CONFIG_INIT_FILEPATH is not set
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
|
|
@ -507,6 +526,13 @@ CONFIG_SIG_SIGCONDTIMEDOUT=16
|
|||
CONFIG_PREALLOC_MQ_MSGS=4
|
||||
CONFIG_MQ_MAXMSGSIZE=32
|
||||
|
||||
#
|
||||
# Work Queue Support
|
||||
#
|
||||
# CONFIG_SCHED_WORKQUEUE is not set
|
||||
# CONFIG_SCHED_HPWORK is not set
|
||||
# CONFIG_SCHED_LPWORK is not set
|
||||
|
||||
#
|
||||
# Stack and heap information
|
||||
#
|
||||
|
|
@ -581,6 +607,7 @@ CONFIG_ARCH_HAVE_USART2=y
|
|||
# CONFIG_ARCH_HAVE_USART6 is not set
|
||||
# CONFIG_ARCH_HAVE_USART7 is not set
|
||||
# CONFIG_ARCH_HAVE_USART8 is not set
|
||||
# CONFIG_ARCH_HAVE_OTHER_UART is not set
|
||||
|
||||
#
|
||||
# USART Configuration
|
||||
|
|
@ -588,7 +615,10 @@ CONFIG_ARCH_HAVE_USART2=y
|
|||
CONFIG_USART2_ISUART=y
|
||||
CONFIG_MCU_SERIAL=y
|
||||
CONFIG_STANDARD_SERIAL=y
|
||||
CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
|
||||
# CONFIG_SERIAL_TERMIOS is not set
|
||||
CONFIG_USART2_SERIAL_CONSOLE=y
|
||||
# CONFIG_OTHER_SERIAL_CONSOLE is not set
|
||||
# CONFIG_NO_SERIAL_CONSOLE is not set
|
||||
|
||||
#
|
||||
|
|
@ -641,6 +671,8 @@ CONFIG_USART2_2STOP=0
|
|||
# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
|
||||
# CONFIG_FS_READABLE is not set
|
||||
# CONFIG_FS_WRITABLE is not set
|
||||
# CONFIG_FS_NAMED_SEMAPHORES is not set
|
||||
CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
|
||||
# CONFIG_FS_RAMMAP is not set
|
||||
# CONFIG_FS_FAT is not set
|
||||
# CONFIG_FS_NXFFS is not set
|
||||
|
|
@ -652,7 +684,6 @@ CONFIG_USART2_2STOP=0
|
|||
#
|
||||
# System Logging
|
||||
#
|
||||
|
||||
# CONFIG_SYSLOG is not set
|
||||
|
||||
#
|
||||
|
|
@ -674,7 +705,7 @@ CONFIG_MM_REGIONS=2
|
|||
# CONFIG_AUDIO is not set
|
||||
|
||||
#
|
||||
# Binary Formats
|
||||
# Binary Loader
|
||||
#
|
||||
# CONFIG_BINFMT_DISABLE is not set
|
||||
# CONFIG_BINFMT_EXEPATH is not set
|
||||
|
|
@ -717,7 +748,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
|
|||
#
|
||||
# Non-standard Library Support
|
||||
#
|
||||
# CONFIG_SCHED_WORKQUEUE is not set
|
||||
# CONFIG_LIB_KBDCODEC is not set
|
||||
# CONFIG_LIB_SLCDCODEC is not set
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue