diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
index 1db1766890..c9b4a11d09 100644
--- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
@@ -1009,10 +1009,10 @@ void stm32_stdclockconfig(void)
 
       /* Configure ADC source clock */
 
-#if defined(STM32_RCC_D3CCIPR_ADCSEL)
+#if defined(STM32_RCC_D3CCIPR_ADCSRC)
       regval = getreg32(STM32_RCC_D3CCIPR);
       regval &= ~RCC_D3CCIPR_ADCSEL_MASK;
-      regval |= STM32_RCC_D3CCIPR_ADCSEL;
+      regval |= STM32_RCC_D3CCIPR_ADCSRC;
       putreg32(regval, STM32_RCC_D3CCIPR);
 #endif
 
diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
index 90ffc7758b..c42876b383 100644
--- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
@@ -983,10 +983,10 @@ void stm32_stdclockconfig(void)
 
       /* Configure ADC source clock */
 
-#if defined(STM32_RCC_D3CCIPR_ADCSEL)
+#if defined(STM32_RCC_D3CCIPR_ADCSRC)
       regval = getreg32(STM32_RCC_D3CCIPR);
       regval &= ~RCC_D3CCIPR_ADCSEL_MASK;
-      regval |= STM32_RCC_D3CCIPR_ADCSEL;
+      regval |= STM32_RCC_D3CCIPR_ADCSRC;
       putreg32(regval, STM32_RCC_D3CCIPR);
 #endif
 
diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h
index 666c0bbae6..cf20b93511 100644
--- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h
+++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h
@@ -232,7 +232,7 @@
 
 /* ADC 1 2 3 clock source - pll2_pclk */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FLASH wait states
  *
diff --git a/boards/arm/stm32h7/nucleo-h743zi/include/board.h b/boards/arm/stm32h7/nucleo-h743zi/include/board.h
index 99d5a380fa..1252b6c372 100644
--- a/boards/arm/stm32h7/nucleo-h743zi/include/board.h
+++ b/boards/arm/stm32h7/nucleo-h743zi/include/board.h
@@ -240,7 +240,7 @@
 
 /* ADC 1 2 3 clock source - pll2_pclk */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FLASH wait states
  *
diff --git a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h
index 25588b09e5..41b80ba563 100644
--- a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h
+++ b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h
@@ -240,7 +240,7 @@
 
 /* ADC 1 2 3 clock source - pll2_pclk */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 2 clock source - HSE (TODO: Not the best choice for this board?) */
 
diff --git a/boards/arm/stm32h7/nucleo-h745zi/include/board.h b/boards/arm/stm32h7/nucleo-h745zi/include/board.h
index 10c481c29d..5c75966617 100644
--- a/boards/arm/stm32h7/nucleo-h745zi/include/board.h
+++ b/boards/arm/stm32h7/nucleo-h745zi/include/board.h
@@ -240,7 +240,7 @@
 
 /* ADC 1 2 3 clock source - pll2_pclk */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FLASH wait states
  *
diff --git a/boards/arm/stm32h7/stm32h745i-disco/include/board.h b/boards/arm/stm32h7/stm32h745i-disco/include/board.h
index feefe1ec08..461d5268f6 100644
--- a/boards/arm/stm32h7/stm32h745i-disco/include/board.h
+++ b/boards/arm/stm32h7/stm32h745i-disco/include/board.h
@@ -236,7 +236,7 @@
 
 /* ADC 1 2 3 clock source - pll2_pclk */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FLASH wait states
  *
diff --git a/boards/arm/stm32h7/stm32h747i-disco/include/board.h b/boards/arm/stm32h7/stm32h747i-disco/include/board.h
index e57983fbef..96c74b6692 100644
--- a/boards/arm/stm32h7/stm32h747i-disco/include/board.h
+++ b/boards/arm/stm32h7/stm32h747i-disco/include/board.h
@@ -232,7 +232,7 @@
 
 /* ADC 1 2 3 clock source - pll2_pclk */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FLASH wait states
  *