Merged in extent3d/nuttx (pull request #582)
SAMDL: Added SAMD DAC header file. Fixed SAMD EVSYS header. Added SAMD TC header file. Fixed some minor typos
* SAMD External Interrupt Controller (EIC) support
* removed comment
* SAMDL: SPI must be disabled before changing the mode bits in CTRLA register
* arch/arm/src/lc823450: Assign I2S IRQ handling to CPU0
Previous commit assumed that the caller is running on CPU0.
However, the caller sometimes runs at CPU1. This patch will
assign the caller to CPU0 explicitly.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Change irqwarn() to ASSERT() in up_ack_irq()
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update README.txt and defconfigs
Update comments on SMP in README.txt
Enable SYSTEM_TIME64 in defconfigs.
Enable INSTRUMENTATION in rndis configuration.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configst/stm3240g-eval: Remove only bogus logic to start the NX server. That was there only to support the knxwm configuration and was implemented priorit to boardctl(BOARCIOC_NX_START).
* drivers/input/ft5x06.c: Remove cool logic to disable polling when there there is no client waiting for read data. That was a great idea to save CPU cycles when there is nothing reading from the touchscrren but, unfortunately, does not work with readers that open the driver in non-blocking mode. So I think we just have to eat the CPUs even when there is nothing waiting for touchscreen input.
* configs/lpcxpresso-lpc54628/lvgl: Add LittlevGL graphics demo configuration.
* configs/lpcxpresso-lpc54628: Update README
* include/termios.h: Update comments; fix long lines.
* sched/semaphore: Add ASSERT(false) in nxsem_post() if no waiting task is found.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* sched/sched/sched_sporadic.c: fix compiler error when priority inheritance is enabled. Noted by eunb.song@samsung.com
* Change ASSERT(false) to DEBUGPANIC().
* Documentation: Fix copy/paste error in NX graphics document. Noted by Henjiu Kang.
* sched/sched: Fix some priority inheritance related issues noted during review of logic. Also add some REVISIT comments for some issues noted in the design.
* Update README and some comments
* Issue #85: /dev/userleds is not working for nucleo-l432kc fixed
* configs/nucleo-l432kc: Fix numerous cloning errors/typos.
* Update TODO list
* NUCLEO F432KC typo fixed, correct name is L432KC
Just README.txt and comments affected, no changes in the code
* Merged in raiden00/nuttx (pull request #579)
Master
* stm32_hritm: add interface to get timer clock frequency
stm32_hrtim: fix timer freq calculation
stm32_hrtim: add compar/capture registers significant bits checking
stm32_hrtim: minor changes
* stm32f334-disco: add buck converter and boost converter logic
Approved-by: Gregory Nutt <gnutt@nuttx.org>
* fs/userfs: use correct req type in userfs_truncate, remove use of undeclared buf
* Merged in david_alessio/nuttx/refactor-pll-setup (pull request #581)
Refactor pll setup
* fix typo in #def
* refactor PLL setup code...
* refactored PLL/CLK config, easier, checks for correctness
* call go_os_start if STACK_COLORIZED
* smarter config of EXTCLK output freq
* cosmetic
Approved-by: Gregory Nutt <gnutt@nuttx.org>
* The existence of the network driver ioctl() method should depend on CONFIG_NETDEV_IOCTL rather than CONFIG_NETDEV_PHY_IOCTL. The former enables the method, the later enables a subset of possible driver IOCTLs. This change should be basically a no-operation. The affected ioctl methods only support those subset of driver IOCTLs selected by CONFIG_NETDEV_PHY_IOCTL and the network logic will tolerate a nul ioctl method.
* net/tcp: Write buffering logic should not wait for a free buffer if the socket was opened non-blocking. Also, rename the TCP write buffering macros from WRB_* to TCPWB_* to make room in the namespace for write buffering with other protocols.
* net/udp: Remove some conditional logic that was true if there is only a single network device, but not true in the multi-device context.
* This commit adds an as-of-yet untested implemented of UDP write buffering.
Squashed commit of the following:
net/udp: Address most of the issues with UDP write buffering. There is a remaining issue with handling one network going down in a multi-network environment. None of this has been test but it is certainly ready for test. Hence, the feature is marked EXPERIMENTAL.
net/udp: Some baby steps toward a corrected write buffering design.
net/udp: Remove pesky write buffer macros.
Eliminate trailing space at the end of lines.
net/udp: A little more UDP write buffering logic. Still at least on big gaping hole in the design.
net/udp: Undefined CONFIG_NET_SENDTO_TIMEOUT.
net/udp: Crude, naive port of the TCP write buffering logic into UDP. This commit is certainly non-functional and is simply a starting point for the implementatin of UDP write buffering.
net/udp: Rename udp/udp_psock_sendto.c udp/udp_psock_sendto_unbuffered.c.
* net/udp: In sendto(), return EHOSTUNREACH if if the network is down.
* net/udp: Resolves final design issues with UDP write buffering. 100% code complete but also 100% untested.
* net/udp and tcp: Yet another (cosmetic) change to UDP and TCP write buffer macro naming.
* net/udp: UDP write buffering is basically functional but needs a lot more verification.
* net/udp: Fix memory leak with UDP + write buffer is closed. Also update TODO and comments and refresh a configuration.
* Update some comments.
* drivers/mtd/at24xx.c: Correct page size for AT24C02 part.
* arch/arm/src/stm32: Make STM32 usable with an external RTC. drivers/timers/ds3231.c: Correct some debug statments.
* arch/arm/src/stm32/stm32_spi.c: Removed unnecessary (and incorrect) speed limitation
* arch/arm/src/stm32/stm32f40xxx_i2c.c: Correct some recent changes to STM32F4 I2C that broke poll mode of operation.
* configs/flipnclick-sam3x: Using JTAG (vs. Bossac) I was finally able to load code and verify the basic NSH configuration. Updated READMEs. Also switched to USART0 (vs UART0) for the serial console because I was not getting bi-directional communication on the VCOM.
* SAMDL: Added SAMD DAC header file. Fixed SAMD EVSYS header. Added SAMD TC header file. Fixed some minor typos
* fix typo
* added missing EVCTRL register bits in TC
Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Matt Thompson
Gregory Nutt
parent
cafb527262
commit
d314feab82
6 changed files with 565 additions and 18 deletions
136
arch/arm/src/samdl/chip/samd_dac.h
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136
arch/arm/src/samdl/chip/samd_dac.h
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@ -0,0 +1,136 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_dac.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DAC_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DAC_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* DAC register offsets ********************************************************************/
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#define SAM_DAC_CTRLA_OFFSET 0x0000 /* Control A Register */
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#define SAM_DAC_CTRLB_OFFSET 0x0001 /* Control B Register */
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#define SAM_DAC_EVCTRL_OFFSET 0x0002 /* Event Control Register */
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#define SAM_DAC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
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#define SAM_DAC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
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#define SAM_DAC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
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#define SAM_DAC_STATUS_OFFSET 0x0007 /* Status Register */
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#define SAM_DAC_DATA0_OFFSET 0x0008 /* Data DAC0 Register */
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#define SAM_DAC_DATA1_OFFSET 0x0009 /* Data DAC1 Register */
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#define SAM_DAC_DATABUF0_OFFSET 0x000C /* Data Buffer DAC0 Register */
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#define SAM_DAC_DATABUF1_OFFSET 0x000D /* Data Buffer DAC1 Register */
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/* DAC register addresses ******************************************************************/
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#define SAM_DAC_CTRLA (SAM_DAC_BASE+SAM_DAC_CTRLA_OFFSET)
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#define SAM_DAC_CTRLB (SAM_DAC_BASE+SAM_DAC_CTRLB_OFFSET)
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#define SAM_DAC_EVCTRL (SAM_DAC_BASE+SAM_DAC_EVCTRL_OFFSET)
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#define SAM_DAC_INTENCLR (SAM_DAC_BASE+SAM_DAC_INTENCLR_OFFSET)
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#define SAM_DAC_INTENSET (SAM_DAC_BASE+SAM_DAC_INTENSET_OFFSET)
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#define SAM_DAC_INTFLAG (SAM_DAC_BASE+SAM_DAC_INTFLAG_OFFSET)
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#define SAM_DAC_STATUS (SAM_DAC_BASE+SAM_DAC_STATUS_OFFSET)
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#define SAM_DAC_DATA0 (SAM_DAC_BASE+SAM_DAC_DATA0_OFFSET)
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#define SAM_DAC_DATA1 (SAM_DAC_BASE+SAM_DAC_DATA1_OFFSET)
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#define SAM_DAC_DATABUF0 (SAM_DAC_BASE+SAM_DAC_DATABUF0_OFFSET)
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#define SAM_DAC_DATABUF1 (SAM_DAC_BASE+SAM_DAC_DATABUF1_OFFSET)
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/* DAC register bit definitions ************************************************************/
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/* Control A Register */
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#define DAC_CTRLA_SWRTS (1 << 0) /* Bit 0: Software reset */
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#define DAC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable DAC controller */
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#define DAC_CTRLA_RUNSTDBY (1 << 2) /* Bit 1: Run in standby */
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/* Control B Register */
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#define DAC_CTRLB_EOEN (1 << 0) /* Bit 0: External Output Enable (to Vout) */
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#define DAC_CTRLB_IOEN (1 << 1) /* Bit 1: Internal Output Enable (to analog comparator) */
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#define DAC_CTRLB_LEFTADJ (1 << 2) /* Bit 2: Left-Adjusted Data */
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#define DAC_CTRLB_VPD (1 << 3) /* Bit 3: Voltage Pump Disabled */
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#define DAC_CTRLB_BDWP (1 << 4) /* Bit 4: Bypass DATABUF Write protection */
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#define DAC_CTRLB_REFSEL_SHIFT (6) /* Bit 7:6: Reference selection */
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#define DAC_CTRLB_REFSEL_MASK (3 << DAC_CTRLB_REFSEL_SHIFT)
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# define DAC_CTRLB_REFSEL_INTREF (0 << DAC_CTRLB_REFSEL_SHIFT) /* Internal voltage reference */
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# define DAC_CTRLB_REFSEL_VDDANA (1 << DAC_CTRLB_REFSEL_SHIFT) /* Analog voltage supply */
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# define DAC_CTRLB_REFSEL_VREFA (2 << DAC_CTRLB_REFSEL_SHIFT) /* External voltage reference */
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/* Event Control Register */
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#define DAC_EVCTRL_STARTEI (1 << 0) /* Bit 0: Start conversion event input */
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#define DAC_EVCTRL_EMPTYEO (1 << 1) /* Bit 1: Data buffer empty event output */
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/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set
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* Register, and Interrupt Flag Status and Clear Register
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*/
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#define DAC_INT_UNDERRUN (1 << 0) /* Bit 0: Underrun interrupt */
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#define DAC_INT_EMPTY (1 << 1) /* Bit 1: Data buffer empty interrupt */
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#define DAC_INT_SYNCRDY (1 << 2) /* Bit 2: Sync ready */
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#define DAC_INT_ALL 0x07
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/* Status Register */
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#define DAC_STATUS_SYNCBUSY (1 << 7) /* Bit 0: Sync busy */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DAC_H */
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@ -68,9 +68,9 @@
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#define SAM_EVSYS_CTRL (SAM_EVSYS_BASE+SAM_EVSYS_CTRL_OFFSET)
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#define SAM_EVSYS_CHANNEL (SAM_EVSYS_BASE+SAM_EVSYS_CHANNEL_OFFSET)
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#define SAM_EVSYS_USER (SAM_EVSYS_BASE+SAM_EVSYS_USER_OFFSET)
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#define SAM_EVSYS_CHSTATUS (SAM_EVSYS_BASE+SAM_EVSYS_CHSTATUS_OFFSET
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#define SAM_EVSYS_INTENCLR (SAM_EVSYS_BASE+SAM_EVSYS_INTENCLR_OFFSET
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#define SAM_EVSYS_INTENSET (SAM_EVSYS_BASE+SAM_EVSYS_INTENSET_OFFSET
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#define SAM_EVSYS_CHSTATUS (SAM_EVSYS_BASE+SAM_EVSYS_CHSTATUS_OFFSET)
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#define SAM_EVSYS_INTENCLR (SAM_EVSYS_BASE+SAM_EVSYS_INTENCLR_OFFSET)
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#define SAM_EVSYS_INTENSET (SAM_EVSYS_BASE+SAM_EVSYS_INTENSET_OFFSET)
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#define SAM_EVSYS_INTFLAG (SAM_EVSYS_BASE+SAM_EVSYS_INTFLAG_OFFSET)
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/* EVSYS register bit definitions ***********************************************************/
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@ -302,12 +302,14 @@
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/* Channel status register */
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#define EVSYS_CHSTATUS_USRRDY_SHIFT (0) /* Bits 0-7: User Ready for Channel n, n=0-7 */
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#define EVSYS_CHSTATUS_USRRDY_MASK (0xff << EVSYS_CHSTATUS_USRRDY_SHIFT)
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# define EVSYS_CHSTATUS_USRRDY(n) (1 << (n))
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#define EVSYS_CHSTATUS_CHBUSY_SHIFT (8) /* Bits 8-15: Channel Busy n, n=0-7 */
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#define EVSYS_CHSTATUS_CHBUSY_MASK (0xff << EVSYS_CHSTATUS_CHBUSY_SHIFT)
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# define EVSYS_CHSTATUS_CHBUSY(n) (1 << ((n) + 8))
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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# define EVSYS_CHSTATUS_USRRDY_SHIFT (0) /* Bits 0-7: User Ready for Channel n, n=0-7 */
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# define EVSYS_CHSTATUS_USRRDY_MASK (0xff << EVSYS_CHSTATUS_USRRDY_SHIFT)
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# define EVSYS_CHSTATUS_USRRDY(n) (1 << (n))
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# define EVSYS_CHSTATUS_CHBUSY_SHIFT (8) /* Bits 8-15: Channel Busy n, n=0-7 */
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# define EVSYS_CHSTATUS_CHBUSY_MASK (0xff << EVSYS_CHSTATUS_CHBUSY_SHIFT)
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# define EVSYS_CHSTATUS_CHBUSY(n) (1 << ((n) + 8))
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#endif
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define EVSYS_CHSTATUS_USRRDYH_SHIFT (16) /* Bits 16-19: User Ready for Channel n, n=8-11 */
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@ -320,12 +322,14 @@
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/* Interrupt enable clear, interrupt enable set, and interrupt flag status and clear registers */
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#define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n=0-7 */
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#define EVSYS_INT_OVR_MASK (0xff << EVSYS_INT_OVR_SHIFT)
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# define EVSYS_INT_OVR(n) (1 << (n))
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#define EVSYS_INT_EVD_SHIFT (8) /* Bits 8-15: Event detected channel n interrupt, n=0-7 */
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#define EVSYS_INT_EVD_MASK (0xff << EVSYS_INT_EVD_SHIFT)
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# define EVSYS_INT_EVD(n) (1 << ((n) + 8))
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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# define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n=0-7 */
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# define EVSYS_INT_OVR_MASK (0xff << EVSYS_INT_OVR_SHIFT)
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# define EVSYS_INT_OVR(n) (1 << (n))
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# define EVSYS_INT_EVD_SHIFT (8) /* Bits 8-15: Event detected channel n interrupt, n=0-7 */
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# define EVSYS_INT_EVD_MASK (0xff << EVSYS_INT_EVD_SHIFT)
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# define EVSYS_INT_EVD(n) (1 << ((n) + 8))
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#endif
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define EVSYS_INT_OVR_SHIFT (16) /* Bits 16-19: Overrun channel n interrupt, n=8-11 */
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254
arch/arm/src/samdl/chip/samd_tc.h
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254
arch/arm/src/samdl/chip/samd_tc.h
Normal file
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@ -0,0 +1,254 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/samd_tc.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Matt Thompson <matt@extent3d.com>
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*
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* References:
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* "Microchip SAMD21 datasheet"
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TC_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TC_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* TC register offsets *********************************************************************/
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#define SAM_TC_CTRLA_OFFSET 0x0000 /* Control A register */
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#define SAM_TC_READREQ_OFFSET 0x0002 /* Read request register */
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#define SAM_TC_CTRLBCLR_OFFSET 0x0004 /* Control B clear register */
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#define SAM_TC_CTRLBSET_OFFSET 0x0005 /* Control B clear register */
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#define SAM_TC_CTRLC_OFFSET 0x0006 /* Control C register */
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#define SAM_TC_DBGCTRL_OFFSET 0x0008 /* Debug control register */
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#define SAM_TC_EVCTRL_OFFSET 0x000A /* Event control register */
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#define SAM_TC_INTENCLR_OFFSET 0x000C /* Interrupt enable clear register */
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#define SAM_TC_INTENSET_OFFSET 0x000D /* Interrupt enable set register */
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#define SAM_TC_INTFLAG_OFFSET 0x000E /* Interrupt flag register */
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#define SAM_TC_STATUS_OFFSET 0x000F /* Status register */
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#define SAM_TC_COUNT_OFFSET 0x0010 /* Count register */
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#define SAM_TC_CC0_OFFSET 0x0018 /* Capture Compare 0 register */
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#define SAM_TC_CC1_OFFSET 0x001C /* Capture Compare 1 register */
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/* TC register addresses *******************************************************************/
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#define SAM_TC3_CTRLA (SAM_TC3_BASE+SAM_TC_CTRLA_OFFSET)
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#define SAM_TC3_READREQ (SAM_TC3_BASE+SAM_TC_READREQ_OFFSET)
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#define SAM_TC3_CTRLBCLR (SAM_TC3_BASE+SAM_TC_CTRLBCLR_OFFSET)
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#define SAM_TC3_CTRLBSET (SAM_TC3_BASE+SAM_TC_CTRLBSET_OFFSET)
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#define SAM_TC3_CTRLC (SAM_TC3_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC3_DBGCTRL (SAM_TC3_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC3_EVCTRL (SAM_TC3_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC3_INTENCLR (SAM_TC3_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC3_INTENSET (SAM_TC3_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC3_INTFLAG (SAM_TC3_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC3_STATUS (SAM_TC3_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC3_COUNT (SAM_TC3_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC3_CC0 (SAM_TC3_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC3_CC1 (SAM_TC3_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
#define SAM_TC4_CTRLA (SAM_TC4_BASE+SAM_TC_CTRLA_OFFSET)
|
||||
#define SAM_TC4_READREQ (SAM_TC4_BASE+SAM_TC_READREQ_OFFSET)
|
||||
#define SAM_TC4_CTRLBCLR (SAM_TC4_BASE+SAM_TC_CTRLBCLR_OFFSET)
|
||||
#define SAM_TC4_CTRLBSET (SAM_TC4_BASE+SAM_TC_CTRLBSET_OFFSET)
|
||||
#define SAM_TC4_CTRLC (SAM_TC4_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC4_DBGCTRL (SAM_TC4_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC4_EVCTRL (SAM_TC4_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC4_INTENCLR (SAM_TC4_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC4_INTENSET (SAM_TC4_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC4_INTFLAG (SAM_TC4_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC4_STATUS (SAM_TC4_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC4_COUNT (SAM_TC4_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC4_CC0 (SAM_TC4_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC4_CC1 (SAM_TC4_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
#define SAM_TC5_CTRLA (SAM_TC5_BASE+SAM_TC_CTRLA_OFFSET)
|
||||
#define SAM_TC5_READREQ (SAM_TC5_BASE+SAM_TC_READREQ_OFFSET)
|
||||
#define SAM_TC5_CTRLBCLR (SAM_TC5_BASE+SAM_TC_CTRLBCLR_OFFSET)
|
||||
#define SAM_TC5_CTRLBSET (SAM_TC5_BASE+SAM_TC_CTRLBSET_OFFSET)
|
||||
#define SAM_TC5_CTRLC (SAM_TC5_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC5_DBGCTRL (SAM_TC5_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC5_EVCTRL (SAM_TC5_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC5_INTENCLR (SAM_TC5_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC5_INTENSET (SAM_TC5_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC5_INTFLAG (SAM_TC5_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC5_STATUS (SAM_TC5_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC5_COUNT (SAM_TC5_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC5_CC0 (SAM_TC5_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC5_CC1 (SAM_TC5_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
#define SAM_TC6_CTRLA (SAM_TC6_BASE+SAM_TC_CTRLA_OFFSET)
|
||||
#define SAM_TC6_READREQ (SAM_TC6_BASE+SAM_TC_READREQ_OFFSET)
|
||||
#define SAM_TC6_CTRLBCLR (SAM_TC6_BASE+SAM_TC_CTRLBCLR_OFFSET)
|
||||
#define SAM_TC6_CTRLBSET (SAM_TC6_BASE+SAM_TC_CTRLBSET_OFFSET)
|
||||
#define SAM_TC6_CTRLC (SAM_TC6_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC6_DBGCTRL (SAM_TC6_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC6_EVCTRL (SAM_TC6_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC6_INTENCLR (SAM_TC6_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC6_INTENSET (SAM_TC6_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC6_INTFLAG (SAM_TC6_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC6_STATUS (SAM_TC6_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC6_COUNT (SAM_TC6_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC6_CC0 (SAM_TC6_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC6_CC1 (SAM_TC6_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
#define SAM_TC7_CTRLA (SAM_TC7_BASE+SAM_TC_CTRLA_OFFSET)
|
||||
#define SAM_TC7_READREQ (SAM_TC7_BASE+SAM_TC_READREQ_OFFSET)
|
||||
#define SAM_TC7_CTRLBCLR (SAM_TC7_BASE+SAM_TC_CTRLBCLR_OFFSET)
|
||||
#define SAM_TC7_CTRLBSET (SAM_TC7_BASE+SAM_TC_CTRLBSET_OFFSET)
|
||||
#define SAM_TC7_CTRLC (SAM_TC7_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC7_DBGCTRL (SAM_TC7_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC7_EVCTRL (SAM_TC7_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC7_INTENCLR (SAM_TC7_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC7_INTENSET (SAM_TC7_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC7_INTFLAG (SAM_TC7_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC7_STATUS (SAM_TC7_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC7_COUNT (SAM_TC7_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC7_CC0 (SAM_TC7_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC7_CC1 (SAM_TC7_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
/* TC register bit definitions *************************************************************/
|
||||
|
||||
/* Control A register */
|
||||
|
||||
#define TC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
|
||||
#define TC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
|
||||
#define TC_CTRLA_MODE_SHIFT (2)
|
||||
#define TC_CTRLA_MODE_MASK (3 << TC_CTRLA_MODE_SHIFT)
|
||||
# define TC_CTRLA_MODE_COUNT16 (0 << TC_CTRLA_MODE_SHIFT)
|
||||
# define TC_CTRLA_MODE_COUNT8 (1 << TC_CTRLA_MODE_SHIFT)
|
||||
# define TC_CTRLA_MODE_COUNT32 (2 << TC_CTRLA_MODE_SHIFT)
|
||||
#define TC_CTRLA_WAVEGEN_SHIFT (5)
|
||||
#define TC_CTRLA_WAVEGEN_MASK (3 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
# define TC_CTRLA_WAVEGEN_NFRQ (0 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
# define TC_CTRLA_WAVEGEN_MFRQ (1 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
# define TC_CTRLA_WAVEGEN_NPWM (2 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
# define TC_CTRLA_WAVEGEN_MPWM (3 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
#define TC_CTRLA_PRESCALER_SHIFT (8)
|
||||
#define TC_CTRLA_PRESCALER_MASK (7 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV1 (0 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV2 (1 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV4 (2 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV8 (3 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV16 (4 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV64 (5 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV256 (6 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV1024 (7 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
#define TC_CTRLA_RUNSTDBY (1 << 11)
|
||||
#define TC_CTRLA_PRESCSYNC_SHIFT (12)
|
||||
#define TC_CTRLA_PRESCSYNC_MASK (3 << TC_CTRLA_PRESCSYNC_SHIFT)
|
||||
# define TC_CTRLA_PRESCSYNC_GCLK (0 << TC_CTRLA_PRESCSYNC_SHIFT)
|
||||
# define TC_CTRLA_PRESCSYNC_PRESC (1 << TC_CTRLA_PRESCSYNC_SHIFT)
|
||||
# define TC_CTRLA_PRESCSYNC_RESYNC (2 << TC_CTRLA_PRESCSYNC_SHIFT)
|
||||
|
||||
/* Read Request register */
|
||||
|
||||
#define TC_READREQ_ADDR_SHIFT (0)
|
||||
#define TC_READREQ_ADDR_MASK (0x1F << TC_READREQ_ADDR_SHIFT)
|
||||
#define TC_READREQ_RCONT (1 << 14)
|
||||
#define TC_READREQ_RREQ (1 << 15)
|
||||
|
||||
/* Control B Set/Clear register */
|
||||
|
||||
#define TC_CTRLB_DIR (1 << 0)
|
||||
#define TC_CTRLB_ONESHOT (1 << 2)
|
||||
#define TC_CTRLB_CMD_SHIFT (6)
|
||||
#define TC_CTRLB_CMD_MASK (3 << TC_CTRLBCLR_CMD_SHIFT)
|
||||
# define TC_CTRLB_CMD_NONE (0 << TC_CTRLBCLR_CMD_SHIFT)
|
||||
# define TC_CTRLB_CMD_RETRIGGER (1 << TC_CTRLBCLR_CMD_SHIFT)
|
||||
# define TC_CTRLB_CMD_STOP (2 << TC_CTRLBCLR_CMD_SHIFT)
|
||||
|
||||
/* Control C register */
|
||||
|
||||
#define TC_CTRLC_INVEN0 (1 << 0)
|
||||
#define TC_CTRLC_INVEN1 (1 << 1)
|
||||
#define TC_CTRLC_CPTEN0 (1 << 4)
|
||||
#define TC_CTRLC_CPTEN1 (1 << 5)
|
||||
|
||||
/* Debug control register */
|
||||
|
||||
#define TC_DBGCTRL_DBGRUN (1 << 0)
|
||||
|
||||
/* Event control register */
|
||||
|
||||
#define TC_EVCTRL_EVACT_SHIFT (0)
|
||||
#define TC_EVCTRL_EVACT_MASK (7 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_OFF (0 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_RETRIGGER (1 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_COUNT (2 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_START (3 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_PPW (5 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_PWP (6 << TC_EVCTRL_EVACT_SHIFT)
|
||||
#define TC_EVCTRL_TCINV (1 << 4)
|
||||
#define TC_EVCTRL_TCEI (1 << 5)
|
||||
#define TC_EVCTRL_OVFEO (1 << 8)
|
||||
#define TC_EVCTRL_MCEO0 (1 << 12)
|
||||
#define TC_EVCTRL_MCEO1 (1 << 13)
|
||||
|
||||
/* Interrupt register bits */
|
||||
|
||||
#define TC_INT_OVF (1 << 0)
|
||||
#define TC_INT_ERR (1 << 1)
|
||||
#define TC_INT_SYNCRDY (1 << 3)
|
||||
#define TC_INT_MC0 (1 << 4)
|
||||
#define TC_INT_MC1 (1 << 5)
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define TC_STATUS_STOP (1 << 3)
|
||||
#define TC_STATUS_SLAVE (1 << 4)
|
||||
#define TC_STATUS_SYNCBUSY (1 << 7)
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TC_H */
|
||||
77
arch/arm/src/samdl/sam_dac.h
Normal file
77
arch/arm/src/samdl/sam_dac.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/samdl/sam_dac.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Matt Thompson <matt@extent3d.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMDL_SAM_DAC_H
|
||||
#define __ARCH_ARM_SRC_SAMDL_SAM_DAC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "sam_config.h"
|
||||
#include "sam_port.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
|
||||
# include "chip/samd_dac.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
|
||||
# include "chip/saml_dac.h"
|
||||
#else
|
||||
# error Unrecognized SAMD/L architecture
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_SAM_DAC_H */
|
||||
76
arch/arm/src/samdl/sam_evsys.h
Normal file
76
arch/arm/src/samdl/sam_evsys.h
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/samdl/sam_evsys.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Matt Thompson <matt@extent3d.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMDL_SAM_EVSYS_H
|
||||
#define __ARCH_ARM_SRC_SAMDL_SAM_EVSYS_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "sam_config.h"
|
||||
#include "sam_port.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
|
||||
# include "chip/samd_evsys.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
|
||||
# include "chip/saml_evsys.h"
|
||||
#else
|
||||
# error Unrecognized SAMD/L architecture
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_SAM_EVSYS_H */
|
||||
|
|
@ -75,7 +75,7 @@
|
|||
#define sam_apbc_enableperiph(s) modifyreg32(SAM_PM_APBCMASK,0,s)
|
||||
|
||||
#define sam_pac2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PAC2)
|
||||
#define sam_devsys_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_EVSYS)
|
||||
#define sam_evsys_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_EVSYS)
|
||||
#define sam_sercom_enableperiph(n) sam_apbc_enableperiph(PM_APBCMASK_SERCOM(n))
|
||||
#define sam_sercom0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM0)
|
||||
#define sam_sercom1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM1)
|
||||
|
|
@ -135,7 +135,7 @@
|
|||
#define sam_apbc_disableperiph(s) modifyreg32(SAM_PM_APBCMASK,s,0)
|
||||
|
||||
#define sam_pac2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PAC2)
|
||||
#define sam_devsys_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_EVSYS)
|
||||
#define sam_evsys_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_EVSYS)
|
||||
#define sam_sercom_disableperiph(n) sam_apbc_disableperiph(PM_APBCMASK_SERCOM(n))
|
||||
#define sam_sercom0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM0)
|
||||
#define sam_sercom1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM1)
|
||||
|
|
@ -195,7 +195,7 @@
|
|||
#define sam_apbc_isenabled(s) (getreg32(SAM_PM_APBCMASK) & (s)) != 0)
|
||||
|
||||
#define sam_pac2_isenabled() sam_apbc_isenabled(PM_APBCMASK_PAC2)
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#define sam_devsys_isenabled() sam_apbc_isenabled(PM_APBCMASK_EVSYS)
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#define sam_evsys_isenabled() sam_apbc_isenabled(PM_APBCMASK_EVSYS)
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#define sam_sercom_isenabled(n) sam_apbc_isenabled(PM_APBCMASK_SERCOM(n))
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#define sam_sercom0_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM0)
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#define sam_sercom1_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM1)
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||||
|
|
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Loading…
Add table
Reference in a new issue