diff --git a/arch/Kconfig b/arch/Kconfig index 12701b9952..e0eb9f4d7f 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -327,9 +327,6 @@ config ARCH_HAVE_DPFPU default n select ARCH_HAVE_FPU -config ARCH_HAVE_LAZYFPU - bool - config ARCH_HAVE_MMU bool default n diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ef0b98cea2..653d063920 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -607,7 +607,6 @@ config ARCH_CORTEXM3 select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_RAMVECTORS - select ARCH_HAVE_LAZYFPU select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET @@ -624,7 +623,6 @@ config ARCH_CORTEXM4 select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_RAMVECTORS - select ARCH_HAVE_LAZYFPU select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET @@ -642,7 +640,6 @@ config ARCH_CORTEXM7 select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_RAMVECTORS - select ARCH_HAVE_LAZYFPU select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET @@ -739,7 +736,6 @@ config ARCH_CORTEXM23 select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_RAMVECTORS - select ARCH_HAVE_LAZYFPU select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET @@ -753,7 +749,6 @@ config ARCH_CORTEXM33 select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_RAMVECTORS - select ARCH_HAVE_LAZYFPU select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET @@ -771,7 +766,6 @@ config ARCH_CORTEXM35P select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_RAMVECTORS - select ARCH_HAVE_LAZYFPU select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET @@ -789,7 +783,6 @@ config ARCH_CORTEXM55 select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQTRIGGER select ARCH_HAVE_RAMVECTORS - select ARCH_HAVE_LAZYFPU select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h index ece05c61c7..6219bb888b 100644 --- a/arch/arm/include/armv7-m/irq.h +++ b/arch/arm/include/armv7-m/irq.h @@ -38,14 +38,6 @@ # include #endif -/* Included implementation-dependent register save structure layouts */ - -#ifndef CONFIG_ARMV7M_LAZYFPU -# include -#else -# include -#endif - /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ @@ -60,6 +52,110 @@ # define CONFIG_SYS_NNEST 2 #endif +/* IRQ Stack Frame Format: */ + +/* The following additional registers are stored by the interrupt handling + * logic. + */ + +#define REG_R13 (0) /* R13 = SP at time of interrupt */ +#ifdef CONFIG_ARMV7M_USEBASEPRI +# define REG_BASEPRI (1) /* BASEPRI */ +#else +# define REG_PRIMASK (1) /* PRIMASK */ +#endif +#define REG_R4 (2) /* R4 */ +#define REG_R5 (3) /* R5 */ +#define REG_R6 (4) /* R6 */ +#define REG_R7 (5) /* R7 */ +#define REG_R8 (6) /* R8 */ +#define REG_R9 (7) /* R9 */ +#define REG_R10 (8) /* R10 */ +#define REG_R11 (9) /* R11 */ +#define REG_EXC_RETURN (10) /* EXC_RETURN */ +#define SW_INT_REGS (11) + +#ifdef CONFIG_ARCH_FPU + +/* If the MCU supports a floating point unit, then it will be necessary + * to save the state of the non-volatile registers before calling code + * that may save and overwrite them. + */ + +# define REG_S16 (SW_INT_REGS + 0) /* S16 */ +# define REG_S17 (SW_INT_REGS + 1) /* S17 */ +# define REG_S18 (SW_INT_REGS + 2) /* S18 */ +# define REG_S19 (SW_INT_REGS + 3) /* S19 */ +# define REG_S20 (SW_INT_REGS + 4) /* S20 */ +# define REG_S21 (SW_INT_REGS + 5) /* S21 */ +# define REG_S22 (SW_INT_REGS + 6) /* S22 */ +# define REG_S23 (SW_INT_REGS + 7) /* S23 */ +# define REG_S24 (SW_INT_REGS + 8) /* S24 */ +# define REG_S25 (SW_INT_REGS + 9) /* S25 */ +# define REG_S26 (SW_INT_REGS + 10) /* S26 */ +# define REG_S27 (SW_INT_REGS + 11) /* S27 */ +# define REG_S28 (SW_INT_REGS + 12) /* S28 */ +# define REG_S29 (SW_INT_REGS + 13) /* S29 */ +# define REG_S30 (SW_INT_REGS + 14) /* S30 */ +# define REG_S31 (SW_INT_REGS + 15) /* S31 */ +# define SW_FPU_REGS (16) +#else +# define SW_FPU_REGS (0) +#endif + +/* The total number of registers saved by software */ + +#define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS) +#define SW_XCPT_SIZE (4 * SW_XCPT_REGS) + +/* On entry into an IRQ, the hardware automatically saves the following + * registers on the stack in this (address) order: + */ + +#define REG_R0 (SW_XCPT_REGS + 0) /* R0 */ +#define REG_R1 (SW_XCPT_REGS + 1) /* R1 */ +#define REG_R2 (SW_XCPT_REGS + 2) /* R2 */ +#define REG_R3 (SW_XCPT_REGS + 3) /* R3 */ +#define REG_R12 (SW_XCPT_REGS + 4) /* R12 */ +#define REG_R14 (SW_XCPT_REGS + 5) /* R14 = LR */ +#define REG_R15 (SW_XCPT_REGS + 6) /* R15 = PC */ +#define REG_XPSR (SW_XCPT_REGS + 7) /* xPSR */ +#define HW_INT_REGS (8) + +#ifdef CONFIG_ARCH_FPU + +/* If the FPU is enabled, the hardware also saves the volatile FP registers. + */ + +# define REG_S0 (SW_XCPT_REGS + 8) /* S0 */ +# define REG_S1 (SW_XCPT_REGS + 9) /* S1 */ +# define REG_S2 (SW_XCPT_REGS + 10) /* S2 */ +# define REG_S3 (SW_XCPT_REGS + 11) /* S3 */ +# define REG_S4 (SW_XCPT_REGS + 12) /* S4 */ +# define REG_S5 (SW_XCPT_REGS + 13) /* S5 */ +# define REG_S6 (SW_XCPT_REGS + 14) /* S6 */ +# define REG_S7 (SW_XCPT_REGS + 15) /* S7 */ +# define REG_S8 (SW_XCPT_REGS + 16) /* S8 */ +# define REG_S9 (SW_XCPT_REGS + 17) /* S9 */ +# define REG_S10 (SW_XCPT_REGS + 18) /* S10 */ +# define REG_S11 (SW_XCPT_REGS + 19) /* S11 */ +# define REG_S12 (SW_XCPT_REGS + 20) /* S12 */ +# define REG_S13 (SW_XCPT_REGS + 21) /* S13 */ +# define REG_S14 (SW_XCPT_REGS + 22) /* S14 */ +# define REG_S15 (SW_XCPT_REGS + 23) /* S15 */ +# define REG_FPSCR (SW_XCPT_REGS + 24) /* FPSCR */ +# define REG_FP_RESERVED (SW_XCPT_REGS + 25) /* Reserved */ +# define HW_FPU_REGS (18) +#else +# define HW_FPU_REGS (0) +#endif + +#define HW_XCPT_REGS (HW_INT_REGS + HW_FPU_REGS) +#define HW_XCPT_SIZE (4 * HW_XCPT_REGS) + +#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS) +#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) + /* Alternate register names *************************************************/ #define REG_A1 REG_R0 diff --git a/arch/arm/include/armv7-m/irq_cmnvector.h b/arch/arm/include/armv7-m/irq_cmnvector.h deleted file mode 100644 index 4c923e3d83..0000000000 --- a/arch/arm/include/armv7-m/irq_cmnvector.h +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** - * arch/arm/include/armv7-m/irq_cmnvector.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_CMNVECTOR_H -#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_CMNVECTOR_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ Stack Frame Format: */ - -/* The following additional registers are stored by the interrupt handling - * logic. - */ - -#define REG_R13 (0) /* R13 = SP at time of interrupt */ -#ifdef CONFIG_ARMV7M_USEBASEPRI -# define REG_BASEPRI (1) /* BASEPRI */ -#else -# define REG_PRIMASK (1) /* PRIMASK */ -#endif -#define REG_R4 (2) /* R4 */ -#define REG_R5 (3) /* R5 */ -#define REG_R6 (4) /* R6 */ -#define REG_R7 (5) /* R7 */ -#define REG_R8 (6) /* R8 */ -#define REG_R9 (7) /* R9 */ -#define REG_R10 (8) /* R10 */ -#define REG_R11 (9) /* R11 */ -#define REG_EXC_RETURN (10) /* EXC_RETURN */ -#define SW_INT_REGS (11) - -#ifdef CONFIG_ARCH_FPU - -/* If the MCU supports a floating point unit, then it will be necessary - * to save the state of the non-volatile registers before calling code - * that may save and overwrite them. - */ - -# define REG_S16 (SW_INT_REGS + 0) /* S16 */ -# define REG_S17 (SW_INT_REGS + 1) /* S17 */ -# define REG_S18 (SW_INT_REGS + 2) /* S18 */ -# define REG_S19 (SW_INT_REGS + 3) /* S19 */ -# define REG_S20 (SW_INT_REGS + 4) /* S20 */ -# define REG_S21 (SW_INT_REGS + 5) /* S21 */ -# define REG_S22 (SW_INT_REGS + 6) /* S22 */ -# define REG_S23 (SW_INT_REGS + 7) /* S23 */ -# define REG_S24 (SW_INT_REGS + 8) /* S24 */ -# define REG_S25 (SW_INT_REGS + 9) /* S25 */ -# define REG_S26 (SW_INT_REGS + 10) /* S26 */ -# define REG_S27 (SW_INT_REGS + 11) /* S27 */ -# define REG_S28 (SW_INT_REGS + 12) /* S28 */ -# define REG_S29 (SW_INT_REGS + 13) /* S29 */ -# define REG_S30 (SW_INT_REGS + 14) /* S30 */ -# define REG_S31 (SW_INT_REGS + 15) /* S31 */ -# define SW_FPU_REGS (16) -#else -# define SW_FPU_REGS (0) -#endif - -/* The total number of registers saved by software */ - -#define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS) -#define SW_XCPT_SIZE (4 * SW_XCPT_REGS) - -/* On entry into an IRQ, the hardware automatically saves the following - * registers on the stack in this (address) order: - */ - -#define REG_R0 (SW_XCPT_REGS + 0) /* R0 */ -#define REG_R1 (SW_XCPT_REGS + 1) /* R1 */ -#define REG_R2 (SW_XCPT_REGS + 2) /* R2 */ -#define REG_R3 (SW_XCPT_REGS + 3) /* R3 */ -#define REG_R12 (SW_XCPT_REGS + 4) /* R12 */ -#define REG_R14 (SW_XCPT_REGS + 5) /* R14 = LR */ -#define REG_R15 (SW_XCPT_REGS + 6) /* R15 = PC */ -#define REG_XPSR (SW_XCPT_REGS + 7) /* xPSR */ -#define HW_INT_REGS (8) - -#ifdef CONFIG_ARCH_FPU - -/* If the FPU is enabled, the hardware also saves the volatile FP registers. - */ - -# define REG_S0 (SW_XCPT_REGS + 8) /* S0 */ -# define REG_S1 (SW_XCPT_REGS + 9) /* S1 */ -# define REG_S2 (SW_XCPT_REGS + 10) /* S2 */ -# define REG_S3 (SW_XCPT_REGS + 11) /* S3 */ -# define REG_S4 (SW_XCPT_REGS + 12) /* S4 */ -# define REG_S5 (SW_XCPT_REGS + 13) /* S5 */ -# define REG_S6 (SW_XCPT_REGS + 14) /* S6 */ -# define REG_S7 (SW_XCPT_REGS + 15) /* S7 */ -# define REG_S8 (SW_XCPT_REGS + 16) /* S8 */ -# define REG_S9 (SW_XCPT_REGS + 17) /* S9 */ -# define REG_S10 (SW_XCPT_REGS + 18) /* S10 */ -# define REG_S11 (SW_XCPT_REGS + 19) /* S11 */ -# define REG_S12 (SW_XCPT_REGS + 20) /* S12 */ -# define REG_S13 (SW_XCPT_REGS + 21) /* S13 */ -# define REG_S14 (SW_XCPT_REGS + 22) /* S14 */ -# define REG_S15 (SW_XCPT_REGS + 23) /* S15 */ -# define REG_FPSCR (SW_XCPT_REGS + 24) /* FPSCR */ -# define REG_FP_RESERVED (SW_XCPT_REGS + 25) /* Reserved */ -# define HW_FPU_REGS (18) -#else -# define HW_FPU_REGS (0) -#endif - -#define HW_XCPT_REGS (HW_INT_REGS + HW_FPU_REGS) -#define HW_XCPT_SIZE (4 * HW_XCPT_REGS) - -#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS) -#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) - -#define FPU_CONTEXT_REGS SW_FPU_REGS - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_CMNVECTOR_H */ diff --git a/arch/arm/include/armv7-m/irq_lazyfpu.h b/arch/arm/include/armv7-m/irq_lazyfpu.h deleted file mode 100644 index 0b2b2611e0..0000000000 --- a/arch/arm/include/armv7-m/irq_lazyfpu.h +++ /dev/null @@ -1,172 +0,0 @@ -/**************************************************************************** - * arch/arm/include/armv7-m/irq_lazyfpu.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H -#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ Stack Frame Format: */ - -/* The following additional registers are stored by the interrupt handling - * logic. - */ - -#define REG_R13 (0) /* R13 = SP at time of interrupt */ -#ifdef CONFIG_ARMV7M_USEBASEPRI -# define REG_BASEPRI (1) /* BASEPRI */ -#else -# define REG_PRIMASK (1) /* PRIMASK */ -#endif -#define REG_R4 (2) /* R4 */ -#define REG_R5 (3) /* R5 */ -#define REG_R6 (4) /* R6 */ -#define REG_R7 (5) /* R7 */ -#define REG_R8 (6) /* R8 */ -#define REG_R9 (7) /* R9 */ -#define REG_R10 (8) /* R10 */ -#define REG_R11 (9) /* R11 */ - -#ifdef CONFIG_BUILD_PROTECTED -# define REG_EXC_RETURN (10) /* EXC_RETURN */ -# define SW_INT_REGS (11) -#else -# define SW_INT_REGS (10) -#endif - -/* If the MCU supports a floating point unit, then it will be necessary - * to save the state of the FPU status register and data registers on - * each context switch. These registers are not saved during interrupt - * level processing, however. So, as a consequence, floating point - * operations may NOT be performed in interrupt handlers. - * - * The FPU provides an extension register file containing 32 single- - * precision registers. These can be viewed as: - * - * - Sixteen 64-bit doubleword registers, D0-D15 - * - Thirty-two 32-bit single-word registers, S0-S31 - * S<2n> maps to the least significant half of D - * S<2n+1> maps to the most significant half of D. - */ - -#ifdef CONFIG_ARCH_FPU -# define REG_D0 (SW_INT_REGS+0) /* D0 */ -# define REG_S0 (SW_INT_REGS+0) /* S0 */ -# define REG_S1 (SW_INT_REGS+1) /* S1 */ -# define REG_D1 (SW_INT_REGS+2) /* D1 */ -# define REG_S2 (SW_INT_REGS+2) /* S2 */ -# define REG_S3 (SW_INT_REGS+3) /* S3 */ -# define REG_D2 (SW_INT_REGS+4) /* D2 */ -# define REG_S4 (SW_INT_REGS+4) /* S4 */ -# define REG_S5 (SW_INT_REGS+5) /* S5 */ -# define REG_D3 (SW_INT_REGS+6) /* D3 */ -# define REG_S6 (SW_INT_REGS+6) /* S6 */ -# define REG_S7 (SW_INT_REGS+7) /* S7 */ -# define REG_D4 (SW_INT_REGS+8) /* D4 */ -# define REG_S8 (SW_INT_REGS+8) /* S8 */ -# define REG_S9 (SW_INT_REGS+9) /* S9 */ -# define REG_D5 (SW_INT_REGS+10) /* D5 */ -# define REG_S10 (SW_INT_REGS+10) /* S10 */ -# define REG_S11 (SW_INT_REGS+11) /* S11 */ -# define REG_D6 (SW_INT_REGS+12) /* D6 */ -# define REG_S12 (SW_INT_REGS+12) /* S12 */ -# define REG_S13 (SW_INT_REGS+13) /* S13 */ -# define REG_D7 (SW_INT_REGS+14) /* D7 */ -# define REG_S14 (SW_INT_REGS+14) /* S14 */ -# define REG_S15 (SW_INT_REGS+15) /* S15 */ -# define REG_D8 (SW_INT_REGS+16) /* D8 */ -# define REG_S16 (SW_INT_REGS+16) /* S16 */ -# define REG_S17 (SW_INT_REGS+17) /* S17 */ -# define REG_D9 (SW_INT_REGS+18) /* D9 */ -# define REG_S18 (SW_INT_REGS+18) /* S18 */ -# define REG_S19 (SW_INT_REGS+19) /* S19 */ -# define REG_D10 (SW_INT_REGS+20) /* D10 */ -# define REG_S20 (SW_INT_REGS+20) /* S20 */ -# define REG_S21 (SW_INT_REGS+21) /* S21 */ -# define REG_D11 (SW_INT_REGS+22) /* D11 */ -# define REG_S22 (SW_INT_REGS+22) /* S22 */ -# define REG_S23 (SW_INT_REGS+23) /* S23 */ -# define REG_D12 (SW_INT_REGS+24) /* D12 */ -# define REG_S24 (SW_INT_REGS+24) /* S24 */ -# define REG_S25 (SW_INT_REGS+25) /* S25 */ -# define REG_D13 (SW_INT_REGS+26) /* D13 */ -# define REG_S26 (SW_INT_REGS+26) /* S26 */ -# define REG_S27 (SW_INT_REGS+27) /* S27 */ -# define REG_D14 (SW_INT_REGS+28) /* D14 */ -# define REG_S28 (SW_INT_REGS+28) /* S28 */ -# define REG_S29 (SW_INT_REGS+29) /* S29 */ -# define REG_D15 (SW_INT_REGS+30) /* D15 */ -# define REG_S30 (SW_INT_REGS+30) /* S30 */ -# define REG_S31 (SW_INT_REGS+31) /* S31 */ -# define REG_FPSCR (SW_INT_REGS+32) /* Floating point status and control */ -# define SW_FPU_REGS (33) -#else -# define SW_FPU_REGS (0) -#endif - -/* The total number of registers saved by software */ - -#define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS) -#define SW_XCPT_SIZE (4 * SW_XCPT_REGS) - -/* On entry into an IRQ, the hardware automatically saves the following - * registers on the stack in this (address) order: - */ - -#define REG_R0 (SW_XCPT_REGS+0) /* R0 */ -#define REG_R1 (SW_XCPT_REGS+1) /* R1 */ -#define REG_R2 (SW_XCPT_REGS+2) /* R2 */ -#define REG_R3 (SW_XCPT_REGS+3) /* R3 */ -#define REG_R12 (SW_XCPT_REGS+4) /* R12 */ -#define REG_R14 (SW_XCPT_REGS+5) /* R14 = LR */ -#define REG_R15 (SW_XCPT_REGS+6) /* R15 = PC */ -#define REG_XPSR (SW_XCPT_REGS+7) /* xPSR */ - -#define HW_XCPT_REGS (8) -#define HW_XCPT_SIZE (4 * HW_XCPT_REGS) - -#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS) -#define XCPTCONTEXT_SIZE (HW_XCPT_SIZE + SW_XCPT_SIZE) - -#define FPU_CONTEXT_REGS SW_FPU_REGS - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H */ diff --git a/arch/arm/include/armv8-m/irq.h b/arch/arm/include/armv8-m/irq.h index 62ff2b73d4..4874dbd032 100644 --- a/arch/arm/include/armv8-m/irq.h +++ b/arch/arm/include/armv8-m/irq.h @@ -38,14 +38,6 @@ # include #endif -/* Included implementation-dependent register save structure layouts */ - -#ifndef CONFIG_ARMV8M_LAZYFPU -# include -#else -# include -#endif - /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ @@ -60,6 +52,116 @@ # define CONFIG_SYS_NNEST 2 #endif +/* IRQ Stack Frame Format: */ + +/* The following additional registers are stored by the interrupt handling + * logic. + */ + +#define REG_R13 (0) /* R13 = SP at time of interrupt */ +#ifdef CONFIG_ARMV8M_USEBASEPRI +# define REG_BASEPRI (1) /* BASEPRI */ +#else +# define REG_PRIMASK (1) /* PRIMASK */ +#endif +#define REG_R4 (2) /* R4 */ +#define REG_R5 (3) /* R5 */ +#define REG_R6 (4) /* R6 */ +#define REG_R7 (5) /* R7 */ +#define REG_R8 (6) /* R8 */ +#define REG_R9 (7) /* R9 */ +#define REG_R10 (8) /* R10 */ +#define REG_R11 (9) /* R11 */ +#define REG_EXC_RETURN (10) /* EXC_RETURN */ +#define SW_INT_REGS (11) + +#ifdef CONFIG_ARCH_FPU + +/* If the MCU supports a floating point unit, then it will be necessary + * to save the state of the non-volatile registers before calling code + * that may save and overwrite them. + */ + +# define REG_S16 (SW_INT_REGS + 0) /* S16 */ +# define REG_S17 (SW_INT_REGS + 1) /* S17 */ +# define REG_S18 (SW_INT_REGS + 2) /* S18 */ +# define REG_S19 (SW_INT_REGS + 3) /* S19 */ +# define REG_S20 (SW_INT_REGS + 4) /* S20 */ +# define REG_S21 (SW_INT_REGS + 5) /* S21 */ +# define REG_S22 (SW_INT_REGS + 6) /* S22 */ +# define REG_S23 (SW_INT_REGS + 7) /* S23 */ +# define REG_S24 (SW_INT_REGS + 8) /* S24 */ +# define REG_S25 (SW_INT_REGS + 9) /* S25 */ +# define REG_S26 (SW_INT_REGS + 10) /* S26 */ +# define REG_S27 (SW_INT_REGS + 11) /* S27 */ +# define REG_S28 (SW_INT_REGS + 12) /* S28 */ +# define REG_S29 (SW_INT_REGS + 13) /* S29 */ +# define REG_S30 (SW_INT_REGS + 14) /* S30 */ +# define REG_S31 (SW_INT_REGS + 15) /* S31 */ +# define SW_FPU_REGS (16) +#else +# define SW_FPU_REGS (0) +#endif + +/* The total number of registers saved by software */ + +#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE +# define REG_SPLIM (SW_INT_REGS + SW_FPU_REGS + 0) /* REG_SPLIM */ +# define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS + 1) +#else +# define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS) +#endif + +#define SW_XCPT_SIZE (4 * SW_XCPT_REGS) + +/* On entry into an IRQ, the hardware automatically saves the following + * registers on the stack in this (address) order: + */ + +#define REG_R0 (SW_XCPT_REGS + 0) /* R0 */ +#define REG_R1 (SW_XCPT_REGS + 1) /* R1 */ +#define REG_R2 (SW_XCPT_REGS + 2) /* R2 */ +#define REG_R3 (SW_XCPT_REGS + 3) /* R3 */ +#define REG_R12 (SW_XCPT_REGS + 4) /* R12 */ +#define REG_R14 (SW_XCPT_REGS + 5) /* R14 = LR */ +#define REG_R15 (SW_XCPT_REGS + 6) /* R15 = PC */ +#define REG_XPSR (SW_XCPT_REGS + 7) /* xPSR */ +#define HW_INT_REGS (8) + +#ifdef CONFIG_ARCH_FPU + +/* If the FPU is enabled, the hardware also saves the volatile FP registers. + */ + +# define REG_S0 (SW_XCPT_REGS + 8) /* S0 */ +# define REG_S1 (SW_XCPT_REGS + 9) /* S1 */ +# define REG_S2 (SW_XCPT_REGS + 10) /* S2 */ +# define REG_S3 (SW_XCPT_REGS + 11) /* S3 */ +# define REG_S4 (SW_XCPT_REGS + 12) /* S4 */ +# define REG_S5 (SW_XCPT_REGS + 13) /* S5 */ +# define REG_S6 (SW_XCPT_REGS + 14) /* S6 */ +# define REG_S7 (SW_XCPT_REGS + 15) /* S7 */ +# define REG_S8 (SW_XCPT_REGS + 16) /* S8 */ +# define REG_S9 (SW_XCPT_REGS + 17) /* S9 */ +# define REG_S10 (SW_XCPT_REGS + 18) /* S10 */ +# define REG_S11 (SW_XCPT_REGS + 19) /* S11 */ +# define REG_S12 (SW_XCPT_REGS + 20) /* S12 */ +# define REG_S13 (SW_XCPT_REGS + 21) /* S13 */ +# define REG_S14 (SW_XCPT_REGS + 22) /* S14 */ +# define REG_S15 (SW_XCPT_REGS + 23) /* S15 */ +# define REG_FPSCR (SW_XCPT_REGS + 24) /* FPSCR */ +# define REG_FP_RESERVED (SW_XCPT_REGS + 25) /* Reserved */ +# define HW_FPU_REGS (18) +#else +# define HW_FPU_REGS (0) +#endif + +#define HW_XCPT_REGS (HW_INT_REGS + HW_FPU_REGS) +#define HW_XCPT_SIZE (4 * HW_XCPT_REGS) + +#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS) +#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) + /* Alternate register names *************************************************/ #define REG_A1 REG_R0 diff --git a/arch/arm/include/armv8-m/irq_cmnvector.h b/arch/arm/include/armv8-m/irq_cmnvector.h deleted file mode 100644 index c64467689f..0000000000 --- a/arch/arm/include/armv8-m/irq_cmnvector.h +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * arch/arm/include/armv8-m/irq_cmnvector.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_ARMV8_M_IRQ_CMNVECTOR_H -#define __ARCH_ARM_INCLUDE_ARMV8_M_IRQ_CMNVECTOR_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ Stack Frame Format: */ - -/* The following additional registers are stored by the interrupt handling - * logic. - */ - -#define REG_R13 (0) /* R13 = SP at time of interrupt */ -#ifdef CONFIG_ARMV8M_USEBASEPRI -# define REG_BASEPRI (1) /* BASEPRI */ -#else -# define REG_PRIMASK (1) /* PRIMASK */ -#endif -#define REG_R4 (2) /* R4 */ -#define REG_R5 (3) /* R5 */ -#define REG_R6 (4) /* R6 */ -#define REG_R7 (5) /* R7 */ -#define REG_R8 (6) /* R8 */ -#define REG_R9 (7) /* R9 */ -#define REG_R10 (8) /* R10 */ -#define REG_R11 (9) /* R11 */ -#define REG_EXC_RETURN (10) /* EXC_RETURN */ -#define SW_INT_REGS (11) - -#ifdef CONFIG_ARCH_FPU - -/* If the MCU supports a floating point unit, then it will be necessary - * to save the state of the non-volatile registers before calling code - * that may save and overwrite them. - */ - -# define REG_S16 (SW_INT_REGS + 0) /* S16 */ -# define REG_S17 (SW_INT_REGS + 1) /* S17 */ -# define REG_S18 (SW_INT_REGS + 2) /* S18 */ -# define REG_S19 (SW_INT_REGS + 3) /* S19 */ -# define REG_S20 (SW_INT_REGS + 4) /* S20 */ -# define REG_S21 (SW_INT_REGS + 5) /* S21 */ -# define REG_S22 (SW_INT_REGS + 6) /* S22 */ -# define REG_S23 (SW_INT_REGS + 7) /* S23 */ -# define REG_S24 (SW_INT_REGS + 8) /* S24 */ -# define REG_S25 (SW_INT_REGS + 9) /* S25 */ -# define REG_S26 (SW_INT_REGS + 10) /* S26 */ -# define REG_S27 (SW_INT_REGS + 11) /* S27 */ -# define REG_S28 (SW_INT_REGS + 12) /* S28 */ -# define REG_S29 (SW_INT_REGS + 13) /* S29 */ -# define REG_S30 (SW_INT_REGS + 14) /* S30 */ -# define REG_S31 (SW_INT_REGS + 15) /* S31 */ -# define SW_FPU_REGS (16) -#else -# define SW_FPU_REGS (0) -#endif - -/* The total number of registers saved by software */ - -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE -# define REG_SPLIM (SW_INT_REGS + SW_FPU_REGS + 0) /* REG_SPLIM */ -# define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS + 1) -#else -# define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS) -#endif - -#define SW_XCPT_SIZE (4 * SW_XCPT_REGS) - -/* On entry into an IRQ, the hardware automatically saves the following - * registers on the stack in this (address) order: - */ - -#define REG_R0 (SW_XCPT_REGS + 0) /* R0 */ -#define REG_R1 (SW_XCPT_REGS + 1) /* R1 */ -#define REG_R2 (SW_XCPT_REGS + 2) /* R2 */ -#define REG_R3 (SW_XCPT_REGS + 3) /* R3 */ -#define REG_R12 (SW_XCPT_REGS + 4) /* R12 */ -#define REG_R14 (SW_XCPT_REGS + 5) /* R14 = LR */ -#define REG_R15 (SW_XCPT_REGS + 6) /* R15 = PC */ -#define REG_XPSR (SW_XCPT_REGS + 7) /* xPSR */ -#define HW_INT_REGS (8) - -#ifdef CONFIG_ARCH_FPU - -/* If the FPU is enabled, the hardware also saves the volatile FP registers. - */ - -# define REG_S0 (SW_XCPT_REGS + 8) /* S0 */ -# define REG_S1 (SW_XCPT_REGS + 9) /* S1 */ -# define REG_S2 (SW_XCPT_REGS + 10) /* S2 */ -# define REG_S3 (SW_XCPT_REGS + 11) /* S3 */ -# define REG_S4 (SW_XCPT_REGS + 12) /* S4 */ -# define REG_S5 (SW_XCPT_REGS + 13) /* S5 */ -# define REG_S6 (SW_XCPT_REGS + 14) /* S6 */ -# define REG_S7 (SW_XCPT_REGS + 15) /* S7 */ -# define REG_S8 (SW_XCPT_REGS + 16) /* S8 */ -# define REG_S9 (SW_XCPT_REGS + 17) /* S9 */ -# define REG_S10 (SW_XCPT_REGS + 18) /* S10 */ -# define REG_S11 (SW_XCPT_REGS + 19) /* S11 */ -# define REG_S12 (SW_XCPT_REGS + 20) /* S12 */ -# define REG_S13 (SW_XCPT_REGS + 21) /* S13 */ -# define REG_S14 (SW_XCPT_REGS + 22) /* S14 */ -# define REG_S15 (SW_XCPT_REGS + 23) /* S15 */ -# define REG_FPSCR (SW_XCPT_REGS + 24) /* FPSCR */ -# define REG_FP_RESERVED (SW_XCPT_REGS + 25) /* Reserved */ -# define HW_FPU_REGS (18) -#else -# define HW_FPU_REGS (0) -#endif - -#define HW_XCPT_REGS (HW_INT_REGS + HW_FPU_REGS) -#define HW_XCPT_SIZE (4 * HW_XCPT_REGS) - -#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS) -#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) - -#define FPU_CONTEXT_REGS SW_FPU_REGS - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_ARMV8_M_IRQ_CMNVECTOR_H */ diff --git a/arch/arm/include/armv8-m/irq_lazyfpu.h b/arch/arm/include/armv8-m/irq_lazyfpu.h deleted file mode 100644 index 5c159d6a45..0000000000 --- a/arch/arm/include/armv8-m/irq_lazyfpu.h +++ /dev/null @@ -1,178 +0,0 @@ -/**************************************************************************** - * arch/arm/include/armv8-m/irq_lazyfpu.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_ARMV8_M_IRQ_LAZYFPU_H -#define __ARCH_ARM_INCLUDE_ARMV8_M_IRQ_LAZYFPU_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ Stack Frame Format: */ - -/* The following additional registers are stored by the interrupt handling - * logic. - */ - -#define REG_R13 (0) /* R13 = SP at time of interrupt */ -#ifdef CONFIG_ARMV8M_USEBASEPRI -# define REG_BASEPRI (1) /* BASEPRI */ -#else -# define REG_PRIMASK (1) /* PRIMASK */ -#endif -#define REG_R4 (2) /* R4 */ -#define REG_R5 (3) /* R5 */ -#define REG_R6 (4) /* R6 */ -#define REG_R7 (5) /* R7 */ -#define REG_R8 (6) /* R8 */ -#define REG_R9 (7) /* R9 */ -#define REG_R10 (8) /* R10 */ -#define REG_R11 (9) /* R11 */ - -#ifdef CONFIG_BUILD_PROTECTED -# define REG_EXC_RETURN (10) /* EXC_RETURN */ -# define SW_INT_REGS (11) -#else -# define SW_INT_REGS (10) -#endif - -/* If the MCU supports a floating point unit, then it will be necessary - * to save the state of the FPU status register and data registers on - * each context switch. These registers are not saved during interrupt - * level processing, however. So, as a consequence, floating point - * operations may NOT be performed in interrupt handlers. - * - * The FPU provides an extension register file containing 32 single- - * precision registers. These can be viewed as: - * - * - Sixteen 64-bit doubleword registers, D0-D15 - * - Thirty-two 32-bit single-word registers, S0-S31 - * S<2n> maps to the least significant half of D - * S<2n+1> maps to the most significant half of D. - */ - -#ifdef CONFIG_ARCH_FPU -# define REG_D0 (SW_INT_REGS+0) /* D0 */ -# define REG_S0 (SW_INT_REGS+0) /* S0 */ -# define REG_S1 (SW_INT_REGS+1) /* S1 */ -# define REG_D1 (SW_INT_REGS+2) /* D1 */ -# define REG_S2 (SW_INT_REGS+2) /* S2 */ -# define REG_S3 (SW_INT_REGS+3) /* S3 */ -# define REG_D2 (SW_INT_REGS+4) /* D2 */ -# define REG_S4 (SW_INT_REGS+4) /* S4 */ -# define REG_S5 (SW_INT_REGS+5) /* S5 */ -# define REG_D3 (SW_INT_REGS+6) /* D3 */ -# define REG_S6 (SW_INT_REGS+6) /* S6 */ -# define REG_S7 (SW_INT_REGS+7) /* S7 */ -# define REG_D4 (SW_INT_REGS+8) /* D4 */ -# define REG_S8 (SW_INT_REGS+8) /* S8 */ -# define REG_S9 (SW_INT_REGS+9) /* S9 */ -# define REG_D5 (SW_INT_REGS+10) /* D5 */ -# define REG_S10 (SW_INT_REGS+10) /* S10 */ -# define REG_S11 (SW_INT_REGS+11) /* S11 */ -# define REG_D6 (SW_INT_REGS+12) /* D6 */ -# define REG_S12 (SW_INT_REGS+12) /* S12 */ -# define REG_S13 (SW_INT_REGS+13) /* S13 */ -# define REG_D7 (SW_INT_REGS+14) /* D7 */ -# define REG_S14 (SW_INT_REGS+14) /* S14 */ -# define REG_S15 (SW_INT_REGS+15) /* S15 */ -# define REG_D8 (SW_INT_REGS+16) /* D8 */ -# define REG_S16 (SW_INT_REGS+16) /* S16 */ -# define REG_S17 (SW_INT_REGS+17) /* S17 */ -# define REG_D9 (SW_INT_REGS+18) /* D9 */ -# define REG_S18 (SW_INT_REGS+18) /* S18 */ -# define REG_S19 (SW_INT_REGS+19) /* S19 */ -# define REG_D10 (SW_INT_REGS+20) /* D10 */ -# define REG_S20 (SW_INT_REGS+20) /* S20 */ -# define REG_S21 (SW_INT_REGS+21) /* S21 */ -# define REG_D11 (SW_INT_REGS+22) /* D11 */ -# define REG_S22 (SW_INT_REGS+22) /* S22 */ -# define REG_S23 (SW_INT_REGS+23) /* S23 */ -# define REG_D12 (SW_INT_REGS+24) /* D12 */ -# define REG_S24 (SW_INT_REGS+24) /* S24 */ -# define REG_S25 (SW_INT_REGS+25) /* S25 */ -# define REG_D13 (SW_INT_REGS+26) /* D13 */ -# define REG_S26 (SW_INT_REGS+26) /* S26 */ -# define REG_S27 (SW_INT_REGS+27) /* S27 */ -# define REG_D14 (SW_INT_REGS+28) /* D14 */ -# define REG_S28 (SW_INT_REGS+28) /* S28 */ -# define REG_S29 (SW_INT_REGS+29) /* S29 */ -# define REG_D15 (SW_INT_REGS+30) /* D15 */ -# define REG_S30 (SW_INT_REGS+30) /* S30 */ -# define REG_S31 (SW_INT_REGS+31) /* S31 */ -# define REG_FPSCR (SW_INT_REGS+32) /* Floating point status and control */ -# define SW_FPU_REGS (33) -#else -# define SW_FPU_REGS (0) -#endif - -/* The total number of registers saved by software */ - -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE -# define REG_SPLIM (SW_INT_REGS + SW_FPU_REGS + 0) /* REG_SPLIM */ -# define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS + 1) -#else -# define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS) -#endif - -#define SW_XCPT_SIZE (4 * SW_XCPT_REGS) - -/* On entry into an IRQ, the hardware automatically saves the following - * registers on the stack in this (address) order: - */ - -#define REG_R0 (SW_XCPT_REGS+0) /* R0 */ -#define REG_R1 (SW_XCPT_REGS+1) /* R1 */ -#define REG_R2 (SW_XCPT_REGS+2) /* R2 */ -#define REG_R3 (SW_XCPT_REGS+3) /* R3 */ -#define REG_R12 (SW_XCPT_REGS+4) /* R12 */ -#define REG_R14 (SW_XCPT_REGS+5) /* R14 = LR */ -#define REG_R15 (SW_XCPT_REGS+6) /* R15 = PC */ -#define REG_XPSR (SW_XCPT_REGS+7) /* xPSR */ - -#define HW_XCPT_REGS (8) -#define HW_XCPT_SIZE (4 * HW_XCPT_REGS) - -#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS) -#define XCPTCONTEXT_SIZE (HW_XCPT_SIZE + SW_XCPT_SIZE) - -#define FPU_CONTEXT_REGS SW_FPU_REGS - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_ARMV8_M_IRQ_LAZYFPU_H */ diff --git a/arch/arm/src/a1x/Make.defs b/arch/arm/src/a1x/Make.defs index 53c68204a1..2950115d95 100644 --- a/arch/arm/src/a1x/Make.defs +++ b/arch/arm/src/a1x/Make.defs @@ -60,7 +60,7 @@ CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_mmu.c arm_prefetchabort.c CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c arm_tcbinfo.c -CMN_CSRCS += arm_switchcontext.c +CMN_CSRCS += arm_switchcontext.c arm_cache.c # Use common heap allocation for now (may need to be customized later) @@ -101,10 +101,7 @@ CMN_CSRCS += arm_virtpgaddr.c endif endif -CMN_CSRCS += arm_cache.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/am335x/Make.defs b/arch/arm/src/am335x/Make.defs index 13bfad7d45..f565aaccca 100644 --- a/arch/arm/src/am335x/Make.defs +++ b/arch/arm/src/am335x/Make.defs @@ -60,7 +60,7 @@ CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_mmu.c arm_prefetchabort.c CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c arm_tcbinfo.c -CMN_CSRCS += arm_switchcontext.c +CMN_CSRCS += arm_switchcontext.c arm_cache.c # Use common heap allocation for now (may need to be customized later) @@ -97,10 +97,7 @@ CMN_CSRCS += arm_virtpgaddr.c endif endif -CMN_CSRCS += arm_cache.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/armv7-a/arm_restorefpu.S b/arch/arm/src/armv7-a/arm_restorefpu.S deleted file mode 100644 index 809d3c2a9b..0000000000 --- a/arch/arm/src/armv7-a/arm_restorefpu.S +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/arm_restorefpu.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#ifdef CONFIG_ARCH_FPU - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_restorefpu - .file "arm_restorefpu.S" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - - .text - -/**************************************************************************** - * Name: arm_restorefpu - * - * Description: - * Given the pointer to a register save area (in R0), restore the state of the - * floating point registers. - * - * C Function Prototype: - * void arm_restorefpu(const uint32_t *regs); - * - * Input Parameters: - * regs - A pointer to the register save area containing the floating point - * registers. - * - * Returned Value: - * This function does not return anything explicitly. However, it is called from - * interrupt level assembly logic that assumes that r0 is preserved. - * - ****************************************************************************/ - - .globl arm_restorefpu - .type arm_restorefpu, function - -arm_restorefpu: - - add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */ - - /* Load all floating point registers. Registers are loaded in numeric order, - * s0, s1, ... in increasing address order. - */ - -#ifdef CONFIG_ARM_DPFPU32 - vldmia.64 r1!, {d0-d15} /* Restore the full FP context */ - vldmia.64 r1!, {d16-d31} -#else - vldmia r1!, {s0-s31} /* Restore the full FP context */ -#endif - - /* Load the floating point control and status register. At the end of the - * vstmia, r1 will point to the FPSCR storage location. - */ - - ldr r2, [r1], #4 /* Fetch the floating point control and status register */ - vmsr fpscr, r2 /* Restore the FPSCR */ - bx lr - - .size arm_restorefpu, .-arm_restorefpu -#endif /* CONFIG_ARCH_FPU */ - .end diff --git a/arch/arm/src/armv7-a/arm_savefpu.S b/arch/arm/src/armv7-a/arm_savefpu.S deleted file mode 100644 index caf8e7e455..0000000000 --- a/arch/arm/src/armv7-a/arm_savefpu.S +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/arm_savefpu.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#ifdef CONFIG_ARCH_FPU - - .file "arm_savefpu.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_savefpu - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - - .text - -/**************************************************************************** - * Name: arm_savefpu - * - * Description: - * Given the pointer to a register save area (in R0), save the state of the - * floating point registers. - * - * C Function Prototype: - * void arm_savefpu(uint32_t *regs); - * - * Input Parameters: - * regs - A pointer to the register save area in which to save the floating point - * registers - * - * Returned Value: - * None - * - ****************************************************************************/ - - .globl arm_savefpu - .type arm_savefpu, function - -arm_savefpu: - - add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */ - - /* Store all floating point registers. Registers are stored in numeric order, - * s0, s1, ... in increasing address order. - */ - -#ifdef CONFIG_ARM_DPFPU32 - vstmia.64 r1!, {d0-d15} /* Save the full FP context */ - vstmia.64 r1!, {d16-d31} -#else - vstmia r1!, {s0-s31} /* Save the full FP context */ -#endif - - /* Store the floating point control and status register. At the end of the - * vstmia, r1 will point to the FPSCR storage location. - */ - - vmrs r2, fpscr /* Fetch the FPSCR */ - str r2, [r1], #4 /* Save the floating point control and status register */ - bx lr - - .size arm_savefpu, .-arm_savefpu -#endif /* CONFIG_ARCH_FPU */ - .end diff --git a/arch/arm/src/armv7-m/Kconfig b/arch/arm/src/armv7-m/Kconfig index 6625e37e1d..87c7c2297b 100644 --- a/arch/arm/src/armv7-m/Kconfig +++ b/arch/arm/src/armv7-m/Kconfig @@ -13,40 +13,6 @@ config ARMV7M_HAVE_DCACHE bool default n -config ARMV7M_LAZYFPU - bool "Lazy FPU storage" - default n - depends on ARCH_HAVE_LAZYFPU - ---help--- - There are two forms of the common vector logic. There are pros and - cons to each option: - - 1) The standard common vector logic exploits features of the ARMv7-M - architecture to save the all of floating registers on entry into - each interrupt and then to restore the floating registers when - the interrupt returns. The primary advantage to this approach is - that floating point operations are available in interrupt - handling logic. Since the volatile registers are preserved, - operations on the floating point registers by interrupt handling - logic has no ill effect. The downside is, of course, that more - stack operations are required on each interrupt to save and store - the floating point registers. Because of the some special - features of the ARMv-M, this is not as much overhead as you might - expect, but overhead nonetheless. - - 2) The lazy FPU common vector logic does not save or restore - floating point registers on entry and exit from the interrupt - handler. Rather, the floating point registers are not restored - until it is absolutely necessary to do so when a context switch - occurs and the interrupt handler will be returning to a different - floating point context. Since floating point registers are not - protected, floating point operations must not be performed in - interrupt handling logic. Better interrupt performance is be - expected, however. - - By default, the "standard" common vector logic is build. This - option selects the alternate lazy FPU common vector logic. - config ARMV7M_USEBASEPRI bool "Use BASEPRI Register" default y if ARCH_HIPRI_INTERRUPT diff --git a/arch/arm/src/armv7-m/arm_fpuconfig.c b/arch/arm/src/armv7-m/arm_fpuconfig.c index df676ee482..0bcdeb45c0 100644 --- a/arch/arm/src/armv7-m/arm_fpuconfig.c +++ b/arch/arm/src/armv7-m/arm_fpuconfig.c @@ -54,8 +54,6 @@ * ****************************************************************************/ -#ifndef CONFIG_ARMV7M_LAZYFPU - void arm_fpuconfig(void) { uint32_t regval; @@ -83,35 +81,3 @@ void arm_fpuconfig(void) regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11); putreg32(regval, NVIC_CPACR); } - -#else - -void arm_fpuconfig(void) -{ - uint32_t regval; - - /* Clear CONTROL.FPCA so that we do not get the extended context frame - * with the volatile FP registers stacked in the saved context. - */ - - regval = getcontrol(); - regval &= ~CONTROL_FPCA; - setcontrol(regval); - - /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend - * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we - * are going to keep CONTROL.FPCA off for all contexts. - */ - - regval = getreg32(NVIC_FPCCR); - regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN); - putreg32(regval, NVIC_FPCCR); - - /* Enable full access to CP10 and CP11 */ - - regval = getreg32(NVIC_CPACR); - regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11); - putreg32(regval, NVIC_CPACR); -} - -#endif diff --git a/arch/arm/src/armv7-m/arm_initialstate.c b/arch/arm/src/armv7-m/arm_initialstate.c index b913fc9611..f5af28e9ce 100644 --- a/arch/arm/src/armv7-m/arm_initialstate.c +++ b/arch/arm/src/armv7-m/arm_initialstate.c @@ -136,7 +136,6 @@ void up_initial_state(struct tcb_s *tcb) #endif #endif /* CONFIG_PIC */ -#if !defined(CONFIG_ARMV7M_LAZYFPU) || defined(CONFIG_BUILD_PROTECTED) /* All tasks start via a stub function in kernel space. So all * tasks must start in privileged thread mode. If CONFIG_BUILD_PROTECTED * is defined, then that stub function will switch to unprivileged @@ -145,14 +144,10 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_EXC_RETURN] = EXC_RETURN_PRIVTHR; -#endif /* !CONFIG_ARMV7M_LAZYFPU || CONFIG_BUILD_PROTECTED */ - -#if !defined(CONFIG_ARMV7M_LAZYFPU) && defined(CONFIG_ARCH_FPU) - +#ifdef CONFIG_ARCH_FPU xcp->regs[REG_FPSCR] = 0; /* REVISIT: Initial FPSCR should be configurable */ xcp->regs[REG_FP_RESERVED] = 0; - -#endif /* !CONFIG_ARMV7M_LAZYFPU && CONFIG_ARCH_FPU */ +#endif /* CONFIG_ARCH_FPU */ /* Enable or disable interrupts, based on user configuration */ diff --git a/arch/arm/src/armv7-m/arm_svcall.c b/arch/arm/src/armv7-m/arm_svcall.c index 51d28cec44..2f2241b102 100644 --- a/arch/arm/src/armv7-m/arm_svcall.c +++ b/arch/arm/src/armv7-m/arm_svcall.c @@ -175,9 +175,6 @@ int arm_svcall(int irq, void *context, void *arg) case SYS_save_context: { DEBUGASSERT(regs[REG_R1] != 0); -#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU) - arm_savefpu(regs); -#endif memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE); } break; @@ -226,9 +223,6 @@ int arm_svcall(int irq, void *context, void *arg) case SYS_switch_context: { DEBUGASSERT(regs[REG_R1] != 0 && regs[REG_R2] != 0); -#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU) - arm_savefpu(regs); -#endif *(uint32_t **)regs[REG_R1] = regs; CURRENT_REGS = (uint32_t *)regs[REG_R2]; } diff --git a/arch/arm/src/armv7-m/exc_return.h b/arch/arm/src/armv7-m/exc_return.h index 14147bef9f..ddac01de57 100644 --- a/arch/arm/src/armv7-m/exc_return.h +++ b/arch/arm/src/armv7-m/exc_return.h @@ -81,7 +81,7 @@ * gets state from the main stack. Execution uses MSP after return. */ -#if !defined(CONFIG_ARMV7M_LAZYFPU) && defined(CONFIG_ARCH_FPU) +#ifdef CONFIG_ARCH_FPU # define EXC_RETURN_PRIVTHR (EXC_RETURN_BASE | EXC_RETURN_THREAD_MODE) #else # define EXC_RETURN_PRIVTHR (EXC_RETURN_BASE | EXC_RETURN_STD_CONTEXT | \ @@ -92,7 +92,7 @@ * gets state from the process stack. Execution uses PSP after return. */ -#if !defined(CONFIG_ARMV7M_LAZYFPU) && defined(CONFIG_ARCH_FPU) +#ifdef CONFIG_ARCH_FPU # define EXC_RETURN_UNPRIVTHR (EXC_RETURN_BASE | EXC_RETURN_THREAD_MODE | \ EXC_RETURN_PROCESS_STACK) #else diff --git a/arch/arm/src/armv7-m/gnu/arm_fpu.S b/arch/arm/src/armv7-m/gnu/arm_fpu.S deleted file mode 100644 index cf63f642f7..0000000000 --- a/arch/arm/src/armv7-m/gnu/arm_fpu.S +++ /dev/null @@ -1,270 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/gnu/arm_fpu.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ -/* - * When this file is assembled, it will require the following GCC options: - * - * -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfp -meabi=5 -mthumb - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#ifdef CONFIG_ARCH_FPU - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_savefpu - .globl arm_restorefpu - - .syntax unified - .thumb - .file "arm_fpu.S" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_savefpu - * - * Description: - * Given the pointer to a register save area (in R0), save the state of the - * floating point registers. - * - * C Function Prototype: - * void arm_savefpu(uint32_t *regs); - * - * Input Parameters: - * regs - A pointer to the register save area in which to save the floating point - * registers - * - * Returned Value: - * None - * - ****************************************************************************/ - - .thumb_func - .type arm_savefpu, function -arm_savefpu: - - add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */ - - /* Some older GNU assemblers don't support all the newer UAL mnemonics. */ - -#if 1 /* Use UAL mnemonics */ - /* Store all floating point registers. Registers are stored in numeric order, - * s0, s1, ... in increasing address order. - */ - - vstmia r1!, {s0-s31} /* Save the full FP context */ - - /* Store the floating point control and status register. At the end of the - * vstmia, r1 will point to the FPSCR storage location. - */ - - vmrs r2, fpscr /* Fetch the FPSCR */ - str r2, [r1], #4 /* Save the floating point control and status register */ -#else - /* Store all floating point registers */ - -#if 1 /* Use store multiple */ - fstmias r1!, {s0-s31} /* Save the full FP context */ -#else - vmov r2, r3, d0 /* r2, r3 = d0 */ - str r2, [r1], #4 /* Save S0 and S1 values */ - str r3, [r1], #4 - vmov r2, r3, d1 /* r2, r3 = d1 */ - str r2, [r1], #4 /* Save S2 and S3 values */ - str r3, [r1], #4 - vmov r2, r3, d2 /* r2, r3 = d2 */ - str r2, [r1], #4 /* Save S4 and S5 values */ - str r3, [r1], #4 - vmov r2, r3, d3 /* r2, r3 = d3 */ - str r2, [r1], #4 /* Save S6 and S7 values */ - str r3, [r1], #4 - vmov r2, r3, d4 /* r2, r3 = d4 */ - str r2, [r1], #4 /* Save S8 and S9 values */ - str r3, [r1], #4 - vmov r2, r3, d5 /* r2, r3 = d5 */ - str r2, [r1], #4 /* Save S10 and S11 values */ - str r3, [r1], #4 - vmov r2, r3, d6 /* r2, r3 = d6 */ - str r2, [r1], #4 /* Save S12 and S13 values */ - str r3, [r1], #4 - vmov r2, r3, d7 /* r2, r3 = d7 */ - str r2, [r1], #4 /* Save S14 and S15 values */ - str r3, [r1], #4 - vmov r2, r3, d8 /* r2, r3 = d8 */ - str r2, [r1], #4 /* Save S16 and S17 values */ - str r3, [r1], #4 - vmov r2, r3, d9 /* r2, r3 = d9 */ - str r2, [r1], #4 /* Save S18 and S19 values */ - str r3, [r1], #4 - vmov r2, r3, d10 /* r2, r3 = d10 */ - str r2, [r1], #4 /* Save S20 and S21 values */ - str r3, [r1], #4 - vmov r2, r3, d11 /* r2, r3 = d11 */ - str r2, [r1], #4 /* Save S22 and S23 values */ - str r3, [r1], #4 - vmov r2, r3, d12 /* r2, r3 = d12 */ - str r2, [r1], #4 /* Save S24 and S25 values */ - str r3, [r1], #4 - vmov r2, r3, d13 /* r2, r3 = d13 */ - str r2, [r1], #4 /* Save S26 and S27 values */ - str r3, [r1], #4 - vmov r2, r3, d14 /* r2, r3 = d14 */ - str r2, [r1], #4 /* Save S28 and S29 values */ - str r3, [r1], #4 - vmov r2, r3, d15 /* r2, r3 = d15 */ - str r2, [r1], #4 /* Save S30 and S31 values */ - str r3, [r1], #4 -#endif - - /* Store the floating point control and status register */ - - fmrx r2, fpscr /* Fetch the FPSCR */ - str r2, [r1], #4 /* Save the floating point control and status register */ -#endif - bx lr - - .size arm_savefpu, .-arm_savefpu - -/**************************************************************************** - * Name: arm_restorefpu - * - * Description: - * Given the pointer to a register save area (in R0), restore the state of the - * floating point registers. - * - * C Function Prototype: - * void arm_restorefpu(const uint32_t *regs); - * - * Input Parameters: - * regs - A pointer to the register save area containing the floating point - * registers. - * - * Returned Value: - * This function does not return anything explicitly. However, it is called from - * interrupt level assembly logic that assumes that r0 is preserved. - * - ****************************************************************************/ - - .thumb_func - .type arm_restorefpu, function -arm_restorefpu: - - add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */ - - /* Some older GNU assemblers don't support all the newer UAL mnemonics. */ - -#if 1 /* Use UAL mnemonics */ - /* Load all floating point registers. Registers are loaded in numeric order, - * s0, s1, ... in increasing address order. - */ - - vldmia r1!, {s0-s31} /* Restore the full FP context */ - - /* Load the floating point control and status register. At the end of the - * vstmia, r1 will point to the FPSCR storage location. - */ - - ldr r2, [r1], #4 /* Fetch the floating point control and status register */ - vmsr fpscr, r2 /* Restore the FPSCR */ -#else - /* Load all floating point registers Registers are loaded in numeric order, - * s0, s1, ... in increasing address order. - */ - -#if 1 /* Use load multiple */ - fldmias r1!, {s0-s31} /* Restore the full FP context */ -#else - ldr r2, [r1], #4 /* Fetch S0 and S1 values */ - ldr r3, [r1], #4 - vmov d0, r2, r3 /* Save as d0 */ - ldr r2, [r1], #4 /* Fetch S2 and S3 values */ - ldr r3, [r1], #4 - vmov d1, r2, r3 /* Save as d1 */ - ldr r2, [r1], #4 /* Fetch S4 and S5 values */ - ldr r3, [r1], #4 - vmov d2, r2, r3 /* Save as d2 */ - ldr r2, [r1], #4 /* Fetch S6 and S7 values */ - ldr r3, [r1], #4 - vmov d3, r2, r3 /* Save as d3 */ - ldr r2, [r1], #4 /* Fetch S8 and S9 values */ - ldr r3, [r1], #4 - vmov d4, r2, r3 /* Save as d4 */ - ldr r2, [r1], #4 /* Fetch S10 and S11 values */ - ldr r3, [r1], #4 - vmov d5, r2, r3 /* Save as d5 */ - ldr r2, [r1], #4 /* Fetch S12 and S13 values */ - ldr r3, [r1], #4 - vmov d6, r2, r3 /* Save as d6 */ - ldr r2, [r1], #4 /* Fetch S14 and S15 values */ - ldr r3, [r1], #4 - vmov d7, r2, r3 /* Save as d7 */ - ldr r2, [r1], #4 /* Fetch S16 and S17 values */ - ldr r3, [r1], #4 - vmov d8, r2, r3 /* Save as d8 */ - ldr r2, [r1], #4 /* Fetch S18 and S19 values */ - ldr r3, [r1], #4 - vmov d9, r2, r3 /* Save as d9 */ - ldr r2, [r1], #4 /* Fetch S20 and S21 values */ - ldr r3, [r1], #4 - vmov d10, r2, r3 /* Save as d10 */ - ldr r2, [r1], #4 /* Fetch S22 and S23 values */ - ldr r3, [r1], #4 - vmov d11, r2, r3 /* Save as d11 */ - ldr r2, [r1], #4 /* Fetch S24 and S25 values */ - ldr r3, [r1], #4 - vmov d12, r2, r3 /* Save as d12 */ - ldr r2, [r1], #4 /* Fetch S26 and S27 values */ - ldr r3, [r1], #4 - vmov d13, r2, r3 /* Save as d13 */ - ldr r2, [r1], #4 /* Fetch S28 and S29 values */ - ldr r3, [r1], #4 - vmov d14, r2, r3 /* Save as d14 */ - ldr r2, [r1], #4 /* Fetch S30 and S31 values */ - ldr r3, [r1], #4 - vmov d15, r2, r3 /* Save as d15 */ -#endif - - /* Load the floating point control and status register. r1 points t - * the address of the FPSCR register. - */ - - ldr r2, [r1], #4 /* Fetch the floating point control and status register */ - fmxr fpscr, r2 /* Restore the FPSCR */ -#endif - bx lr - - .size arm_restorefpu, .-arm_restorefpu -#endif /* CONFIG_ARCH_FPU */ - .end diff --git a/arch/arm/src/armv7-m/gnu/arm_lazyexception.S b/arch/arm/src/armv7-m/gnu/arm_lazyexception.S deleted file mode 100644 index 29b88f638b..0000000000 --- a/arch/arm/src/armv7-m/gnu/arm_lazyexception.S +++ /dev/null @@ -1,333 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/gnu/up_lazyexcption.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "exc_return.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - /* In protected mode without an interrupt stack, this interrupt handler will set the MSP to the - * stack pointer of the interrupted thread. If the interrupted thread was a privileged - * thread, that will be the MSP otherwise it will be the PSP. If the PSP is used, then the - * value of the MSP will be invalid when the interrupt handler returns because it will be a - * pointer to an old position in the unprivileged stack. Then when the high priority - * interrupt occurs and uses this stale MSP, there will most likely be a system failure. - * - * If the interrupt stack is selected, on the other hand, then the interrupt handler will - * always set the MSP to the interrupt stack. So when the high priority interrupt occurs, - * it will either use the MSP of the last privileged thread to run or, in the case of the - * nested interrupt, the interrupt stack if no privileged task has run. - */ - -# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8 -# error Interrupt stack must be used with high priority interrupts in protected mode -# endif - - /* Use the BASEPRI to control interrupts is required if nested, high - * priority interrupts are supported. - */ - -# ifndef CONFIG_ARMV7M_USEBASEPRI -# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT -# endif -#endif - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl exception_common - - .syntax unified - .thumb - .file "arm_lazyexception.S" - -/**************************************************************************** - * Macro Definitions - ****************************************************************************/ - -/**************************************************************************** - * Name: setintstack - * - * Description: - * Set the current stack pointer to the "top" the interrupt stack. Single CPU case. Must be - * provided by MCU-specific logic in chip.h for the SMP case. - * - ****************************************************************************/ - -#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .macro setintstack, tmp1, tmp2 - ldr sp, =g_intstacktop - .endm -#endif - -/**************************************************************************** - * .text - ****************************************************************************/ - -/* Common IRQ handling logic. On entry here, the return stack is on either - * the PSP or the MSP and looks like the following: - * - * REG_XPSR - * REG_R15 - * REG_R14 - * REG_R12 - * REG_R3 - * REG_R2 - * REG_R1 - * MSP->REG_R0 - * - * And - * IPSR contains the IRQ number - * R14 Contains the EXC_RETURN value - * We are in handler mode and the current SP is the MSP - */ - - .text - .type exception_common, function - -exception_common: - - /* Get the IRQ number from the IPSR */ - - mrs r0, ipsr /* R0=exception number */ - - /* Complete the context save */ - -#ifdef CONFIG_BUILD_PROTECTED - /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 - * (handler mode) if the stack is on the MSP. It can only be on the PSP if - * EXC_RETURN is 0xfffffffd (unprivileged thread) - */ - - tst r14, #EXC_RETURN_PROCESS_STACK /* Nonzero if context on process stack */ - beq 1f /* Branch if context already on the MSP */ - mrs r1, psp /* R1=The process stack pointer (PSP) */ - mov sp, r1 /* Set the MSP to the PSP */ - -1: -#endif - - /* sp holds the value of the stack pointer AFTER the exception handling logic - * pushed the various registers onto the stack. Get r2 = the value of the - * stack pointer BEFORE the interrupt modified it. - */ - - mov r2, sp /* R2=Copy of the main/process stack pointer */ - add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ - -#ifdef CONFIG_ARMV7M_USEBASEPRI - mrs r3, basepri /* R3=Current BASEPRI setting */ -#else - mrs r3, primask /* R3=Current PRIMASK setting */ -#endif - -#ifdef CONFIG_ARCH_FPU - /* Skip over the block of memory reserved for floating pointer register save. - * Lazy FPU register saving is used. FPU registers will be saved in this - * block only if a context switch occurs (this means, of course, that the FPU - * cannot be used in interrupt processing). - */ - - sub sp, #(4*SW_FPU_REGS) -#endif - - /* Save the remaining registers on the stack after the registers pushed - * by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11, - * r14=register values. - */ - -#ifdef CONFIG_BUILD_PROTECTED - stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ -#else - stmdb sp!, {r2-r11} /* Save the remaining registers plus the SP value */ -#endif - - /* There are two arguments to arm_doirq: - * - * R0 = The IRQ number - * R1 = The top of the stack points to the saved state - */ - - mov r1, sp - - /* Also save the top of the stack in a preserved register */ - - mov r4, sp - -#if CONFIG_ARCH_INTERRUPTSTACK > 7 - /* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use - * a special special interrupt stack pointer. The way that this is done - * here prohibits nested interrupts without some additional logic! - */ - - setintstack r2, r3 /* SP = IRQ stack top */ -#else - /* Otherwise, we will re-use the interrupted thread's stack. That may - * mean using either MSP or PSP stack for interrupt level processing (in - * kernel mode). - */ - - /* If the interrupt stack is disabled, reserve xcpcontext to ensure - * that signal processing can have a separate xcpcontext to handle - * signal context (reference: arm_schedulesigaction.c): - * ---------------------- - * | IRQ XCP context | - * ------------------- - * | Signal XCP context | - * ---------------------- <- SP - * also the sp should be restore after arm_doirq() - */ - - sub r2, r4, #XCPTCONTEXT_SIZE /* Reserve signal context */ - bic r2, r2, #7 /* Get the stack pointer with 8-byte alignment */ - mov sp, r2 /* Instantiate the aligned stack */ -#endif - - bl arm_doirq /* R0=IRQ, R1=register save (msp) */ - - /* On return from arm_doirq, R0 will hold a pointer to register context - * array to use for the interrupt return. If that return value is the same - * as current stack pointer, then things are relatively easy. - */ - - cmp r0, r4 /* Context switch? */ - beq 2f /* Branch if no context switch */ - - /* We are returning with a pending context switch. - * - * If the FPU is enabled, then we will need to restore FPU registers. - * This is not done in normal interrupt save/restore because the cost - * is prohibitive. This is only done when switching contexts. A - * consequence of this is that floating point operations may not be - * performed in interrupt handling logic. - * - * Here: - * r0 = Address of the register save area - * - * NOTE: It is a requirement that arm_restorefpu() preserve the value of - * r0! - */ - -#ifdef CONFIG_ARCH_FPU - bl arm_restorefpu /* Restore the FPU registers */ -#endif - -2: -#ifdef CONFIG_BUILD_PROTECTED - ldmia r0!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ -#else - ldmia r0!, {r2-r11} /* Recover R4-R11 + 2 temp values */ -#endif - -#ifdef CONFIG_ARCH_FPU - /* Skip over the block of memory reserved for floating pointer register - * save. Then R0 is the address of the HW save area - */ - - add r0, #(4*SW_FPU_REGS) -#endif - - /* Set up to return from the exception - * - * Here: - * r0 = Address on the target thread's stack position at the start of - * the registers saved by hardware - * r3 = primask or basepri - * r4-r11 = restored register values - */ - -#ifdef CONFIG_BUILD_PROTECTED - /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 - * (handler mode) if the stack is on the MSP. It can only be on the PSP if - * EXC_RETURN is 0xfffffffd (unprivileged thread) - */ - - mrs r2, control /* R2=Contents of the control register */ - tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */ - beq 3f /* Branch if privileged */ - - orr r2, r2, #1 /* Unprivileged mode */ - msr psp, r0 /* R0=The process stack pointer */ - b 4f -3: - bic r2, r2, #1 /* Privileged mode */ - msr msp, r0 /* R0=The main stack pointer */ -4: - msr control, r2 /* Save the updated control register */ -#else - msr msp, r0 /* Recover the return MSP value */ - - /* Preload r14 with the special return value first (so that the return - * actually occurs with interrupts still disabled). - */ - - ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */ -#endif - - /* Restore the interrupt state */ - -#ifdef CONFIG_ARMV7M_USEBASEPRI - msr basepri, r3 /* Restore interrupts priority masking */ -#else - msr primask, r3 /* Restore interrupts */ -#endif - - /* Always return with R14 containing the special value that will: (1) - * return to thread mode, and (2) continue to use the MSP - */ - - bx r14 /* And return */ - .size exception_common, .-exception_common - -/**************************************************************************** - * Name: g_intstackalloc/g_intstacktop - * - * Description: - * Shouldn't happen - * - ****************************************************************************/ - -#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .bss - .global g_intstackalloc - .global g_intstacktop - .balign 8 -g_intstackalloc: - .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7) -g_intstacktop: - .size g_intstackalloc, .-g_intstackalloc -#endif - - .end diff --git a/arch/arm/src/armv7-r/arm_restorefpu.S b/arch/arm/src/armv7-r/arm_restorefpu.S deleted file mode 100644 index 746a3e121e..0000000000 --- a/arch/arm/src/armv7-r/arm_restorefpu.S +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-r/arm_restorefpu.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#ifdef CONFIG_ARCH_FPU - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_restorefpu - .file "arm_restorefpu.S" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - - .text - -/**************************************************************************** - * Name: arm_restorefpu - * - * Description: - * Given the pointer to a register save area (in R0), restore the state of the - * floating point registers. - * - * C Function Prototype: - * void arm_restorefpu(const uint32_t *regs); - * - * Input Parameters: - * regs - A pointer to the register save area containing the floating point - * registers. - * - * Returned Value: - * This function does not return anything explicitly. However, it is called from - * interrupt level assembly logic that assumes that r0 is preserved. - * - ****************************************************************************/ - - .globl arm_restorefpu - .type arm_restorefpu, function - -arm_restorefpu: - - add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */ - - /* Load all floating point registers. Registers are loaded in numeric order, - * s0, s1, ... in increasing address order. - */ - -#ifdef CONFIG_ARM_DPFPU32 - vldmia.64 r1!, {d0-d15} /* Restore the full FP context */ - vldmia.64 r1!, {d16-d31} -#else - vldmia r1!, {s0-s31} /* Restore the full FP context */ -#endif - - /* Load the floating point control and status register. At the end of the - * vstmia, r1 will point to the FPSCR storage location. - */ - - ldr r2, [r1], #4 /* Fetch the floating point control and status register */ - vmsr fpscr, r2 /* Restore the FPSCR */ - bx lr - - .size arm_restorefpu, .-arm_restorefpu -#endif /* CONFIG_ARCH_FPU */ - .end diff --git a/arch/arm/src/armv7-r/arm_savefpu.S b/arch/arm/src/armv7-r/arm_savefpu.S deleted file mode 100644 index 2ae4830b85..0000000000 --- a/arch/arm/src/armv7-r/arm_savefpu.S +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-r/arm_savefpu.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#ifdef CONFIG_ARCH_FPU - - .file "arm_savefpu.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_savefpu - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - - .text - -/**************************************************************************** - * Name: arm_savefpu - * - * Description: - * Given the pointer to a register save area (in R0), save the state of the - * floating point registers. - * - * C Function Prototype: - * void arm_savefpu(uint32_t *regs); - * - * Input Parameters: - * regs - A pointer to the register save area in which to save the floating point - * registers - * - * Returned Value: - * None - * - ****************************************************************************/ - - .globl arm_savefpu - .type arm_savefpu, function - -arm_savefpu: - - add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */ - - /* Store all floating point registers. Registers are stored in numeric order, - * s0, s1, ... in increasing address order. - */ - -#ifdef CONFIG_ARM_DPFPU32 - vstmia.64 r1!, {d0-d15} /* Save the full FP context */ - vstmia.64 r1!, {d16-d31} -#else - vstmia r1!, {s0-s31} /* Save the full FP context */ -#endif - - /* Store the floating point control and status register. At the end of the - * vstmia, r1 will point to the FPSCR storage location. - */ - - vmrs r2, fpscr /* Fetch the FPSCR */ - str r2, [r1], #4 /* Save the floating point control and status register */ - bx lr - - .size arm_savefpu, .-arm_savefpu -#endif /* CONFIG_ARCH_FPU */ - .end diff --git a/arch/arm/src/armv8-m/Kconfig b/arch/arm/src/armv8-m/Kconfig index c868c59de9..4ae3fcec50 100644 --- a/arch/arm/src/armv8-m/Kconfig +++ b/arch/arm/src/armv8-m/Kconfig @@ -13,40 +13,6 @@ config ARMV8M_HAVE_DCACHE bool default n -config ARMV8M_LAZYFPU - bool "Lazy FPU storage" - default n - depends on ARCH_HAVE_LAZYFPU - ---help--- - There are two forms of the common vector logic. There are pros and - cons to each option: - - 1) The standard common vector logic exploits features of the ARMv8-M - architecture to save the all of floating registers on entry into - each interrupt and then to restore the floating registers when - the interrupt returns. The primary advantage to this approach is - that floating point operations are available in interrupt - handling logic. Since the volatile registers are preserved, - operations on the floating point registers by interrupt handling - logic has no ill effect. The downside is, of course, that more - stack operations are required on each interrupt to save and store - the floating point registers. Because of the some special - features of the ARMv-M, this is not as much overhead as you might - expect, but overhead nonetheless. - - 2) The lazy FPU common vector logic does not save or restore - floating point registers on entry and exit from the interrupt - handler. Rather, the floating point registers are not restored - until it is absolutely necessary to do so when a context switch - occurs and the interrupt handler will be returning to a different - floating point context. Since floating point registers are not - protected, floating point operations must not be performed in - interrupt handling logic. Better interrupt performance is be - expected, however. - - By default, the "standard" common vector logic is build. This - option selects the alternate lazy FPU common vector logic. - config ARMV8M_USEBASEPRI bool "Use BASEPRI Register" default y if ARCH_HIPRI_INTERRUPT diff --git a/arch/arm/src/armv8-m/arm_fpu.S b/arch/arm/src/armv8-m/arm_fpu.S deleted file mode 100644 index 5ced463059..0000000000 --- a/arch/arm/src/armv8-m/arm_fpu.S +++ /dev/null @@ -1,270 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv8-m/arm_fpu.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ -/* - * When this file is assembled, it will require the following GCC options: - * - * -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfp -meabi=5 -mthumb - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#ifdef CONFIG_ARCH_FPU - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_savefpu - .globl arm_restorefpu - - .syntax unified - .thumb - .file "arm_fpu.S" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_savefpu - * - * Description: - * Given the pointer to a register save area (in R0), save the state of the - * floating point registers. - * - * C Function Prototype: - * void arm_savefpu(uint32_t *regs); - * - * Input Parameters: - * regs - A pointer to the register save area in which to save the floating point - * registers - * - * Returned Value: - * None - * - ****************************************************************************/ - - .thumb_func - .type arm_savefpu, function -arm_savefpu: - - add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */ - - /* Some older GNU assemblers don't support all the newer UAL mnemonics. */ - -#if 1 /* Use UAL mnemonics */ - /* Store all floating point registers. Registers are stored in numeric order, - * s0, s1, ... in increasing address order. - */ - - vstmia r1!, {s0-s31} /* Save the full FP context */ - - /* Store the floating point control and status register. At the end of the - * vstmia, r1 will point to the FPSCR storage location. - */ - - vmrs r2, fpscr /* Fetch the FPSCR */ - str r2, [r1], #4 /* Save the floating point control and status register */ -#else - /* Store all floating point registers */ - -#if 1 /* Use store multiple */ - fstmias r1!, {s0-s31} /* Save the full FP context */ -#else - vmov r2, r3, d0 /* r2, r3 = d0 */ - str r2, [r1], #4 /* Save S0 and S1 values */ - str r3, [r1], #4 - vmov r2, r3, d1 /* r2, r3 = d1 */ - str r2, [r1], #4 /* Save S2 and S3 values */ - str r3, [r1], #4 - vmov r2, r3, d2 /* r2, r3 = d2 */ - str r2, [r1], #4 /* Save S4 and S5 values */ - str r3, [r1], #4 - vmov r2, r3, d3 /* r2, r3 = d3 */ - str r2, [r1], #4 /* Save S6 and S7 values */ - str r3, [r1], #4 - vmov r2, r3, d4 /* r2, r3 = d4 */ - str r2, [r1], #4 /* Save S8 and S9 values */ - str r3, [r1], #4 - vmov r2, r3, d5 /* r2, r3 = d5 */ - str r2, [r1], #4 /* Save S10 and S11 values */ - str r3, [r1], #4 - vmov r2, r3, d6 /* r2, r3 = d6 */ - str r2, [r1], #4 /* Save S12 and S13 values */ - str r3, [r1], #4 - vmov r2, r3, d7 /* r2, r3 = d7 */ - str r2, [r1], #4 /* Save S14 and S15 values */ - str r3, [r1], #4 - vmov r2, r3, d8 /* r2, r3 = d8 */ - str r2, [r1], #4 /* Save S16 and S17 values */ - str r3, [r1], #4 - vmov r2, r3, d9 /* r2, r3 = d9 */ - str r2, [r1], #4 /* Save S18 and S19 values */ - str r3, [r1], #4 - vmov r2, r3, d10 /* r2, r3 = d10 */ - str r2, [r1], #4 /* Save S20 and S21 values */ - str r3, [r1], #4 - vmov r2, r3, d11 /* r2, r3 = d11 */ - str r2, [r1], #4 /* Save S22 and S23 values */ - str r3, [r1], #4 - vmov r2, r3, d12 /* r2, r3 = d12 */ - str r2, [r1], #4 /* Save S24 and S25 values */ - str r3, [r1], #4 - vmov r2, r3, d13 /* r2, r3 = d13 */ - str r2, [r1], #4 /* Save S26 and S27 values */ - str r3, [r1], #4 - vmov r2, r3, d14 /* r2, r3 = d14 */ - str r2, [r1], #4 /* Save S28 and S29 values */ - str r3, [r1], #4 - vmov r2, r3, d15 /* r2, r3 = d15 */ - str r2, [r1], #4 /* Save S30 and S31 values */ - str r3, [r1], #4 -#endif - - /* Store the floating point control and status register */ - - fmrx r2, fpscr /* Fetch the FPSCR */ - str r2, [r1], #4 /* Save the floating point control and status register */ -#endif - bx lr - - .size arm_savefpu, .-arm_savefpu - -/**************************************************************************** - * Name: arm_restorefpu - * - * Description: - * Given the pointer to a register save area (in R0), restore the state of the - * floating point registers. - * - * C Function Prototype: - * void arm_restorefpu(const uint32_t *regs); - * - * Input Parameters: - * regs - A pointer to the register save area containing the floating point - * registers. - * - * Returned Value: - * This function does not return anything explicitly. However, it is called from - * interrupt level assembly logic that assumes that r0 is preserved. - * - ****************************************************************************/ - - .thumb_func - .type arm_restorefpu, function -arm_restorefpu: - - add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */ - - /* Some older GNU assemblers don't support all the newer UAL mnemonics. */ - -#if 1 /* Use UAL mnemonics */ - /* Load all floating point registers. Registers are loaded in numeric order, - * s0, s1, ... in increasing address order. - */ - - vldmia r1!, {s0-s31} /* Restore the full FP context */ - - /* Load the floating point control and status register. At the end of the - * vstmia, r1 will point to the FPSCR storage location. - */ - - ldr r2, [r1], #4 /* Fetch the floating point control and status register */ - vmsr fpscr, r2 /* Restore the FPSCR */ -#else - /* Load all floating point registers Registers are loaded in numeric order, - * s0, s1, ... in increasing address order. - */ - -#if 1 /* Use load multiple */ - fldmias r1!, {s0-s31} /* Restore the full FP context */ -#else - ldr r2, [r1], #4 /* Fetch S0 and S1 values */ - ldr r3, [r1], #4 - vmov d0, r2, r3 /* Save as d0 */ - ldr r2, [r1], #4 /* Fetch S2 and S3 values */ - ldr r3, [r1], #4 - vmov d1, r2, r3 /* Save as d1 */ - ldr r2, [r1], #4 /* Fetch S4 and S5 values */ - ldr r3, [r1], #4 - vmov d2, r2, r3 /* Save as d2 */ - ldr r2, [r1], #4 /* Fetch S6 and S7 values */ - ldr r3, [r1], #4 - vmov d3, r2, r3 /* Save as d3 */ - ldr r2, [r1], #4 /* Fetch S8 and S9 values */ - ldr r3, [r1], #4 - vmov d4, r2, r3 /* Save as d4 */ - ldr r2, [r1], #4 /* Fetch S10 and S11 values */ - ldr r3, [r1], #4 - vmov d5, r2, r3 /* Save as d5 */ - ldr r2, [r1], #4 /* Fetch S12 and S13 values */ - ldr r3, [r1], #4 - vmov d6, r2, r3 /* Save as d6 */ - ldr r2, [r1], #4 /* Fetch S14 and S15 values */ - ldr r3, [r1], #4 - vmov d7, r2, r3 /* Save as d7 */ - ldr r2, [r1], #4 /* Fetch S16 and S17 values */ - ldr r3, [r1], #4 - vmov d8, r2, r3 /* Save as d8 */ - ldr r2, [r1], #4 /* Fetch S18 and S19 values */ - ldr r3, [r1], #4 - vmov d9, r2, r3 /* Save as d9 */ - ldr r2, [r1], #4 /* Fetch S20 and S21 values */ - ldr r3, [r1], #4 - vmov d10, r2, r3 /* Save as d10 */ - ldr r2, [r1], #4 /* Fetch S22 and S23 values */ - ldr r3, [r1], #4 - vmov d11, r2, r3 /* Save as d11 */ - ldr r2, [r1], #4 /* Fetch S24 and S25 values */ - ldr r3, [r1], #4 - vmov d12, r2, r3 /* Save as d12 */ - ldr r2, [r1], #4 /* Fetch S26 and S27 values */ - ldr r3, [r1], #4 - vmov d13, r2, r3 /* Save as d13 */ - ldr r2, [r1], #4 /* Fetch S28 and S29 values */ - ldr r3, [r1], #4 - vmov d14, r2, r3 /* Save as d14 */ - ldr r2, [r1], #4 /* Fetch S30 and S31 values */ - ldr r3, [r1], #4 - vmov d15, r2, r3 /* Save as d15 */ -#endif - - /* Load the floating point control and status register. r1 points t - * the address of the FPSCR register. - */ - - ldr r2, [r1], #4 /* Fetch the floating point control and status register */ - fmxr fpscr, r2 /* Restore the FPSCR */ -#endif - bx lr - - .size arm_restorefpu, .-arm_restorefpu -#endif /* CONFIG_ARCH_FPU */ - .end diff --git a/arch/arm/src/armv8-m/arm_fpuconfig.c b/arch/arm/src/armv8-m/arm_fpuconfig.c index f81ada6f51..b0b1642128 100644 --- a/arch/arm/src/armv8-m/arm_fpuconfig.c +++ b/arch/arm/src/armv8-m/arm_fpuconfig.c @@ -54,8 +54,6 @@ * ****************************************************************************/ -#ifndef CONFIG_ARMV8M_LAZYFPU - void arm_fpuconfig(void) { uint32_t regval; @@ -83,35 +81,3 @@ void arm_fpuconfig(void) regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11); putreg32(regval, NVIC_CPACR); } - -#else - -void arm_fpuconfig(void) -{ - uint32_t regval; - - /* Clear CONTROL.FPCA so that we do not get the extended context frame - * with the volatile FP registers stacked in the saved context. - */ - - regval = getcontrol(); - regval &= ~CONTROL_FPCA; - setcontrol(regval); - - /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend - * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we - * are going to keep CONTROL.FPCA off for all contexts. - */ - - regval = getreg32(NVIC_FPCCR); - regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN); - putreg32(regval, NVIC_FPCCR); - - /* Enable full access to CP10 and CP11 */ - - regval = getreg32(NVIC_CPACR); - regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11); - putreg32(regval, NVIC_CPACR); -} - -#endif diff --git a/arch/arm/src/armv8-m/arm_initialstate.c b/arch/arm/src/armv8-m/arm_initialstate.c index ad8e0d15b1..98f5b794e9 100644 --- a/arch/arm/src/armv8-m/arm_initialstate.c +++ b/arch/arm/src/armv8-m/arm_initialstate.c @@ -142,7 +142,6 @@ void up_initial_state(struct tcb_s *tcb) #endif #endif /* CONFIG_PIC */ -#if !defined(CONFIG_ARMV8M_LAZYFPU) || defined(CONFIG_BUILD_PROTECTED) /* All tasks start via a stub function in kernel space. So all * tasks must start in privileged thread mode. If CONFIG_BUILD_PROTECTED * is defined, then that stub function will switch to unprivileged @@ -151,14 +150,10 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_EXC_RETURN] = EXC_RETURN_PRIVTHR; -#endif /* !CONFIG_ARMV8M_LAZYFPU || CONFIG_BUILD_PROTECTED */ - -#if !defined(CONFIG_ARMV8M_LAZYFPU) && defined(CONFIG_ARCH_FPU) - +#ifdef CONFIG_ARCH_FPU xcp->regs[REG_FPSCR] |= ARMV8M_FPSCR_LTPSIZE_NONE; xcp->regs[REG_FP_RESERVED] = 0; - -#endif /* !CONFIG_ARMV8M_LAZYFPU && CONFIG_ARCH_FPU */ +#endif /* CONFIG_ARCH_FPU */ /* Enable or disable interrupts, based on user configuration */ diff --git a/arch/arm/src/armv8-m/arm_lazyexception.S b/arch/arm/src/armv8-m/arm_lazyexception.S deleted file mode 100644 index cc9b994925..0000000000 --- a/arch/arm/src/armv8-m/arm_lazyexception.S +++ /dev/null @@ -1,362 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv8-m/up_lazyexcption.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "exc_return.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - /* In protected mode without an interrupt stack, this interrupt handler will set the MSP to the - * stack pointer of the interrupted thread. If the interrupted thread was a privileged - * thread, that will be the MSP otherwise it will be the PSP. If the PSP is used, then the - * value of the MSP will be invalid when the interrupt handler returns because it will be a - * pointer to an old position in the unprivileged stack. Then when the high priority - * interrupt occurs and uses this stale MSP, there will most likely be a system failure. - * - * If the interrupt stack is selected, on the other hand, then the interrupt handler will - * always set the MSP to the interrupt stack. So when the high priority interrupt occurs, - * it will either use the MSP of the last privileged thread to run or, in the case of the - * nested interrupt, the interrupt stack if no privileged task has run. - */ - -# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8 -# error Interrupt stack must be used with high priority interrupts in protected mode -# endif - - /* Use the BASEPRI to control interrupts is required if nested, high - * priority interrupts are supported. - */ - -# ifndef CONFIG_ARMV8M_USEBASEPRI -# error CONFIG_ARMV8M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT -# endif -#endif - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl exception_common - - .syntax unified - .thumb - .file "arm_lazyexception.S" - -/**************************************************************************** - * Macro Definitions - ****************************************************************************/ - -/**************************************************************************** - * Name: setintstack - * - * Description: - * Set the current stack pointer to the "top" the interrupt stack. Single CPU case. Must be - * provided by MCU-specific logic in chip.h for the SMP case. - * - ****************************************************************************/ - -#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .macro setintstack, tmp1, tmp2 -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE - ldr \tmp1, =g_intstackalloc - msr msplim, \tmp1 -#endif - ldr sp, =g_intstacktop - .endm -#endif - -/**************************************************************************** - * .text - ****************************************************************************/ - -/* Common IRQ handling logic. On entry here, the return stack is on either - * the PSP or the MSP and looks like the following: - * - * REG_XPSR - * REG_R15 - * REG_R14 - * REG_R12 - * REG_R3 - * REG_R2 - * REG_R1 - * MSP->REG_R0 - * - * And - * IPSR contains the IRQ number - * R14 Contains the EXC_RETURN value - * We are in handler mode and the current SP is the MSP - */ - - .text - .type exception_common, function - -exception_common: - - /* Get the IRQ number from the IPSR */ - - mrs r0, ipsr /* R0=exception number */ - - /* Complete the context save */ - - tst r14, #EXC_RETURN_PROCESS_STACK /* Nonzero if context on process stack */ - -#ifdef CONFIG_BUILD_PROTECTED - /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 - * (handler mode) if the stack is on the MSP. It can only be on the PSP if - * EXC_RETURN is 0xfffffffd (unprivileged thread) - */ - - beq 1f /* Branch if context already on the MSP */ - mrs r1, psp /* R1=The process stack pointer (PSP) */ - mov sp, r1 /* Set the MSP to the PSP */ - -1: -#endif - - /* sp holds the value of the stack pointer AFTER the exception handling logic - * pushed the various registers onto the stack. Get r2 = the value of the - * stack pointer BEFORE the interrupt modified it. - */ - - mov r2, sp /* R2=Copy of the main/process stack pointer */ - add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ - -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE - mov r3, #0x0 - - ittee eq - mrseq r1, msplim - msreq msplim, r3 - mrsne r1, psplim - msrne psplim, r3 - - stmdb sp!, {r1} -#endif - -#ifdef CONFIG_ARMV8M_USEBASEPRI - mrs r3, basepri /* R3=Current BASEPRI setting */ -#else - mrs r3, primask /* R3=Current PRIMASK setting */ -#endif - -#ifdef CONFIG_ARCH_FPU - /* Skip over the block of memory reserved for floating pointer register save. - * Lazy FPU register saving is used. FPU registers will be saved in this - * block only if a context switch occurs (this means, of course, that the FPU - * cannot be used in interrupt processing). - */ - - sub sp, #(4*SW_FPU_REGS) -#endif - - /* Save the remaining registers on the stack after the registers pushed - * by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11, - * r14=register values. - */ - -#ifdef CONFIG_BUILD_PROTECTED - stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ -#else - stmdb sp!, {r2-r11} /* Save the remaining registers plus the SP value */ -#endif - - /* There are two arguments to arm_doirq: - * - * R0 = The IRQ number - * R1 = The top of the stack points to the saved state - */ - - mov r1, sp - - /* Also save the top of the stack in a preserved register */ - - mov r4, sp - -#if CONFIG_ARCH_INTERRUPTSTACK > 7 - /* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use - * a special special interrupt stack pointer. The way that this is done - * here prohibits nested interrupts without some additional logic! - */ - - setintstack r2, r3 /* SP = IRQ stack top */ -#else - /* Otherwise, we will re-use the interrupted thread's stack. That may - * mean using either MSP or PSP stack for interrupt level processing (in - * kernel mode). - */ - - /* If the interrupt stack is disabled, reserve xcpcontext to ensure - * that signal processing can have a separate xcpcontext to handle - * signal context (reference: arm_schedulesigaction.c): - * ---------------------- - * | IRQ XCP context | - * ------------------- - * | Signal XCP context | - * ---------------------- <- SP - * also the sp should be restore after arm_doirq() - */ - - sub r2, r4, #XCPTCONTEXT_SIZE /* Reserve signal context */ - bic r2, r2, #7 /* Get the stack pointer with 8-byte alignment */ - mov sp, r2 /* Instantiate the aligned stack */ -#endif - - bl arm_doirq /* R0=IRQ, R1=register save (msp) */ - - /* On return from arm_doirq, R0 will hold a pointer to register context - * array to use for the interrupt return. - */ - - cmp r0, r4 /* Context switch? */ - beq 2f /* Branch if no context switch */ - - /* We are returning with a pending context switch. - * - * If the FPU is enabled, then we will need to restore FPU registers. - * This is not done in normal interrupt save/restore because the cost - * is prohibitive. This is only done when switching contexts. A - * consequence of this is that floating point operations may not be - * performed in interrupt handling logic. - * - * Here: - * r0 = Address of the register save area - * - * NOTE: It is a requirement that arm_restorefpu() preserve the value of - * r0! - */ - -#ifdef CONFIG_ARCH_FPU - bl arm_restorefpu /* Restore the FPU registers */ -#endif - -2: -#ifdef CONFIG_BUILD_PROTECTED - ldmia r0!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ -#else - ldmia r0!, {r2-r11} /* Recover R4-R11 + 2 temp values */ -#endif - -#ifdef CONFIG_ARCH_FPU - /* Skip over the block of memory reserved for floating pointer register - * save. Then R1 is the address of the HW save area - */ - - add r0, #(4*SW_FPU_REGS) -#endif - -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE - ldmia r0!, {r1} /* Get psplim/msplim */ -#endif - - /* Set up to return from the exception - * - * Here: - * r0 = Address on the target thread's stack position at the start of - * the registers saved by hardware - * r3 = primask or basepri - * r4-r11 = restored register values - */ - -#ifdef CONFIG_BUILD_PROTECTED - /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 - * (handler mode) if the stack is on the MSP. It can only be on the PSP if - * EXC_RETURN is 0xfffffffd (unprivileged thread) - */ - - mrs r2, control /* R2=Contents of the control register */ - tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */ - beq 3f /* Branch if privileged */ - - orr r2, r2, #1 /* Unprivileged mode */ -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE - msr psplim, r1 -#endif - msr psp, r0 /* R1=The process stack pointer */ - b 4f -3: - bic r2, r2, #1 /* Privileged mode */ -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE - msr msplim, r1 -#endif - msr msp, r0 /* R1=The main stack pointer */ -4: - msr control, r2 /* Save the updated control register */ -#else -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE - msr msplim, r1 -#endif - msr msp, r0 /* Recover the return MSP value */ - - /* Preload r14 with the special return value first (so that the return - * actually occurs with interrupts still disabled). - */ - - ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */ -#endif - - /* Restore the interrupt state */ - -#ifdef CONFIG_ARMV8M_USEBASEPRI - msr basepri, r3 /* Restore interrupts priority masking */ -#else - msr primask, r3 /* Restore interrupts */ -#endif - - /* Always return with R14 containing the special value that will: (1) - * return to thread mode, and (2) continue to use the MSP - */ - - bx r14 /* And return */ - .size exception_common, .-exception_common - -/**************************************************************************** - * Name: g_intstackalloc/g_intstacktop - * - * Description: - * Shouldn't happen - * - ****************************************************************************/ - -#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .bss - .global g_intstackalloc - .global g_intstacktop - .balign 8 -g_intstackalloc: - .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7) -g_intstacktop: - .size g_intstackalloc, .-g_intstackalloc -#endif - - .end diff --git a/arch/arm/src/armv8-m/arm_svcall.c b/arch/arm/src/armv8-m/arm_svcall.c index e62b0c2da7..23f9b2cdff 100644 --- a/arch/arm/src/armv8-m/arm_svcall.c +++ b/arch/arm/src/armv8-m/arm_svcall.c @@ -174,9 +174,6 @@ int arm_svcall(int irq, void *context, void *arg) case SYS_save_context: { DEBUGASSERT(regs[REG_R1] != 0); -#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV8M_LAZYFPU) - arm_savefpu(regs); -#endif memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE); } break; @@ -225,9 +222,6 @@ int arm_svcall(int irq, void *context, void *arg) case SYS_switch_context: { DEBUGASSERT(regs[REG_R1] != 0 && regs[REG_R2] != 0); -#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV8M_LAZYFPU) - arm_savefpu(regs); -#endif *(uint32_t **)regs[REG_R1] = regs; CURRENT_REGS = (uint32_t *)regs[REG_R2]; } diff --git a/arch/arm/src/armv8-m/exc_return.h b/arch/arm/src/armv8-m/exc_return.h index 9bb3976c86..f415558a7c 100644 --- a/arch/arm/src/armv8-m/exc_return.h +++ b/arch/arm/src/armv8-m/exc_return.h @@ -108,7 +108,7 @@ * gets state from the main stack. Execution uses MSP after return. */ -#if !defined(CONFIG_ARMV8M_LAZYFPU) && defined(CONFIG_ARCH_FPU) +#ifdef CONFIG_ARCH_FPU # define EXC_RETURN_PRIVTHR (EXC_RETURN_BASE | EXC_RETURN_THREAD_MODE | \ EXC_RETURN_DEF_STACKING) #else @@ -120,7 +120,7 @@ * gets state from the process stack. Execution uses PSP after return. */ -#if !defined(CONFIG_ARMV8M_LAZYFPU) && defined(CONFIG_ARCH_FPU) +#ifdef CONFIG_ARCH_FPU # define EXC_RETURN_UNPRIVTHR (EXC_RETURN_BASE | EXC_RETURN_THREAD_MODE | \ EXC_RETURN_PROCESS_STACK | EXC_RETURN_DEF_STACKING) #else @@ -129,7 +129,7 @@ EXC_RETURN_DEF_STACKING) #endif -#if defined(CONFIG_ARCH_FPU) +#ifdef CONFIG_ARCH_FPU #define EXC_INTEGRITY_SIGNATURE (0xfefa125a) #else #define EXC_INTEGRITY_SIGNATURE (0xfefa125b) diff --git a/arch/arm/src/common/arm_internal.h b/arch/arm/src/common/arm_internal.h index ecaed55624..4bd18f6772 100644 --- a/arch/arm/src/common/arm_internal.h +++ b/arch/arm/src/common/arm_internal.h @@ -89,67 +89,10 @@ #define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK) -/* Macros to handle saving and restoring interrupt state. In the current ARM - * model, the state is always copied to and from the stack and TCB. In the - * Cortex-M0/3 model, the state is copied from the stack to the TCB, but only - * a referenced is passed to get the state from the TCB. Cortex-M4 is the - * same, but may have additional complexity for floating point support in - * some configurations. - */ +/* Macros to handle saving and restoring interrupt state. */ -#if defined(CONFIG_ARCH_ARMV6M) || defined(CONFIG_ARCH_ARMV7M) || \ - defined(CONFIG_ARCH_ARMV8M) - - /* If the floating point unit is present and enabled, then save the - * floating point registers as well as normal ARM registers. This only - * applies if "lazy" floating point register save/restore is used - */ - -# if defined(CONFIG_ARCH_FPU) && (defined(CONFIG_ARMV7M_LAZYFPU) || \ - defined(CONFIG_ARMV8M_LAZYFPU)) -# define arm_savestate(regs) (regs = (uint32_t *)CURRENT_REGS, arm_savefpu(regs)) -# else -# define arm_savestate(regs) (regs = (uint32_t *)CURRENT_REGS) -# endif -# define arm_restorestate(regs) (CURRENT_REGS = regs) - -/* The Cortex-A and Cortex-R support the same mechanism, but only lazy - * floating point register save/restore. - */ - -#elif defined(CONFIG_ARCH_ARMV7A) || defined(CONFIG_ARCH_ARMV7R) - - /* If the floating point unit is present and enabled, then save the - * floating point registers as well as normal ARM registers. - */ - -# if defined(CONFIG_ARCH_FPU) -# define arm_savestate(regs) (regs = (uint32_t *)CURRENT_REGS, arm_savefpu(regs)) -# else -# define arm_savestate(regs) (regs = (uint32_t *)CURRENT_REGS) -# endif -# define arm_restorestate(regs) (CURRENT_REGS = regs) - -/* Otherwise, for the ARM7 and ARM9. The state is copied in full from stack - * to stack. This is not very efficient and should be fixed to match - * Cortex-A5. - */ - -#else - - /* If the floating point unit is present and enabled, then save the - * floating point registers as well as normal ARM registers. Only "lazy" - * floating point save/restore is supported. - */ - -# if defined(CONFIG_ARCH_FPU) -# define arm_savestate(regs) (regs = (uint32_t *)CURRENT_REGS, arm_savefpu(regs)) -# else -# define arm_savestate(regs) (regs = (uint32_t *)CURRENT_REGS) -# endif -# define arm_restorestate(regs) (CURRENT_REGS = regs) - -#endif +#define arm_savestate(regs) (regs = (uint32_t *)CURRENT_REGS) +#define arm_restorestate(regs) (CURRENT_REGS = regs) /* Toolchain dependent, linker defined section addresses */ @@ -440,12 +383,8 @@ void arm_vectorfiq(void); #ifdef CONFIG_ARCH_FPU void arm_fpuconfig(void); -void arm_savefpu(uint32_t *regs); -void arm_restorefpu(const uint32_t *regs); #else # define arm_fpuconfig() -# define arm_savefpu(regs) -# define arm_restorefpu(regs) #endif /* Low level serial output **************************************************/ diff --git a/arch/arm/src/cxd56xx/Make.defs b/arch/arm/src/cxd56xx/Make.defs index 68105f0ed3..4ae0bfb939 100644 --- a/arch/arm/src/cxd56xx/Make.defs +++ b/arch/arm/src/cxd56xx/Make.defs @@ -19,7 +19,7 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += vfork.S +CMN_ASRCS += vfork.S arm_exception.S ifneq ($(CONFIG_CXD56_TESTSET),y) CMN_ASRCS += arm_testset.S @@ -33,14 +33,7 @@ CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_doirq.c arm_hardfault.c CMN_CSRCS += arm_svcall.c arm_vfork.c arm_switchcontext.c arm_puts.c -CMN_CSRCS += arm_tcbinfo.c - -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c +CMN_CSRCS += arm_tcbinfo.c arm_vectors.c ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c @@ -61,7 +54,6 @@ CMN_CSRCS += arm_checkstack.c endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/efm32/Make.defs b/arch/arm/src/efm32/Make.defs index 4a47269488..aa98ca4bfd 100644 --- a/arch/arm/src/efm32/Make.defs +++ b/arch/arm/src/efm32/Make.defs @@ -19,7 +19,7 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c @@ -29,14 +29,7 @@ CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_systemreset.c CMN_CSRCS += arm_trigger_irq.c arm_udelay.c arm_unblocktask.c arm_usestack.c arm_vfork.c -CMN_CSRCS += arm_switchcontext.c arm_puts.c arm_tcbinfo.c - -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c +CMN_CSRCS += arm_switchcontext.c arm_puts.c arm_tcbinfo.c arm_vectors.c ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c @@ -57,7 +50,6 @@ CMN_CSRCS += arm_checkstack.c endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/eoss3/Make.defs b/arch/arm/src/eoss3/Make.defs index 549b3fb97b..78bb4a150f 100644 --- a/arch/arm/src/eoss3/Make.defs +++ b/arch/arm/src/eoss3/Make.defs @@ -19,7 +19,7 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c @@ -29,14 +29,7 @@ CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_systemreset.c CMN_CSRCS += arm_trigger_irq.c arm_udelay.c arm_unblocktask.c arm_usestack.c arm_vfork.c -CMN_CSRCS += arm_switchcontext.c arm_puts.c arm_tcbinfo.c - -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c +CMN_CSRCS += arm_switchcontext.c arm_puts.c arm_tcbinfo.c arm_vectors.c ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index 68a0bfd519..bf3449ee0f 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -63,7 +63,7 @@ CMN_CSRCS += arm_doirq.c arm_gicv2.c arm_initialstate.c arm_mmu.c CMN_CSRCS += arm_prefetchabort.c arm_releasepending.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c arm_tcbinfo.c -CMN_CSRCS += arm_switchcontext.c +CMN_CSRCS += arm_switchcontext.c arm_cache.c ifeq ($(CONFIG_ARM_SEMIHOSTING_HOSTFS),y) CMN_CSRCS += arm_hostfs.c @@ -117,14 +117,11 @@ CMN_CSRCS += arm_virtpgaddr.c endif endif -CMN_CSRCS += arm_cache.c - ifeq ($(CONFIG_ARCH_L2CACHE),y) CMN_CSRCS += arm_l2cc_pl310.c endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs index 37f0ae6b91..6a79bdb70d 100644 --- a/arch/arm/src/imxrt/Make.defs +++ b/arch/arm/src/imxrt/Make.defs @@ -21,7 +21,7 @@ # Common ARM and Cortex-M7 files CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S CMN_CSRCS = arm_assert.c arm_blocktask.c CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c @@ -31,7 +31,7 @@ CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_doirq.c arm_hardfault.c CMN_CSRCS += arm_svcall.c arm_vfork.c arm_trigger_irq.c arm_systemreset.c -CMN_CSRCS += arm_switchcontext.c arm_puts.c arm_tcbinfo.c +CMN_CSRCS += arm_switchcontext.c arm_puts.c arm_tcbinfo.c arm_vectors.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += arm_backtrace_thumb.c @@ -41,15 +41,6 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -# Configuration-dependent common files - -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -71,7 +62,6 @@ endif CMN_CSRCS += arm_cache.c ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs index 0863ef844c..8342cd8b22 100644 --- a/arch/arm/src/kinetis/Make.defs +++ b/arch/arm/src/kinetis/Make.defs @@ -19,9 +19,9 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_mdelay.c arm_udelay.c arm_exit.c arm_initialize.c arm_memfault.c CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_modifyreg8.c CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasestack.c @@ -39,13 +39,6 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -75,7 +68,6 @@ endif endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/lc823450/Make.defs b/arch/arm/src/lc823450/Make.defs index e798b24cd4..588e4f8544 100644 --- a/arch/arm/src/lc823450/Make.defs +++ b/arch/arm/src/lc823450/Make.defs @@ -19,7 +19,7 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += vfork.S +CMN_ASRCS += vfork.S arm_exception.S CMN_CSRCS = arm_assert.c arm_blocktask.c CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c @@ -29,13 +29,7 @@ CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_systemreset.c CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_doirq.c arm_hardfault.c CMN_CSRCS += arm_svcall.c arm_vfork.c arm_trigger_irq.c arm_switchcontext.c -CMN_CSRCS += arm_puts.c arm_tcbinfo.c - -# CMN_CSRCS += up_dwt.c - -CMN_CSRCS += arm_stackframe.c -CMN_ASRCS += arm_exception.S -CMN_CSRCS += arm_vectors.c +CMN_CSRCS += arm_puts.c arm_tcbinfo.c arm_stackframe.c arm_vectors.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += arm_backtrace_thumb.c diff --git a/arch/arm/src/lpc17xx_40xx/Make.defs b/arch/arm/src/lpc17xx_40xx/Make.defs index c5552bc8a3..df62de2f2d 100644 --- a/arch/arm/src/lpc17xx_40xx/Make.defs +++ b/arch/arm/src/lpc17xx_40xx/Make.defs @@ -21,9 +21,9 @@ # Common ARM and Cortex-M3 files CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_mdelay.c arm_udelay.c arm_exit.c arm_initialize.c arm_memfault.c CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_modifyreg8.c CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c @@ -41,13 +41,6 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -73,7 +66,6 @@ endif endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs index 71a3582d7f..26000361a9 100644 --- a/arch/arm/src/lpc43xx/Make.defs +++ b/arch/arm/src/lpc43xx/Make.defs @@ -19,9 +19,9 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c @@ -31,13 +31,6 @@ CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_udelay.c CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_puts.c CMN_CSRCS += arm_tcbinfo.c -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -61,7 +54,6 @@ CMN_CSRCS += arm_checkstack.c endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs index 8b515c3837..92a335ceff 100644 --- a/arch/arm/src/lpc54xx/Make.defs +++ b/arch/arm/src/lpc54xx/Make.defs @@ -19,9 +19,9 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c @@ -31,13 +31,6 @@ CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_udelay.c CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_puts.c CMN_CSRCS += arm_tcbinfo.c -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -61,7 +54,6 @@ CMN_CSRCS += arm_checkstack.c endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/max326xx/Make.defs b/arch/arm/src/max326xx/Make.defs index f7bc59918f..303c859dfc 100644 --- a/arch/arm/src/max326xx/Make.defs +++ b/arch/arm/src/max326xx/Make.defs @@ -21,9 +21,9 @@ # Common ARMv7-M Source Files CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c +CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c arm_vectors.c CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c CMN_CSRCS += arm_mdelay.c arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c @@ -33,13 +33,6 @@ CMN_CSRCS += arm_stackframe.c arm_svcall.c arm_trigger_irq.c arm_unblocktask.c CMN_CSRCS += arm_udelay.c arm_usestack.c arm_vfork.c arm_switchcontext.c CMN_CSRCS += arm_puts.c arm_tcbinfo.c -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -59,7 +52,6 @@ CMN_CSRCS += arm_checkstack.c endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/nrf52/Make.defs b/arch/arm/src/nrf52/Make.defs index 887fc836a2..9a32a31b3f 100644 --- a/arch/arm/src/nrf52/Make.defs +++ b/arch/arm/src/nrf52/Make.defs @@ -19,9 +19,9 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S vfork.S +CMN_ASRCS += arm_testset.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_vectors.c CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c @@ -39,13 +39,6 @@ CMN_CSRCS += nrf52_tickless_rtc.c arm_mdelay.c endif endif -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -69,7 +62,6 @@ CMN_CSRCS += arm_stackcheck.c endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/rtl8720c/Make.defs b/arch/arm/src/rtl8720c/Make.defs index f0eca0b8dc..33948b19c1 100644 --- a/arch/arm/src/rtl8720c/Make.defs +++ b/arch/arm/src/rtl8720c/Make.defs @@ -26,11 +26,9 @@ CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_pthread_start.c CMN_CSRCS += arm_puts.c arm_releasestack.c arm_semi_syslog.c CMN_CSRCS += arm_stackframe.c arm_task_start.c arm_usestack.c arm_vfork.c -CMN_ASRCS += arm_exception.S - # arch/arm/src/armv8-m # -CMN_ASRCS += arm_fetchadd.S arm_fpu.S arm_setjmp.S +CMN_ASRCS += arm_exception.S arm_fetchadd.S arm_setjmp.S CMN_ASRCS += arm_fullcontextrestore.S arm_saveusercontext.S CMN_ASRCS += arm_testset.S vfork.S diff --git a/arch/arm/src/s32k1xx/s32k14x/Make.defs b/arch/arm/src/s32k1xx/s32k14x/Make.defs index e54d78855a..64942b1148 100644 --- a/arch/arm/src/s32k1xx/s32k14x/Make.defs +++ b/arch/arm/src/s32k1xx/s32k14x/Make.defs @@ -21,21 +21,14 @@ # Source files specific to the Cortex-M4F CMN_ASRCS += arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS += arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS += arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_initialstate.c arm_memfault.c CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c arm_schedulesigaction.c CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c arm_unblocktask.c CMN_CSRCS += arm_systemreset.c arm_switchcontext.c -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -45,10 +38,6 @@ CMN_CSRCS += arm_mpu.c arm_signal_dispatch.c CMN_UASRCS += arm_signal_handler.S endif -ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S -endif - # Source file specific to the S32k11x family CHIP_CSRCS += s32k14x_irq.c s32k14x_clrpend.c s32k14x_clockmapping.c diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs index a390e7a26f..412112dd04 100644 --- a/arch/arm/src/sam34/Make.defs +++ b/arch/arm/src/sam34/Make.defs @@ -23,9 +23,9 @@ # Common ARM and Cortex-M3 files CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c @@ -43,13 +43,6 @@ endif # Configuration-dependent common files -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -65,7 +58,6 @@ CMN_UASRCS += arm_signal_handler.S endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs index e6657f9f81..c1fff66689 100644 --- a/arch/arm/src/sama5/Make.defs +++ b/arch/arm/src/sama5/Make.defs @@ -62,7 +62,7 @@ CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_mmu.c arm_prefetchabort.c CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c arm_tcbinfo.c -CMN_CSRCS += arm_switchcontext.c +CMN_CSRCS += arm_switchcontext.c arm_cache.c # Configuration dependent C files @@ -103,10 +103,7 @@ CMN_CSRCS += arm_virtpgaddr.c endif endif -CMN_CSRCS += arm_cache.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/samd5e5/Make.defs b/arch/arm/src/samd5e5/Make.defs index afa67f1b42..d41549e18f 100644 --- a/arch/arm/src/samd5e5/Make.defs +++ b/arch/arm/src/samd5e5/Make.defs @@ -23,9 +23,9 @@ # Common ARM and Cortex-M4 files CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c +CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c arm_vectors.c CMN_CSRCS += arm_createstack.c arm_exit.c arm_initialize.c arm_initialstate.c CMN_CSRCS += arm_interruptcontext.c arm_mdelay.c arm_memfault.c arm_modifyreg8.c CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c @@ -37,13 +37,6 @@ CMN_CSRCS += arm_tcbinfo.c # Configuration-dependent common files -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -55,7 +48,6 @@ CMN_UASRCS += arm_signal_handler.S endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index 67d481e3b5..4d6a8f5796 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -24,9 +24,9 @@ # Common ARM and Cortex-M7 files CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_exit.c arm_hardfault.c arm_initialize.c arm_initialstate.c CMN_CSRCS += arm_interruptcontext.c arm_mdelay.c arm_udelay.c arm_systemreset.c CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c @@ -34,7 +34,7 @@ CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_usestack.c CMN_CSRCS += arm_doirq.c arm_vfork.c arm_switchcontext.c arm_puts.c -CMN_CSRCS += arm_tcbinfo.c +CMN_CSRCS += arm_tcbinfo.c arm_cache.c # Configuration-dependent common files @@ -50,17 +50,7 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - -CMN_CSRCS += arm_cache.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 0103951438..2269b1637f 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -19,9 +19,9 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_exit.c arm_hardfault.c arm_initialize.c arm_initialstate.c CMN_CSRCS += arm_interruptcontext.c arm_memfault.c arm_modifyreg8.c arm_mdelay.c CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c @@ -43,13 +43,6 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -69,7 +62,6 @@ CMN_CSRCS += arm_checkstack.c endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index f0178c78cf..f5ff1992d6 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -24,9 +24,9 @@ # Common ARM and Cortex-M7 files CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c @@ -34,7 +34,7 @@ CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_unblocktask.c CMN_CSRCS += arm_udelay.c arm_usestack.c arm_vfork.c arm_switchcontext.c arm_puts.c -CMN_CSRCS += arm_tcbinfo.c +CMN_CSRCS += arm_tcbinfo.c arm_cache.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += arm_backtrace_thumb.c @@ -50,17 +50,7 @@ endif # Configuration-dependent common files -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - -CMN_CSRCS += arm_cache.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 78831a876a..66ffd09ab1 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -24,9 +24,9 @@ # Common ARM and Cortex-M7 files CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S vfork.S +CMN_ASRCS += arm_testset.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c @@ -34,7 +34,7 @@ CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c arm_svcall.c CMN_CSRCS += arm_systemreset.c arm_trigger_irq.c arm_udelay.c arm_unblocktask.c CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_puts.c -CMN_CSRCS += arm_tcbinfo.c arm_perf.c +CMN_CSRCS += arm_tcbinfo.c arm_cache.c arm_perf.c ifeq ($(CONFIG_ARMV7M_SYSTICK),y) CMN_CSRCS += arm_systick.c @@ -50,17 +50,7 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - -CMN_CSRCS += arm_cache.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 54d33c6084..db915f72b9 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -24,7 +24,7 @@ # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c @@ -34,7 +34,7 @@ CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_udelay.c CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_vfork.c arm_switchcontext.c -CMN_CSRCS += arm_puts.c arm_tcbinfo.c +CMN_CSRCS += arm_puts.c arm_tcbinfo.c arm_vectors.c # Configuration-dependent common files @@ -46,15 +46,7 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index 667fdf8476..5b22df68fb 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -29,9 +29,9 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c @@ -51,15 +51,7 @@ ifeq ($(CONFIG_ARMV8M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -ifeq ($(CONFIG_ARMV8M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/stm32u5/Make.defs b/arch/arm/src/stm32u5/Make.defs index 44c11dbba6..e06b1231ce 100644 --- a/arch/arm/src/stm32u5/Make.defs +++ b/arch/arm/src/stm32u5/Make.defs @@ -29,9 +29,9 @@ CMN_UASRCS = CMN_UCSRCS = CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c arm_puts.c @@ -51,15 +51,7 @@ ifeq ($(CONFIG_ARMV8M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -ifeq ($(CONFIG_ARMV8M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs index f4460dbbee..4d6f92e033 100644 --- a/arch/arm/src/tiva/Make.defs +++ b/arch/arm/src/tiva/Make.defs @@ -19,7 +19,7 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c @@ -29,7 +29,7 @@ CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_udelay.c CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_puts.c -CMN_CSRCS += arm_tcbinfo.c +CMN_CSRCS += arm_tcbinfo.c arm_vectors.c ifeq ($(CONFIG_ARM_SEMIHOSTING_HOSTFS),y) CMN_CSRCS += arm_hostfs.c @@ -39,16 +39,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CMN_CSRCS += tiva_idle.c endif -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) - CMN_ASRCS += arm_lazyexception.S -else - CMN_ASRCS += arm_exception.S -endif - -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_FPU),y) - CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/tms570/Make.defs b/arch/arm/src/tms570/Make.defs index 96662935ee..60f4177172 100644 --- a/arch/arm/src/tms570/Make.defs +++ b/arch/arm/src/tms570/Make.defs @@ -51,7 +51,7 @@ CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_prefetchabort.c CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c -CMN_CSRCS += arm_switchcontext.c +CMN_CSRCS += arm_switchcontext.c arm_cache.c # Configuration dependent C files @@ -69,10 +69,7 @@ ifeq ($(CONFIG_ARMV7R_L2CC_PL310),y) CMN_CSRCS += arm_l2cc_pl310.c endif -CMN_CSRCS += arm_cache.c - ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_CSRCS += arm_fpucmp.c endif diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs index 4d3830aa14..2bab5610dd 100644 --- a/arch/arm/src/xmc4/Make.defs +++ b/arch/arm/src/xmc4/Make.defs @@ -19,9 +19,9 @@ ############################################################################ CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S -CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S +CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S arm_exception.S -CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c +CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c CMN_CSRCS += arm_doirq.c arm_exit.c arm_initialize.c arm_initialstate.c CMN_CSRCS += arm_hardfault.c arm_interruptcontext.c arm_memfault.c arm_mdelay.c CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c @@ -38,13 +38,6 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) CMN_CSRCS += arm_stackcheck.c endif -ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) -CMN_ASRCS += arm_lazyexception.S -else -CMN_ASRCS += arm_exception.S -endif -CMN_CSRCS += arm_vectors.c - ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c endif @@ -74,7 +67,6 @@ endif endif ifeq ($(CONFIG_ARCH_FPU),y) -CMN_ASRCS += arm_fpu.S CMN_CSRCS += arm_fpuconfig.c CMN_CSRCS += arm_fpucmp.c endif diff --git a/boards/arm/imxrt/imxrt1050-evk/configs/knsh/defconfig b/boards/arm/imxrt/imxrt1050-evk/configs/knsh/defconfig index dc15959e07..386bc00b4a 100644 --- a/boards/arm/imxrt/imxrt1050-evk/configs/knsh/defconfig +++ b/boards/arm/imxrt/imxrt1050-evk/configs/knsh/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_ARM_MPU=y CONFIG_BOARD_LOOPSPERMSEC=104926 diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/knsh/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/knsh/defconfig index 28fcf72482..ba97882d44 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/knsh/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/knsh/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_ARM_MPU=y CONFIG_BOARD_LOOPSPERMSEC=104926 diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/knsh/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/knsh/defconfig index d44f5c937a..4a9e72fcad 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/knsh/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/knsh/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_ARM_MPU=y CONFIG_BOARD_LOOPSPERMSEC=104926 diff --git a/boards/arm/lpc43xx/bambino-200e/README.txt b/boards/arm/lpc43xx/bambino-200e/README.txt index a33fd3079e..dd79e55e37 100644 --- a/boards/arm/lpc43xx/bambino-200e/README.txt +++ b/boards/arm/lpc43xx/bambino-200e/README.txt @@ -109,7 +109,6 @@ ports. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y Bambino-200e Configuration Options ================================== diff --git a/boards/arm/lpc43xx/lpc4330-xplorer/README.txt b/boards/arm/lpc43xx/lpc4330-xplorer/README.txt index 11ee94643e..93633308ee 100644 --- a/boards/arm/lpc43xx/lpc4330-xplorer/README.txt +++ b/boards/arm/lpc43xx/lpc4330-xplorer/README.txt @@ -361,7 +361,6 @@ ports. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y LPC4330-Xplorer Configuration Options ===================================== diff --git a/boards/arm/lpc43xx/lpc4337-ws/README.txt b/boards/arm/lpc43xx/lpc4337-ws/README.txt index ed61251cfe..96cf0fcf78 100644 --- a/boards/arm/lpc43xx/lpc4337-ws/README.txt +++ b/boards/arm/lpc43xx/lpc4337-ws/README.txt @@ -400,7 +400,6 @@ ports. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y LPC4337-ws Configuration Options ===================================== diff --git a/boards/arm/lpc43xx/lpc4357-evb/README.txt b/boards/arm/lpc43xx/lpc4357-evb/README.txt index 72bdfca85c..463a93689c 100644 --- a/boards/arm/lpc43xx/lpc4357-evb/README.txt +++ b/boards/arm/lpc43xx/lpc4357-evb/README.txt @@ -397,7 +397,6 @@ ports. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y LPC4357-EVB Configuration Options ===================================== diff --git a/boards/arm/lpc43xx/lpc4370-link2/README.txt b/boards/arm/lpc43xx/lpc4370-link2/README.txt index d6fecc5d05..44daaf1328 100644 --- a/boards/arm/lpc43xx/lpc4370-link2/README.txt +++ b/boards/arm/lpc43xx/lpc4370-link2/README.txt @@ -400,7 +400,6 @@ ports. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y LPC4370-Link2 Configuration Options ===================================== diff --git a/boards/arm/max326xx/max32660-evsys/configs/nsh/defconfig b/boards/arm/max326xx/max32660-evsys/configs/nsh/defconfig index d0240f8fb3..583bd750d3 100644 --- a/boards/arm/max326xx/max32660-evsys/configs/nsh/defconfig +++ b/boards/arm/max326xx/max32660-evsys/configs/nsh/defconfig @@ -15,7 +15,6 @@ CONFIG_ARCH_CHIP_MAX326XX=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_BOARD_LOOPSPERMSEC=8192 CONFIG_BUILTIN=y diff --git a/boards/arm/samv7/same70-qmtech/configs/mcuboot-loader/defconfig b/boards/arm/samv7/same70-qmtech/configs/mcuboot-loader/defconfig index 81b43d2836..3ecef2333f 100644 --- a/boards/arm/samv7/same70-qmtech/configs/mcuboot-loader/defconfig +++ b/boards/arm/samv7/same70-qmtech/configs/mcuboot-loader/defconfig @@ -23,7 +23,6 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=51262 CONFIG_BOOT_MCUBOOT=y diff --git a/boards/arm/samv7/same70-qmtech/configs/mcuboot-slot-confirm/defconfig b/boards/arm/samv7/same70-qmtech/configs/mcuboot-slot-confirm/defconfig index 4fe7e2a845..62b49bd646 100644 --- a/boards/arm/samv7/same70-qmtech/configs/mcuboot-slot-confirm/defconfig +++ b/boards/arm/samv7/same70-qmtech/configs/mcuboot-slot-confirm/defconfig @@ -23,7 +23,6 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=51262 CONFIG_BUILTIN=y diff --git a/boards/arm/samv7/same70-qmtech/configs/nsh/defconfig b/boards/arm/samv7/same70-qmtech/configs/nsh/defconfig index 8b4dc914d9..29c7d78d19 100644 --- a/boards/arm/samv7/same70-qmtech/configs/nsh/defconfig +++ b/boards/arm/samv7/same70-qmtech/configs/nsh/defconfig @@ -26,7 +26,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARD_LOOPSPERMSEC=51262 CONFIG_BUILTIN=y CONFIG_FAT_LCNAMES=y diff --git a/boards/arm/samv7/same70-xplained/configs/adc/defconfig b/boards/arm/samv7/same70-xplained/configs/adc/defconfig index 43c01122a7..4c10f6ee9b 100644 --- a/boards/arm/samv7/same70-xplained/configs/adc/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/adc/defconfig @@ -31,7 +31,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/same70-xplained/configs/mcuboot-loader/defconfig b/boards/arm/samv7/same70-xplained/configs/mcuboot-loader/defconfig index 1c5570a36d..f583c7647c 100644 --- a/boards/arm/samv7/same70-xplained/configs/mcuboot-loader/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/mcuboot-loader/defconfig @@ -28,7 +28,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/same70-xplained/configs/mcuboot-slot-confirm/defconfig b/boards/arm/samv7/same70-xplained/configs/mcuboot-slot-confirm/defconfig index 12cc258f6e..477eaa40ba 100644 --- a/boards/arm/samv7/same70-xplained/configs/mcuboot-slot-confirm/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/mcuboot-slot-confirm/defconfig @@ -28,7 +28,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/same70-xplained/configs/mrf24j40-starhub/defconfig b/boards/arm/samv7/same70-xplained/configs/mrf24j40-starhub/defconfig index 0d408fc55c..27496368d1 100644 --- a/boards/arm/samv7/same70-xplained/configs/mrf24j40-starhub/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/mrf24j40-starhub/defconfig @@ -26,7 +26,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig b/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig index 0f89b0a0bb..d04c2718b5 100644 --- a/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig @@ -28,7 +28,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/same70-xplained/configs/nsh/defconfig b/boards/arm/samv7/same70-xplained/configs/nsh/defconfig index 9a51409932..af72bda2e6 100644 --- a/boards/arm/samv7/same70-xplained/configs/nsh/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/nsh/defconfig @@ -29,7 +29,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/same70-xplained/configs/pwm/defconfig b/boards/arm/samv7/same70-xplained/configs/pwm/defconfig index f2cc60be7e..a8a1bd34de 100644 --- a/boards/arm/samv7/same70-xplained/configs/pwm/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/pwm/defconfig @@ -29,7 +29,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/same70-xplained/configs/pysim/defconfig b/boards/arm/samv7/same70-xplained/configs/pysim/defconfig index 5fcceda26b..69f728c69a 100644 --- a/boards/arm/samv7/same70-xplained/configs/pysim/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/pysim/defconfig @@ -31,7 +31,6 @@ CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig b/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig index af4e782e15..5a3dfb7ebc 100644 --- a/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig @@ -30,7 +30,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STDARG_H=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/samv71-xult/configs/knsh/defconfig b/boards/arm/samv7/samv71-xult/configs/knsh/defconfig index 87a699b484..6876ef56cd 100644 --- a/boards/arm/samv7/samv71-xult/configs/knsh/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/knsh/defconfig @@ -29,7 +29,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_ARM_MPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y diff --git a/boards/arm/samv7/samv71-xult/configs/mcuboot-loader/defconfig b/boards/arm/samv7/samv71-xult/configs/mcuboot-loader/defconfig index 0f7a9afecf..139c330121 100644 --- a/boards/arm/samv7/samv71-xult/configs/mcuboot-loader/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mcuboot-loader/defconfig @@ -25,7 +25,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=51262 diff --git a/boards/arm/samv7/samv71-xult/configs/mcuboot-slot-confirm/defconfig b/boards/arm/samv7/samv71-xult/configs/mcuboot-slot-confirm/defconfig index 91665a2115..efb7d6c7ba 100644 --- a/boards/arm/samv7/samv71-xult/configs/mcuboot-slot-confirm/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mcuboot-slot-confirm/defconfig @@ -25,7 +25,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=51262 diff --git a/boards/arm/samv7/samv71-xult/configs/mcuboot-swap-test/defconfig b/boards/arm/samv7/samv71-xult/configs/mcuboot-swap-test/defconfig index 80521525d2..e489c7eb03 100644 --- a/boards/arm/samv7/samv71-xult/configs/mcuboot-swap-test/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mcuboot-swap-test/defconfig @@ -25,7 +25,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=51262 diff --git a/boards/arm/samv7/samv71-xult/configs/mcuboot-update-agent/defconfig b/boards/arm/samv7/samv71-xult/configs/mcuboot-update-agent/defconfig index 22562d645a..ad3d801a6b 100644 --- a/boards/arm/samv7/samv71-xult/configs/mcuboot-update-agent/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mcuboot-update-agent/defconfig @@ -27,7 +27,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/samv71-xult/configs/module/defconfig b/boards/arm/samv7/samv71-xult/configs/module/defconfig index d7b5985580..ce8d367614 100644 --- a/boards/arm/samv7/samv71-xult/configs/module/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/module/defconfig @@ -26,7 +26,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=51262 diff --git a/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig b/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig index 52a906f819..ae6f2e58c4 100644 --- a/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig @@ -27,7 +27,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig b/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig index 65d0fb8812..492d5ce145 100644 --- a/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig @@ -30,7 +30,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig b/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig index 09990555e0..b3a22cbef5 100644 --- a/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig @@ -28,7 +28,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/samv71-xult/configs/nsh/defconfig b/boards/arm/samv7/samv71-xult/configs/nsh/defconfig index 81d946ad04..1e4391969d 100644 --- a/boards/arm/samv7/samv71-xult/configs/nsh/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/nsh/defconfig @@ -29,7 +29,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig b/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig index ba00d20ffa..99be08f1f9 100644 --- a/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig @@ -32,7 +32,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/samv71-xult/configs/vnc/defconfig b/boards/arm/samv7/samv71-xult/configs/vnc/defconfig index 46f1328c57..8aa2fa8388 100644 --- a/boards/arm/samv7/samv71-xult/configs/vnc/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/vnc/defconfig @@ -29,7 +29,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig b/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig index 6337925e9a..dd6d454478 100644 --- a/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig @@ -29,7 +29,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig index dfcf89ac13..cbe3d8ec1c 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig +++ b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig @@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_ARMV7M_LIBM=y CONFIG_ARMV7M_MEMCPY=y CONFIG_DEBUG_FEATURES=y diff --git a/boards/arm/stm32/mikroe-stm32f4/README.txt b/boards/arm/stm32/mikroe-stm32f4/README.txt index ec7985e0e9..0d5faac62d 100644 --- a/boards/arm/stm32/mikroe-stm32f4/README.txt +++ b/boards/arm/stm32/mikroe-stm32f4/README.txt @@ -150,7 +150,6 @@ There are two version of the FPU support built into the STM32 port. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y MIO283QT-2/MIO283QT-9A ====================== diff --git a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig index 481b710b82..aaf47bfcd5 100644 --- a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig +++ b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F405RG=y CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARDCTL_IOCTL=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/stm3240g-eval/README.txt b/boards/arm/stm32/stm3240g-eval/README.txt index a11ca8ac40..de0ddb056e 100644 --- a/boards/arm/stm32/stm3240g-eval/README.txt +++ b/boards/arm/stm32/stm3240g-eval/README.txt @@ -176,7 +176,6 @@ There are two version of the FPU support built into the STM32 port. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y FSMC SRAM ========= diff --git a/boards/arm/stm32/stm32f3discovery/README.txt b/boards/arm/stm32/stm32f3discovery/README.txt index b5ccd2238b..0ed440b72c 100644 --- a/boards/arm/stm32/stm32f3discovery/README.txt +++ b/boards/arm/stm32/stm32f3discovery/README.txt @@ -110,7 +110,6 @@ There are two version of the FPU support built into the STM32 port. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y Debugging ========= diff --git a/boards/arm/stm32/stm32f429i-disco/README.txt b/boards/arm/stm32/stm32f429i-disco/README.txt index 4d212578d2..cd43d3c907 100644 --- a/boards/arm/stm32/stm32f429i-disco/README.txt +++ b/boards/arm/stm32/stm32f429i-disco/README.txt @@ -281,7 +281,6 @@ There are two version of the FPU support built into the STM32 port. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y FMC SDRAM ========= diff --git a/boards/arm/stm32/stm32f4discovery/README.txt b/boards/arm/stm32/stm32f4discovery/README.txt index 9c5cd21858..40c9824b95 100644 --- a/boards/arm/stm32/stm32f4discovery/README.txt +++ b/boards/arm/stm32/stm32f4discovery/README.txt @@ -334,7 +334,6 @@ There are two version of the FPU support built into the STM32 port. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y STM32F4DIS-BB ============= diff --git a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig index 346c91707f..8d23b40d5a 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig @@ -20,7 +20,6 @@ CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/README.txt b/boards/arm/stm32f7/stm32f746g-disco/README.txt index 51f1c89d85..7c6605c612 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/README.txt +++ b/boards/arm/stm32f7/stm32f746g-disco/README.txt @@ -172,7 +172,6 @@ There are two version of the FPU support built into the STM32 port. file: CONFIG_ARCH_FPU=y - CONFIG_ARMV7M_LAZYFPU=y STM32F746G-DISCO-specific Configuration Options =============================================== diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig index 6dbb80fe75..13d1173067 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig @@ -18,7 +18,6 @@ CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_DTCM=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=43103 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig index b3bd22898a..b510300550 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig @@ -19,7 +19,6 @@ CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_DTCM=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARD_LOOPSPERMSEC=43103 CONFIG_BUILTIN=y CONFIG_HAVE_CXX=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig index ee449cc203..9f41d573d6 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig @@ -19,7 +19,6 @@ CONFIG_ARMV7M_DCACHE=y CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y CONFIG_ARMV7M_DTCM=y CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=43103 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig index 33dffe75c8..500885637a 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig +++ b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_CHIP_STM32U5=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_TRUSTZONE_NONSECURE=y -CONFIG_ARMV8M_LAZYFPU=y CONFIG_ARMV8M_USEBASEPRI=y CONFIG_BOARD_LOOPSPERMSEC=4230 CONFIG_BUILTIN=y diff --git a/boards/arm/tiva/launchxl-cc1312r1/configs/nsh/defconfig b/boards/arm/tiva/launchxl-cc1312r1/configs/nsh/defconfig index 445bec41fb..b87a526d1f 100644 --- a/boards/arm/tiva/launchxl-cc1312r1/configs/nsh/defconfig +++ b/boards/arm/tiva/launchxl-cc1312r1/configs/nsh/defconfig @@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP_SIMPLELINK=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_ARMV7M_USEBASEPRI=y CONFIG_BOARD_LOOPSPERMSEC=8192 CONFIG_BUILTIN=y diff --git a/boards/arm/xmc4/xmc4500-relax/configs/nsh/defconfig b/boards/arm/xmc4/xmc4500-relax/configs/nsh/defconfig index 7597a3f2b7..df4306cdf6 100644 --- a/boards/arm/xmc4/xmc4500-relax/configs/nsh/defconfig +++ b/boards/arm/xmc4/xmc4500-relax/configs/nsh/defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_CHIP_XMC4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_AT24XX_ADDR=0x57 CONFIG_AT24XX_EXTENDED=y CONFIG_AT24XX_EXTSIZE=160 diff --git a/boards/arm/xmc4/xmc4700-relax/configs/nsh/defconfig b/boards/arm/xmc4/xmc4700-relax/configs/nsh/defconfig index 0e666f42f2..4d37e9a730 100644 --- a/boards/arm/xmc4/xmc4700-relax/configs/nsh/defconfig +++ b/boards/arm/xmc4/xmc4700-relax/configs/nsh/defconfig @@ -16,7 +16,6 @@ CONFIG_ARCH_CHIP_XMC4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARD_LOOPSPERMSEC=8000 CONFIG_BUILTIN=y CONFIG_DEBUG_NOOPT=y