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arch/stm32f7: Fix nxstyle errors

Browse source 
arch/arm/src/stm32f7/chip.h,
arch/arm/src/stm32f7/stm32_adc.h,
arch/arm/src/stm32f7/stm32_allocateheap.c,
arch/arm/src/stm32f7/stm32_bbsram.h,
arch/arm/src/stm32f7/stm32_can.h,
arch/arm/src/stm32f7/stm32_capture.c,
arch/arm/src/stm32f7/stm32_capture.h:

    * Fix nxstyle errors.
This commit is contained in:
Nathan Hartman 2021-01-31 12:27:30 -05:00 • committed by Abdelatif Guettouche
parent b0d611d3dc
commit d82cc3ccc6
7 changed files with 228 additions and 200 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

36
arch/arm/src/stm32f7/chip.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f7/chip.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
@ -31,19 +31,19 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware files
* should then include this file for the proper setup.
/* Include the memory map and the chip definitions file. Other chip
* hardware files should then include this file for the proper setup.
*/
#include <arch/irq.h>
@ -52,9 +52,9 @@
#include "hardware/stm32_memorymap.h"
/* If the common ARMv7-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported external
* interrupts which, for this architecture, is provided in the arch/stm32f7/chip.h
* header file.
* following definition in this file that provides the number of supported
* external interrupts which, for this architecture, is provided in the
* arch/stm32f7/chip.h header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
@ -64,20 +64,20 @@
#define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */
#define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_H */

31
arch/arm/src/stm32f7/stm32_adc.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f7/stm32_adc.h
*
* Copyright (C) 2009, 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -34,29 +34,30 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F7_STM32_ADC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/analog/adc.h>
#include "chip.h"
#include "hardware/stm32_adc.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
****************************************************************************/
/* Timer devices may be used for different purposes. One special purpose is to
* control periodic ADC sampling. If CONFIG_STM32F7_TIMn is defined then
* CONFIG_STM32F7_TIMn_ADC must also be defined to indicate that timer "n" is intended
* to be used for that purpose. Timers 1-6 and 8 may be used.
/* Configuration ************************************************************/
/* Timer devices may be used for different purposes. One special purpose is
* to control periodic ADC sampling. If CONFIG_STM32F7_TIMn is defined then
* CONFIG_STM32F7_TIMn_ADC must also be defined to indicate that timer "n"
* is intended to be used for that purpose. Timers 1-6 and 8 may be used.
*/
#ifndef CONFIG_STM32F7_TIM1
@ -721,13 +722,13 @@
# endif
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus

64
arch/arm/src/stm32f7/stm32_allocateheap.c
View file

@ -79,15 +79,16 @@
*
* CONFIG_STM32F7_FMC=y : Enables the FMC
* CONFIG_STM32F7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC.
* Either of these autoselects CONFIG_ARCH_HAVE_HEAP2
* Either of these autoselects
* CONFIG_ARCH_HAVE_HEAP2
* which is what we are interested in here.
* CONFIG_HEAP2_BASE : The base address of the external RAM in the FMC
* address space
* CONFIG_HEAP2_BASE : The base address of the external RAM in the
* FMC address space
* CONFIG_HEAP2_SIZE : The size of the external RAM in the FMC
* address space
* CONFIG_MM_REGIONS : Must be set to a large enough value to
* include the FMC external RAM (as determined by
* the rules provided below)
* include the FMC external RAM (as determined
* by the rules provided below)
*/
/* Set the start and end of SRAM1 and SRAM2 */
@ -121,9 +122,9 @@
# undef CONFIG_ARCH_HAVE_HEAP2
#endif
/* If FMC external RAM is going to be used as heap, then verify that the starting
* address and size of the external SRAM region has been provided in the
* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
/* If FMC external RAM is going to be used as heap, then verify that the
* starting address and size of the external SRAM region has been provided
* in the configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
*/
#ifdef CONFIG_ARCH_HAVE_HEAP2
@ -255,21 +256,24 @@ static inline void up_heap_color(FAR void *start, size_t size)
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
* .data region Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack Size determined by
* CONFIG_IDLETHREAD_STACKSIZE.
* Heap Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region. Size determined at link time.
* Kernel .bss region Size determined at link time.
* Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Kernel .data region Size determined at link time.
* Kernel .bss region Size determined at link time.
* Kernel IDLE thread stack Size determined by
* CONFIG_IDLETHREAD_STACKSIZE.
* Padding for alignment
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
* Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
* User heap. Extends to the end of SRAM.
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
* Kernel heap Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE.
* User heap Extends to the end of SRAM.
*
****************************************************************************/
@ -281,7 +285,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
@ -310,7 +315,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Allow user-mode access to the user heap memory */
stm32_mpu_uheap((uintptr_t)ubase, usize);
stm32_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
@ -343,7 +348,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
@ -385,34 +391,34 @@ void arm_addregion(void)
/* Allow user-mode access to the SRAM2 heap */
stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END-SRAM2_START);
stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
up_heap_color((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
/* Add the SRAM2 user heap region. */
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
#ifdef HAVE_DTCM
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the DTCM heap */
stm32_mpu_uheap((uintptr_t)DTCM_START, DTCM_END-DTCM_START);
stm32_mpu_uheap((uintptr_t)DTCM_START, DTCM_END - DTCM_START);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)DTCM_START, DTCM_END-DTCM_START);
up_heap_color((FAR void *)DTCM_START, DTCM_END - DTCM_START);
/* Add the DTCM user heap region. */
kumm_addregion((FAR void *)DTCM_START, DTCM_END-DTCM_START);
kumm_addregion((FAR void *)DTCM_START, DTCM_END - DTCM_START);
#endif
#ifdef CONFIG_ARCH_HAVE_HEAP2
@ -420,7 +426,7 @@ void arm_addregion(void)
/* Allow user-mode access to the FMC RAM user heap memory */
stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif

35
arch/arm/src/stm32f7/stm32_bbsram.h
View file

@ -91,7 +91,7 @@ struct bbsramd_s
{
uint8_t flags; /* The crc is valid and the file was closed */
uint8_t fileno; /* The minor number */
uint16_t len; /* Total Bytes in this file*/
uint16_t len; /* Total Bytes in this file */
struct timespec lastwrite; /* Last write time */
};
@ -111,6 +111,7 @@ extern "C"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Function: stm32_bbsraminitialize
*
@ -136,22 +137,22 @@ extern "C"
int stm32_bbsraminitialize(char *devpath, int *sizes);
/****************************************************************************
* Function: stm32_bbsram_savepanic
*
* Description:
* Saves the panic context in a previously allocated BBSRAM file
*
* Parameters:
* fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL
* context - Pointer to a any array of bytes to save
* length - The length of the data pointed to byt context
*
* Returned Value:
* Length saved or negated errno.
*
* Assumptions:
*
****************************************************************************/
* Function: stm32_bbsram_savepanic
*
* Description:
* Saves the panic context in a previously allocated BBSRAM file
*
* Parameters:
* fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL
* context - Pointer to a any array of bytes to save
* length - The length of the data pointed to byt context
*
* Returned Value:
* Length saved or negated errno.
*
* Assumptions:
*
****************************************************************************/
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length);

34
arch/arm/src/stm32f7/stm32_can.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32/stm32_can.h
*
* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
@ -31,14 +31,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32F7_CAN_H
#define __ARCH_ARM_SRC_STM32_STM32F7_CAN_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -47,11 +47,11 @@
#include <nuttx/can/can.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Configuration ********************************************************************/
/* Configuration ************************************************************/
#if defined(CONFIG_CAN) && (defined(CONFIG_STM32F7_CAN1) || \
defined(CONFIG_STM32F7_CAN2) || defined(CONFIG_STM32F7_CAN3))
@ -81,7 +81,8 @@
# define CONFIG_STM32F7_CAN_TSEG1 6
#endif
#if CONFIG_STM32F7_CAN_TSEG1 < 1 || CONFIG_STM32F7_CAN_TSEG1 > CAN_BTR_TSEG1_MAX
#if CONFIG_STM32F7_CAN_TSEG1 < 1 || \
CONFIG_STM32F7_CAN_TSEG1 > CAN_BTR_TSEG1_MAX
# error "CONFIG_STM32_CAN_TSEG1 is out of range"
#endif
@ -89,19 +90,20 @@
# define CONFIG_STM32F7_CAN_TSEG2 7
#endif
#if CONFIG_STM32F7_CAN_TSEG2 < 1 || CONFIG_STM32F7_CAN_TSEG2 > CAN_BTR_TSEG2_MAX
#if CONFIG_STM32F7_CAN_TSEG2 < 1 || \
CONFIG_STM32F7_CAN_TSEG2 > CAN_BTR_TSEG2_MAX
# error "CONFIG_STM32_CAN_TSEG2 is out of range"
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@ -112,9 +114,9 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_caninitialize

128
arch/arm/src/stm32f7/stm32_capture.c
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32/stm32_capture.c
*
* Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved.
@ -31,11 +31,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
@ -56,32 +56,37 @@
#include "stm32_gpio.h"
#include "stm32_capture.h"
/************************************************************************************
/****************************************************************************
* Private Types
************************************************************************************/
****************************************************************************/
/* Configuration ********************************************************************/
/* Configuration ************************************************************/
#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || defined(GPIO_TIM3_CH1IN) || \
defined(GPIO_TIM4_CH1IN) || defined(GPIO_TIM5_CH1IN) || defined(GPIO_TIM8_CH1IN) || \
defined(GPIO_TIM9_CH1IN) || defined(GPIO_TIM10_CH1IN) || defined(GPIO_TIM11_CH1IN) || \
defined(GPIO_TIM12_CH1IN) || defined(GPIO_TIM13_CH1IN) || defined(GPIO_TIM14_CH1IN)
#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || \
defined(GPIO_TIM3_CH1IN) || defined(GPIO_TIM4_CH1IN) || \
defined(GPIO_TIM5_CH1IN) || defined(GPIO_TIM8_CH1IN) || \
defined(GPIO_TIM9_CH1IN) || defined(GPIO_TIM10_CH1IN) || \
defined(GPIO_TIM11_CH1IN) || defined(GPIO_TIM12_CH1IN) || \
defined(GPIO_TIM13_CH1IN) || defined(GPIO_TIM14_CH1IN)
# define HAVE_CH1IN 1
#endif
#if defined(GPIO_TIM1_CH2IN) || defined(GPIO_TIM2_CH2IN) || defined(GPIO_TIM3_CH2IN) || \
defined(GPIO_TIM4_CH2IN) || defined(GPIO_TIM5_CH2IN) || defined(GPIO_TIM8_CH2IN) || \
#if defined(GPIO_TIM1_CH2IN) || defined(GPIO_TIM2_CH2IN) || \
defined(GPIO_TIM3_CH2IN) || defined(GPIO_TIM4_CH2IN) || \
defined(GPIO_TIM5_CH2IN) || defined(GPIO_TIM8_CH2IN) || \
defined(GPIO_TIM9_CH2IN) || defined(GPIO_TIM12_CH2IN)
# define HAVE_CH2IN 1
#endif
#if defined(GPIO_TIM1_CH3IN) || defined(GPIO_TIM2_CH3IN) || defined(GPIO_TIM3_CH3IN) || \
defined(GPIO_TIM4_CH3IN) || defined(GPIO_TIM5_CH3IN) || defined(GPIO_TIM8_CH3IN)
#if defined(GPIO_TIM1_CH3IN) || defined(GPIO_TIM2_CH3IN) || \
defined(GPIO_TIM3_CH3IN) || defined(GPIO_TIM4_CH3IN) || \
defined(GPIO_TIM5_CH3IN) || defined(GPIO_TIM8_CH3IN)
# define HAVE_CH3IN 1
#endif
#if defined(GPIO_TIM1_CH4IN) || defined(GPIO_TIM2_CH4IN) || defined(GPIO_TIM3_CH4IN) || \
defined(GPIO_TIM4_CH4IN) || defined(GPIO_TIM5_CH4IN) || defined(GPIO_TIM8_CH4IN)
#if defined(GPIO_TIM1_CH4IN) || defined(GPIO_TIM2_CH4IN) || \
defined(GPIO_TIM3_CH4IN) || defined(GPIO_TIM4_CH4IN) || \
defined(GPIO_TIM5_CH4IN) || defined(GPIO_TIM8_CH4IN)
# define HAVE_CH4IN 1
#endif
@ -96,20 +101,26 @@
# define USE_EXT_CLOCK 1
#endif
/* This module then only compiles if there are enabled timers that are not intended
* for some other purpose.
/* This module then only compiles if there are enabled timers that are not
* intended for some other purpose.
*/
#if defined(CONFIG_STM32F7_TIM1_CAP) || defined(CONFIG_STM32F7_TIM2_CAP) || \
defined(CONFIG_STM32F7_TIM3_CAP) || defined(CONFIG_STM32F7_TIM4_CAP) || \
defined(CONFIG_STM32F7_TIM5_CAP) || defined(CONFIG_STM32F7_TIM8_CAP) || \
defined(CONFIG_STM32F7_TIM9_CAP) || defined(CONFIG_STM32F7_TIM10_CAP) || \
defined(CONFIG_STM32F7_TIM11_CAP) || defined(CONFIG_STM32F7_TIM12_CAP) || \
defined(CONFIG_STM32F7_TIM13_CAP) || defined(CONFIG_STM32F7_TIM14_CAP)
#if defined(CONFIG_STM32F7_TIM1_CAP) || \
defined(CONFIG_STM32F7_TIM2_CAP) || \
defined(CONFIG_STM32F7_TIM3_CAP) || \
defined(CONFIG_STM32F7_TIM4_CAP) || \
defined(CONFIG_STM32F7_TIM5_CAP) || \
defined(CONFIG_STM32F7_TIM8_CAP) || \
defined(CONFIG_STM32F7_TIM9_CAP) || \
defined(CONFIG_STM32F7_TIM10_CAP) || \
defined(CONFIG_STM32F7_TIM11_CAP) || \
defined(CONFIG_STM32F7_TIM12_CAP) || \
defined(CONFIG_STM32F7_TIM13_CAP) || \
defined(CONFIG_STM32F7_TIM14_CAP)
/************************************************************************************
/****************************************************************************
* Private Types
************************************************************************************/
****************************************************************************/
/* TIM Device Structure */
@ -126,14 +137,14 @@ struct stm32_cap_priv_s
#endif
};
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
/* Get a 16-bit register value by offset */
static inline uint16_t stm32_getreg16(FAR const struct stm32_cap_priv_s *priv,
uint8_t offset)
static inline uint16_t
stm32_getreg16(FAR const struct stm32_cap_priv_s *priv, uint8_t offset)
{
return getreg16(priv->base + offset);
}
@ -159,8 +170,8 @@ static inline void stm32_modifyreg16(FAR const struct stm32_cap_priv_s *priv,
* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2 and TIM5.
*/
static inline uint32_t stm32_getreg32(FAR const struct stm32_cap_priv_s *priv,
uint8_t offset)
static inline uint32_t
stm32_getreg32(FAR const struct stm32_cap_priv_s *priv, uint8_t offset)
{
return getreg32(priv->base + offset);
}
@ -175,12 +186,12 @@ static inline void stm32_putreg32(FAR const struct stm32_cap_priv_s *priv,
putreg32(value, priv->base + offset);
}
/************************************************************************************
/****************************************************************************
* gpio Functions
************************************************************************************/
****************************************************************************/
static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
int channel)
static inline uint32_t
stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv, int channel)
{
switch (priv->base)
{
@ -320,7 +331,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
/* TIM6 and TIM7 cannot be used in capture */
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32F7_TIM8_CAP
case STM32_TIM8_BASE:
@ -518,6 +529,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
}
return 0;
}
@ -622,12 +634,14 @@ static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv,
return OK;
}
/************************************************************************************
* Basic Functions
************************************************************************************/
static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t clk,
uint32_t prescaler, uint32_t max)
/****************************************************************************
* Basic Functions
****************************************************************************/
static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev,
stm32_cap_clk_t clk, uint32_t prescaler,
uint32_t max)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint16_t regval = 0;
@ -730,6 +744,7 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler,
irq_detach(irq_of);
}
#endif
return OK;
}
@ -901,15 +916,14 @@ static stm32_cap_flags_t stm32_cap_getflags(FAR struct stm32_cap_dev_s *dev)
}
return flags;
}
/************************************************************************************
/****************************************************************************
* General Functions
************************************************************************************/
****************************************************************************/
static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel,
stm32_cap_ch_cfg_t cfg)
static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev,
uint8_t channel, stm32_cap_ch_cfg_t cfg)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint32_t gpio = 0;
@ -979,7 +993,8 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel
/* Set ccmr */
regval = cfg;
mask = (GTIM_CCMR1_IC1F_MASK | GTIM_CCMR1_IC1PSC_MASK | GTIM_CCMR1_CC1S_MASK);
mask = (GTIM_CCMR1_IC1F_MASK | GTIM_CCMR1_IC1PSC_MASK |
GTIM_CCMR1_CC1S_MASK);
regval &= mask;
if (channel & 1)
@ -1014,7 +1029,8 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel
return OK;
}
static uint32_t stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, uint8_t channel)
static uint32_t stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev,
uint8_t channel)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint32_t offset;
@ -1058,15 +1074,15 @@ static uint32_t stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, uint8_t ch
return stm32_getreg16(priv, offset);
}
/************************************************************************************
/****************************************************************************
* Advanced Functions
************************************************************************************/
****************************************************************************/
/* TODO: Advanced functions for the STM32_ATIM */
/************************************************************************************
/****************************************************************************
* Device Structures, Instantiation
************************************************************************************/
****************************************************************************/
struct stm32_cap_ops_s stm32_cap_ops =
{
@ -1285,9 +1301,9 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer)
return NULL;
}
/************************************************************************************
/****************************************************************************
* Public Function - Initialization
************************************************************************************/
****************************************************************************/
FAR struct stm32_cap_dev_s *stm32_cap_init(int timer)
{

100
arch/arm/src/stm32f7/stm32_capture.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32/stm32_capture.h
*
* Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved.
@ -31,14 +31,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_CAPTURE_H
#define __ARCH_ARM_SRC_STM32F7_STM32_CAPTURE_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -46,10 +46,11 @@
#include <arch/board/board.h>
#include "hardware/stm32_tim.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Helpers **************************************************************************/
****************************************************************************/
/* Helpers ******************************************************************/
#define STM32_CAP_SETCLOCK(d,clk_src,psc,max) ((d)->ops->setclock(d,clk_src,psc,max))
#define STM32_CAP_SETCHANNEL(d,ch,cfg) ((d)->ops->setchannel(d,ch,cfg))
@ -59,9 +60,9 @@
#define STM32_CAP_ACKFLAGS(d,f) ((d)->ops->ackflags(d,f))
#define STM32_CAP_GETFLAGS(d) ((d)->ops->getflags(d))
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@ -90,61 +91,60 @@ typedef enum
STM32_CAP_MAPPED_MASK = (GTIM_CCMR1_CC1S_MASK),
STM32_CAP_MAPPED_TI1 = (GTIM_CCMR_CCS_CCIN1),
STM32_CAP_MAPPED_TI2 = (GTIM_CCMR_CCS_CCIN2),
/*TODO STM32_CAP_MAPPED_TRC = (GTIM_CCMR_CCS_CCINTRC), */
/* TODO: STM32_CAP_MAPPED_TRC = (GTIM_CCMR_CCS_CCINTRC), */
/* Event prescaler */
STM32_CAP_INPSC_MASK = (GTIM_CCMR1_IC1PSC_MASK),
STM32_CAP_INPSC_NO = (0<<GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_2EVENTS = (1<<GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_4EVENTS = (2<<GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_8EVENTS = (3<<GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_NO = (0 << GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_2EVENTS = (1 << GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_4EVENTS = (2 << GTIM_CCMR1_IC1PSC_SHIFT),
STM32_CAP_INPSC_8EVENTS = (3 << GTIM_CCMR1_IC1PSC_SHIFT),
/* Event prescaler */
STM32_CAP_FILTER_MASK = (GTIM_CCMR1_IC1F_MASK),
STM32_CAP_FILTER_NO = (0<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_NO = (0 << GTIM_CCMR1_IC1F_SHIFT),
/* Internal clock with N time to confirm event */
STM32_CAP_FILTER_INT_N2 = (1<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_INT_N4 = (2<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_INT_N8 = (3<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_INT_N2 = (1 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_INT_N4 = (2 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_INT_N8 = (3 << GTIM_CCMR1_IC1F_SHIFT),
/* DTS clock div by D with N time to confirm event */
STM32_CAP_FILTER_DTS_D2_N6 = (4<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D2_N8 = (5<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D4_N6 = (6<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D4_N8 = (7<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D8_N6 = (8<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D8_N8 = (9<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D16_N5 = (10<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D16_N6 = (11<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D16_N8 = (12<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D32_N5 = (13<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D32_N6 = (14<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D32_N8 = (15<<GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D2_N6 = (4 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D2_N8 = (5 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D4_N6 = (6 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D4_N8 = (7 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D8_N6 = (8 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D8_N8 = (9 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D16_N5 = (10 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D16_N6 = (11 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D16_N8 = (12 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D32_N5 = (13 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D32_N6 = (14 << GTIM_CCMR1_IC1F_SHIFT),
STM32_CAP_FILTER_DTS_D32_N8 = (15 << GTIM_CCMR1_IC1F_SHIFT),
/* EDGE */
STM32_CAP_EDGE_MASK = (3<<8),
STM32_CAP_EDGE_DISABLED = (0<<8),
STM32_CAP_EDGE_RISING = (1<<8),
STM32_CAP_EDGE_FALLING = (2<<8),
STM32_CAP_EDGE_BOTH = (3<<8),
STM32_CAP_EDGE_MASK = (3 << 8),
STM32_CAP_EDGE_DISABLED = (0 << 8),
STM32_CAP_EDGE_RISING = (1 << 8),
STM32_CAP_EDGE_FALLING = (2 << 8),
STM32_CAP_EDGE_BOTH = (3 << 8),
} stm32_cap_ch_cfg_t;
/* Capture clock sources */
typedef enum
{
STM32_CAP_CLK_INT= 0,
STM32_CAP_CLK_INT = 0,
STM32_CAP_CLK_EXT,
/* TODO: Add other clock */
} stm32_cap_clk_t;
/* Capture flags */
@ -164,29 +164,31 @@ typedef enum
STM32_CAP_FLAG_OF_CH_2 = (GTIM_SR_CC2OF),
STM32_CAP_FLAG_OF_CH_3 = (GTIM_SR_CC3OF),
STM32_CAP_FLAG_OF_CH_4 = (GTIM_SR_CC4OF)
} stm32_cap_flags_t;
#define STM32_CAP_FLAG_IRQ_CH(ch) (GTIM_SR_CC1IF<<((ch)-1))
#define STM32_CAP_FLAG_OF_CH(ch) (GTIM_SR_CC1OF<<((ch)-1))
#define STM32_CAP_FLAG_IRQ_CH(ch) (GTIM_SR_CC1IF << ((ch) - 1))
#define STM32_CAP_FLAG_OF_CH(ch) (GTIM_SR_CC1OF << ((ch) - 1))
#define STM32_CAP_CHANNEL_COUNTER 0
/* Capture Operations */
struct stm32_cap_ops_s
{
int (*setclock)( FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t clk, uint32_t prescaler, uint32_t max);
int (*setchannel)(FAR struct stm32_cap_dev_s *dev, uint8_t channel, stm32_cap_ch_cfg_t cfg);
int (*setclock)(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t clk,
uint32_t prescaler, uint32_t max);
int (*setchannel)(FAR struct stm32_cap_dev_s *dev, uint8_t channel,
stm32_cap_ch_cfg_t cfg);
uint32_t (*getcapture)(FAR struct stm32_cap_dev_s *dev, uint8_t channel);
int (*setisr)(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, void *arg);
void (*enableint)( FAR struct stm32_cap_dev_s *dev, stm32_cap_flags_t src, bool on );
void (*ackflags)( FAR struct stm32_cap_dev_s *dev, int flags);
int (*setisr)(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, void *arg);
void (*enableint)(FAR struct stm32_cap_dev_s *dev, stm32_cap_flags_t src,
bool on);
void (*ackflags)(FAR struct stm32_cap_dev_s *dev, int flags);
stm32_cap_flags_t (*getflags)(FAR struct stm32_cap_dev_s *dev);
};
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/* Power-up timer and get its structure */