From d8ea955d6942ce6a22e7b2eb9acba62e489f5ff2 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 8 Jun 2016 08:26:26 -0600 Subject: [PATCH] Added STM32FF76xxx and STM32FF7xx families --- ChangeLog | 2 + arch/arm/include/stm32f7/chip.h | 297 +++- arch/arm/include/stm32f7/irq.h | 2 + arch/arm/include/stm32f7/stm32f76xx77xx_irq.h | 215 +++ arch/arm/src/stm32f7/Kconfig | 1043 ++++++++++++- arch/arm/src/stm32f7/chip/stm32_dma.h | 5 +- arch/arm/src/stm32f7/chip/stm32_ethernet.h | 8 +- arch/arm/src/stm32f7/chip/stm32_exti.h | 8 +- arch/arm/src/stm32f7/chip/stm32_flash.h | 5 +- arch/arm/src/stm32f7/chip/stm32_gpio.h | 5 +- arch/arm/src/stm32f7/chip/stm32_memorymap.h | 5 +- arch/arm/src/stm32f7/chip/stm32_pinmap.h | 7 +- arch/arm/src/stm32f7/chip/stm32_pwr.h | 5 +- arch/arm/src/stm32f7/chip/stm32_rcc.h | 6 +- arch/arm/src/stm32f7/chip/stm32_syscfg.h | 5 +- arch/arm/src/stm32f7/chip/stm32_uart.h | 9 +- .../arm/src/stm32f7/chip/stm32f74xx75xx_dma.h | 18 +- .../src/stm32f7/chip/stm32f74xx75xx_flash.h | 86 +- .../src/stm32f7/chip/stm32f74xx75xx_gpio.h | 16 - .../stm32f7/chip/stm32f74xx75xx_memorymap.h | 7 +- .../src/stm32f7/chip/stm32f74xx75xx_pinmap.h | 5 +- .../arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h | 6 +- ...f74xx75xx_uart.h => stm32f74xx77xx_uart.h} | 14 +- .../arm/src/stm32f7/chip/stm32f76xx77xx_dma.h | 593 ++++++++ .../src/stm32f7/chip/stm32f76xx77xx_flash.h | 219 +++ .../src/stm32f7/chip/stm32f76xx77xx_gpio.h | 404 +++++ .../stm32f7/chip/stm32f76xx77xx_memorymap.h | 214 +++ .../src/stm32f7/chip/stm32f76xx77xx_pinmap.h | 1343 +++++++++++++++++ .../arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h | 159 ++ .../arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h | 737 +++++++++ .../src/stm32f7/chip/stm32f76xx77xx_syscfg.h | 180 +++ arch/arm/src/stm32f7/stm32_dma.c | 3 +- arch/arm/src/stm32f7/stm32_dumpgpio.c | 3 +- arch/arm/src/stm32f7/stm32_exti_gpio.c | 3 +- arch/arm/src/stm32f7/stm32_gpio.c | 3 +- arch/arm/src/stm32f7/stm32_rcc.c | 5 +- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 886 +++++++++++ 37 files changed, 6335 insertions(+), 196 deletions(-) create mode 100644 arch/arm/include/stm32f7/stm32f76xx77xx_irq.h rename arch/arm/src/stm32f7/chip/{stm32f74xx75xx_uart.h => stm32f74xx77xx_uart.h} (98%) create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h create mode 100644 arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c diff --git a/ChangeLog b/ChangeLog index b3ea24e379..791c59947d 100755 --- a/ChangeLog +++ b/ChangeLog @@ -11919,6 +11919,8 @@ * include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to _sa_handler_t. They type void does not work with the IAR toolchain. From Aleksandr Vyhovanec (2016-06-07). + * arch/arm/src/stm32f7 and include/stm32f7: Added STM32FF76xxx and + STM32FF7xx families. From David Sidrane (2016-06-08). * Refactoring configs/nucleo-144 sub-directories to support additional nucleo-144 board. Add support for the Nucleo-F767ZI board. From David Sidrane (2016-06-08). diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 372bd1143f..d30937541e 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/include/stm32f7/chip.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,99 +45,272 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* STM32F745xx, STM32F746xx, and STM32F56xx. Differences between family members: +/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx, + * STM32F769xx, STM32F777xx and STM32F779xx Differences between family members: * - * ----------- ---------------- ----- -------- ------------ -------- - * PART PACKAGE GPIOs SPI/I2S ADC CHANNELS LCD-TFT? - * ----------- ---------------- ----- -------- ------------ -------- - * STM32F745Vx LQFP100 82 4/3 16 No - * STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No - * STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No - * STM32F745Bx LQFP208 168 6/3 24 No - * STM32F745Nx TFBGA216 68 6/3 24 No + * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------ + * SPI ADC LCD + * PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1 + * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------ + * STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F745Bx LQFP208 168 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F745Nx TFBGA216 68 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 * - * STM32F746Vx LQFP100 82 4/3 16 Yes - * STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes - * STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes - * STM32F746Bx LQFP208 168 6/3 24 Yes - * STM32F746Nx TFBGA216 168 6/3 24 Yes + * STM32F746Vx LQFP100 82 4/3 16 Yes No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F746Bx LQFP208 168 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F746Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No No SFPU * - * STM32F756Vx LQFP100 82 4/3 16 Yes - * STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes - * STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes - * STM32F756Bx LQFP208 168 6/3 24 Yes - * STM32F756Nx TFBGA216 168 6/3 24 Yes - * ----------- ---------------- ----- -------- ------------ -------- + * STM32F756Vx LQFP100 82 4/3 16 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * STM32F756Bx LQFP208 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * STM32F756Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * + * STM32F765Vx LQFP100 82 4/3 16 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F765Zx WLCSP143/LQFP144 114 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F765Ix UFBGA176/LQFP176 140 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F765Bx LQFP208 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F765Nx TFBGA216 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * + * STM32F767Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F767Zx WLCSP143/LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F767Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F767Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F767Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * + * STM32F768Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16 + * + * STM32F769Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F769Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F769Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F769Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F769Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * + * STM32F769Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16 + * + * STM32F777Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F777Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F777Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F777Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F777Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * + * STM32F778Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16 + * + * STM32F779Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F779Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F779Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + + * STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16 + * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------ * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH + * Parts STM32F74xxI have 2048Kb of FLASH + * + * The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x or overridden + * with CONFIG_STM32F7_FLASH_OVERRIDE_x * - * The correct FLASH size must be set with a CONFIG_STM32F7_FLASH_*KB - * selection. */ - -#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \ - defined(CONFIG_ARCH_CHIP_STM32F756) - -#if defined(CONFIG_ARCH_CHIP_STM32F745) -# define STM32F7_STM32F745XX 1 /* STM32F745xx family */ -# undef STM32F7_STM32F746XX /* Not STM32F746xx family */ -# undef STM32F7_STM32F756XX /* Not STM32F756xx family */ - -# define STM32F7_NLCDTFT 0 /* No LCD-TFT */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F746) - -# undef STM32F7_STM32F745XX /* Not STM32F745xx family */ -# define STM32F7_STM32F746XX 1 /* STM32F746xx family */ -# undef STM32F7_STM32F756XX /* Not STM32F756xx family */ - -# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ - -#else /* if defined(CONFIG_ARCH_CHIP_STM32F746) */ - -# undef STM32F7_STM32F745XX /* Not STM32F745xx family */ -# undef STM32F7_STM32F746XX /* Not STM32F746xx family */ -# define STM32F7_STM32F756XX 1 /* STM32F756xx family */ - -# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ +#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F745VE) || \ + defined(CONFIG_ARCH_CHIP_STM32F745IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F745IE) || \ + defined(CONFIG_ARCH_CHIP_STM32F745ZE) || \ + defined(CONFIG_ARCH_CHIP_STM32F745ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746VE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746BE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746IE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746NE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746ZE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F765VI) || \ + defined(CONFIG_ARCH_CHIP_STM32F765VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765BI) || \ + defined(CONFIG_ARCH_CHIP_STM32F765NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765ZI) || \ + defined(CONFIG_ARCH_CHIP_STM32F765IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765II) || \ + defined(CONFIG_ARCH_CHIP_STM32F767NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F767VI) || \ + defined(CONFIG_ARCH_CHIP_STM32F767BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767ZI) || \ + defined(CONFIG_ARCH_CHIP_STM32F767II) || \ + defined(CONFIG_ARCH_CHIP_STM32F769BI) || \ + defined(CONFIG_ARCH_CHIP_STM32F769II) || \ + defined(CONFIG_ARCH_CHIP_STM32F769BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F769NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F769AI) || \ + defined(CONFIG_ARCH_CHIP_STM32F769NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F769IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F777ZI) || \ + defined(CONFIG_ARCH_CHIP_STM32F777VI) || \ + defined(CONFIG_ARCH_CHIP_STM32F777NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F777BI) || \ + defined(CONFIG_ARCH_CHIP_STM32F777II) || \ + defined(CONFIG_ARCH_CHIP_STM32F778AI) || \ + defined(CONFIG_ARCH_CHIP_STM32F779II) || \ + defined(CONFIG_ARCH_CHIP_STM32F779NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F779BI) || \ + defined(CONFIG_ARCH_CHIP_STM32F779AI) +#else +# error STM32 F7 chip not identified #endif -# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM inerface */ -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM inerface */ +/* Size SRAM */ + +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ +# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# if defined(CONFIG_ARMV7M_HAVE_DTCM) +# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# else +# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# endif +# if defined(CONFIG_ARMV7M_HAVE_ITCM) +# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# else +# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# endif +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77X) +# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ +# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# if defined(CONFIG_ARMV7M_HAVE_DTCM) +# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# else +# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# endif +# if defined(CONFIG_ARMV7M_HAVE_ITCM) +# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# else +# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# endif +#else +# error STM32 F7 chip Family not identified +#endif + +/* Common to all Family members */ -# define STM32F7_NFSMC 1 /* Have FSMC memory controller */ -# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */ # define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ # define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ # define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ # define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32F7_NRNG 1 /* Random number generator (RNG) */ # define STM32F7_NUART 4 /* UART 4-5 and 7-8 */ # define STM32F7_NUSART 4 /* USART1-3 and 6 */ -# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */ # define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ # define STM32F7_NI2C 4 /* I2C1-4 */ # define STM32F7_NUSBOTGFS 1 /* USB OTG FS */ # define STM32F7_NUSBOTGHS 1 /* USB OTG HS */ -# define STM32F7_NCAN 2 /* CAN1-2 */ # define STM32F7_NSAI 2 /* SAI1-2 */ # define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ -# define STM32F7_NSDMMC 1 /* SDMMC interface */ -# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ # define STM32F7_NDMA 2 /* DMA1-2 */ -# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ # define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ # define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */ # define STM32F7_NDAC 2 /* 12-bit DAC1-2 */ # define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32F7_NCRC 1 /* CRC */ +/* TBD FPU Configuration */ + +#if defined(CONFIG_ARCH_HAVE_FPU) #else -# error STM32 F7 chip not identified +#endif + +#if defined(CONFIG_ARCH_HAVE_DPFPU) +#else +#endif + +/* Diversification based on Family and package */ + +#if defined(CONFIG_STM32F7_HAVE_FSMC) +# define STM32F7_NFSMC 1 /* Have FSMC memory controller */ +#else +# define STM32F7_NFSMC 0 /* No FSMC memory controller */ +#endif +#if defined(CONFIG_STM32F7_HAVE_ETHRNET) +# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */ +#else +# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +#endif +#if defined(CONFIG_STM32F7_HAVE_RNG) +# define STM32F7_NRNG 1 /* Random number generator (RNG) */ +#else +# define STM32F7_NRNG 0 /* No Random number generator (RNG) */ +#endif +#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) +# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */ +#else +# define STM32F7_NSPI 4 /* SPI1-4 V series */ +#endif +#if defined(CONFIG_STM32F7_HAVE_SDMMC2) +# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */ +#else +# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */ +#endif +#if defined(CONFIG_STM32F7_HAVE_CAN3) +# define STM32F7_NCAN 3 /* CAN1-3 */ +#else +# define STM32F7_NCAN 2 /* CAN1-2 */ +#endif +#if defined(CONFIG_STM32F7_HAVE_DCMI) +# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ +#else +# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */ +#endif +#if defined(CONFIG_STM32F7_HAVE_DSIHOST) +# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */ +#else +# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */ +#endif +#if defined (CONFIG_STM32F7_HAVE_LTDC) +# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ +#else +# define STM32F7_NLCDTFT 0 /* No LCD-TFT */ +#endif +#if defined(CONFIG_STM32F7_HAVE_DMA2D) +# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ +#else +# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ +#endif +#if defined(CONFIG_STM32F7_HAVE_JPEG) +#define STM32F7_NJPEG 1 /* One JPEG Converter */ +#else +#define STM32F7_NJPEG 0 /* No JPEG Converter */ +#endif +#if defined(CONFIG_STM32F7_HAVE_CRYP) +#define STM32F7_NCRYP 1 /* One CRYP engine */ +#else +#define STM32F7_NCRYP 0 /* No CRYP engine */ +#endif +#if defined(CONFIG_STM32F7_HAVE_HASH) +#define STM32F7_NHASH 1 /* One HASH engine */ +#else +#define STM32F7_NHASH 0 /* No HASH engine */ +#endif +#if defined(CONFIG_STM32F7_HAVE_DFSDM) +#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */ +#else +#define STM32F7_NDFSDM 0 /* No Digital filters */ #endif /* NVIC priority levels *************************************************************/ diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h index 5a5c710803..205d06b644 100644 --- a/arch/arm/include/stm32f7/irq.h +++ b/arch/arm/include/stm32f7/irq.h @@ -78,6 +78,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include #else # error "Unsupported STM32 F7 chip" #endif diff --git a/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h new file mode 100644 index 0000000000..6c0461f9ef --- /dev/null +++ b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h @@ -0,0 +1,215 @@ +/**************************************************************************************************** + * arch/arm/include/stm32f7/stm32f76xx77xx_irq.h.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through arch/irq.h */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the + * NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found in the file + * nuttx/arch/arm/include/stm32f7/irq.h which includes this file + * + * External interrupts (vectors >= 16) + */ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */ +#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */ +#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */ +#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */ +#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */ +#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */ +#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */ +#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */ +#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */ +#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */ +#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */ +#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */ +#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */ +#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */ +#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */ +#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */ +#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */ +#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */ +#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */ +#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ +#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */ +#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ +#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */ +#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */ +#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ +#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */ +#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */ +#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */ +#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */ +#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */ +#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */ +#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */ +#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */ +#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */ +#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */ +#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST+98) /* 98: DSI host global interrupt */ +#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST+99) /* 99: DFSDM1 Filter 0 global interrupt */ +#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST+100) /* 100: DFSDM1 Filter 1 global interrupt */ +#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST+101) /* 101: DFSDM1 Filter 2 global interrupt */ +#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST+102) /* 102: DFSDM1 Filter 3 global interrupt */ +#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */ +#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST+104) /* 104: CAN3 TX interrupt */ +#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST+105) /* 105: CAN3 RX0 interrupt */ +#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST+106) /* 106: CAN3 RX1 interrupt */ +#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST+107) /* 107: CAN3 SCE interrupt */ +#define STM32_IRQ_JPEG (STM32_IRQ_FIRST+108) /* 108: JPEG global interrupt */ +#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST+109) /* 109: MDIO slave global interrupt */ + +#define NR_INTERRUPTS 110 +#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS) + +/* EXTI interrupts (Do not use IRQ numbers) */ + +#define NR_IRQS NR_VECTORS + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H */ diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index e3a8d2b42c..e77c028ec0 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -12,59 +12,915 @@ choice default ARCH_CHIP_STM32F746 depends on ARCH_CHIP_STM32F7 -config ARCH_CHIP_STM32F745 - bool "STM32F745xx" - select STM32F7_STM32F74XX +config ARCH_CHIP_STM32F745VG + bool "STM32F745VG" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V ---help--- - STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM -config ARCH_CHIP_STM32F746 - bool "STM32F746xx" - select STM32F7_STM32F74XX - select STM32F7_HAVE_LTDC +config ARCH_CHIP_STM32F745VE + bool "STM32F745VE" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_V ---help--- - STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM + STM32 F7 Cortex M7, 512 320K FLASH, 320K (240+16+64) Kb SRAM -config ARCH_CHIP_STM32F756 - bool "STM32F756xx" - select STM32F7_STM32F75XX - select STM32F7_HAVE_LTDC +config ARCH_CHIP_STM32F745IG + bool "STM32F745IG" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I ---help--- - STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F745IE + bool "STM32F745IE" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F745ZE + bool "STM32F745ZE" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F745ZG + bool "STM32F745ZG" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746BG + bool "STM32F746BG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746VG + bool "STM32F746VG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746VE + bool "STM32F746VE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746BE + bool "STM32F746BE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746ZG + bool "STM32F746ZG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746IE + bool "STM32F746IE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746NG + bool "STM32F746NG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746NE + bool "STM32F746NE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746ZE + bool "STM32F746ZE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746IG + bool "STM32F746IG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756NG + bool "STM32F756NG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756BG + bool "STM32F756BG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756IG + bool "STM32F756IG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756VG + bool "STM32F756VG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756ZG + bool "STM32F756ZG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F765NI + bool "STM32F765NI" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765VI + bool "STM32F765VI" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765VG + bool "STM32F765VG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765BI + bool "STM32F765BI" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765NG + bool "STM32F765NG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765ZG + bool "STM32F765ZG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765ZI + bool "STM32F765ZI" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765IG + bool "STM32F765IG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765BG + bool "STM32F765BG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765II + bool "STM32F765II" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767NG + bool "STM32F767NG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767IG + bool "STM32F767IG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767VG + bool "STM32F767VG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767ZG + bool "STM32F767ZG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767NI + bool "STM32F767NI" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767VI + bool "STM32F767VI" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767BG + bool "STM32F767BG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767ZI + bool "STM32F767ZI" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767II + bool "STM32F767II" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769BI + bool "STM32F769BI" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769II + bool "STM32F769II" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769BG + bool "STM32F769BG" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769NI + bool "STM32F769NI" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769AI + bool "STM32F769AI" + select STM32F7_STM32F769AX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_A + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769NG + bool "STM32F769NG" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769IG + bool "STM32F769IG" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777ZI + bool "STM32F777ZI" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777VI + bool "STM32F777VI" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777NI + bool "STM32F777NI" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777BI + bool "STM32F777BI" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777II + bool "STM32F777II" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F778AI + bool "STM32F778AI" + select STM32F7_STM32F778AX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_A + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F779II + bool "STM32F779II" + select STM32F7_STM32F779XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F779NI + bool "STM32F779NI" + select STM32F7_STM32F779XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F779BI + bool "STM32F779BI" + select STM32F7_STM32F779XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F779AI + bool "STM32F779AI" + select STM32F7_STM32F779XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_A + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM endchoice # STM32 F7 Chip Selection config STM32F7_STM32F74XX bool default n - select ARCH_HAVE_FPU - select ARCH_HAVE_DPFPU # REVISIT - select ARMV7M_HAVE_ICACHE - select ARMV7M_HAVE_DCACHE - select ARMV7M_HAVE_ITCM - select ARMV7M_HAVE_DTCM + +config STM32F7_STM32F74XX + bool + default n config STM32F7_STM32F75XX bool default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_IO_CONFIG_V + bool + default n + +config STM32F7_IO_CONFIG_I + bool + default n + +config STM32F7_IO_CONFIG_Z + bool + default n + +config STM32F7_IO_CONFIG_N + bool + default n + +config STM32F7_IO_CONFIG_B + bool + default n + +config STM32F7_IO_CONFIG_A + bool + default n + +config STM32F7_STM32F745XX + bool + default n + select STM32F7_STM32F74XX select ARCH_HAVE_FPU - select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DMA2D + +config STM32F7_STM32F746XX + bool + default n + select STM32F7_STM32F74XX + select ARCH_HAVE_FPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + +config STM32F7_STM32F756XX + bool + default n + select STM32F7_STM32F75XX + select ARCH_HAVE_FPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + +config STM32F7_STM32F765XX + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG # data sheet says yes, Product matix says no + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F767XX + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F768XX # Revisit Wehn parts released + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F768AX # Revisit When parts released + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 + select STM32F7_HAVE_SPI6 + select STM32F7_HAVE_SDMMC2 + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F769XX + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F769AX # Revisit When parts released + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 + select STM32F7_HAVE_SPI6 + select STM32F7_HAVE_SDMMC2 + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F777XX + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F778XX # Revisit when parts released + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F778AX + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 + select STM32F7_HAVE_SPI6 + select STM32F7_HAVE_SDMMC2 + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F779XX + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F779AX + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_FLASH_CONFIG_E + bool + default n + +config STM32F7_FLASH_CONFIG_I + bool + default n + +config STM32F7_FLASH_CONFIG_I + bool + default n choice - prompt "Embedded FLASH size" - default STM32F7_FLASH_1024KB + prompt "Overrdide Flash Size Designator" + depends on ARCH_CHIP_STM32F7 + default STM32F7_FLASH_OVERRIDE_DEFAULT + ---help--- + STM32F7 series parts numbering (sans the package type) ends with a letter + that designates the FLASH size. -config STM32F7_FLASH_512KB - bool "512 KB" + Designator Size in KiB + E 512 + G 1024 + I 2048 -config STM32F7_FLASH_1024KB - bool "1024 KB" + This configuration option defaults to using the configuration based on that designator + or the default smaller size if there is no last character designator is present in the + STM32 Chip Selection. -endchoice # Embedded FLASH size + Examples: + If the STM32F745VE is chosen, the Flash configuration would be 'E', if a variant of + the part with a 2048 KiB Flash is released in the future one could simply select + the 'I' designator here. + + If an STM32F7xxx Series parts is chosen the default Flash configuration will be set + herein and can be changed. + +config STM32F7_FLASH_OVERRIDE_DEFAULT + bool "Default" + +config STM32F7_FLASH_OVERRIDE_E + bool "E 512KiB" + +config STM32F7_FLASH_OVERRIDE_G + bool "G 1024KiB" + +config STM32F7_FLASH_OVERRIDE_I + bool "I 2048KiB" + +endchoice # "Overrdide Flash Size Designator" menu "STM32 Peripheral Support" @@ -75,6 +931,67 @@ config STM32F7_HAVE_LTDC bool default n +config STM32F7_HAVE_FSMC + bool + default n + + +config STM32F7_HAVE_ETHRNET + bool + default n + +config STM32F7_HAVE_RNG + bool + default n + +config STM32F7_HAVE_SPI5 + bool + default n + +config STM32F7_HAVE_SPI6 + bool + default n + +config STM32F7_HAVE_SDMMC2 + bool + default n + +config STM32F7_HAVE_CAN3 + bool + default n + +config STM32F7_HAVE_DCMI + bool + default n + +config STM32F7_HAVE_DSIHOST + bool + default n + +config STM32F7_HAVE_LTDC + bool + default n + +config STM32F7_HAVE_DMA2D + bool + default n + +config STM32F7_HAVE_JPEG + bool + default n + +config STM32F7_HAVE_CRYP + bool + default n + +config STM32F7_HAVE_HASH + bool + default n + +config STM32F7_HAVE_DFSDM1 + bool + default n + # These "hidden" settings are the OR of individual peripheral selections # indicating that the general capabilitiy is required. @@ -143,6 +1060,13 @@ config STM32F7_CAN2 select CAN select STM32F7_CAN +config STM32F7_CAN3 + bool "CAN3" + default n + select CAN + select STM32F7_CAN + depends on STM32F7_HAVE_CAN3 + config STM32F7_CEC bool "CEC" default n @@ -154,8 +1078,15 @@ config STM32F7_CRC config STM32F7_CRYP bool "CRYP" + depends on STM32F7_HAVE_CRYP default n +config STM32F7_DFSDM1 + bool "DFSDM1" + default n + depends on STM32F7_HAVE_DFSDM1 + select ARCH_HAVE_DFSDM1 + config STM32F7_DMA1 bool "DMA1" default n @@ -181,17 +1112,54 @@ config STM32F7_DAC2 config STM32F7_DCMI bool "DCMI" default n + depends on STM32F7_HAVE_DCMI + ---help--- + The devices embed a camera interface that can connect with camera + modules and CMOS sensors through an 8-bit to 14-bit parallel interface, + to receive video data. + +config STM32F7_DSIHOST + bool "DSIHOST" + default n + depends on STM32F7_HAVE_DSIHOST + ---help--- + The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI + compliant displays. + +config STM32F7_DMA2D + bool "DMA2D" + default n + depends on STM32F7_HAVE_DMA2D + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32 F7 devices. + +config STM32F7_JPEG + bool "JPEG" + default n + depends on STM32F7_HAVE_JPEG + ---help--- + The JPEG codec provides an fast and simple hardware compressor and + decompressor of JPEG images with full management of JPEG headers. config STM32F7_ETHMAC bool "Ethernet MAC" default n + depends on STM32F7_HAVE_ETHRNET select NETDEVICES select ARCH_HAVE_PHY config STM32F7_FSMC bool "FSMC" + depends on STM32F7_HAVE_FSMC default n +config STM32F7_HASH + bool "HASH" + default n + depends on STM32F7_HAVE_HASH + select ARCH_HAVE_HASH + config STM32F7_I2C1 bool "I2C1" default n @@ -225,13 +1193,6 @@ config STM32F7_LTDC video interface (HSYNC, VSYNC, etc.) for controlling TFT LCD displays. -config STM32F7_DMA2D - bool "DMA2D" - default n - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32 F7 devices. - config STM32F7_OTGFS bool "OTG FS" default n @@ -246,10 +1207,10 @@ config STM32F7_QUADSPI bool "QuadSPI" default n -config STM32F7_SAI1 config STM32F7_RNG bool "RNG" default n + depends on STM32F7_HAVE_RNG select ARCH_HAVE_RNG config STM32F7_SAI1 @@ -267,6 +1228,12 @@ config STM32F7_SDMMC1 default n select ARCH_HAVE_SDIO +config STM32F7_SDMMC2 + bool "SDMMC2" + default n + depends on STM32F7_HAVE_SDMMC2 + select ARCH_HAVE_SDIO + config STM32F7_SPDIFRX bool "SPDIFRX" default n @@ -298,12 +1265,14 @@ config STM32F7_SPI4 config STM32F7_SPI5 bool "SPI5" default n + depends on STM32F7_HAVE_SPI5 select SPI select STM32F7_SPI config STM32F7_SPI6 bool "SPI6" default n + depends on STM32F7_HAVE_SPI6 select SPI select STM32F7_SPI @@ -685,7 +1654,7 @@ config STM32F7_SERIALBRK_BSDCOMPAT endmenu # U[S]ART Configuration config STM32F7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" + bool "Custom clock configuration" default n ---help--- Enables special, board-specific STM32 clock configuration. diff --git a/arch/arm/src/stm32f7/chip/stm32_dma.h b/arch/arm/src/stm32f7/chip/stm32_dma.h index 63db15ec9f..64fa967bca 100644 --- a/arch/arm/src/stm32f7/chip/stm32_dma.h +++ b/arch/arm/src/stm32f7/chip/stm32_dma.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_dma.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_dma.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_dma.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_ethernet.h b/arch/arm/src/stm32f7/chip/stm32_ethernet.h index e5fc6982d2..962cb6d922 100644 --- a/arch/arm/src/stm32f7/chip/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/chip/stm32_ethernet.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_ethernet.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -46,7 +47,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************************************** * Pre-processor Definitions @@ -805,6 +807,6 @@ struct eth_rxdesc_s ****************************************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32_exti.h b/arch/arm/src/stm32f7/chip/stm32_exti.h index 1bf43de793..288f51b228 100644 --- a/arch/arm/src/stm32f7/chip/stm32_exti.h +++ b/arch/arm/src/stm32f7/chip/stm32_exti.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_exti.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -47,7 +48,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /************************************************************************************ * Pre-processor Definitions @@ -127,5 +129,5 @@ #define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_IMR_MASK STM32_EXTI_MASK -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32_flash.h b/arch/arm/src/stm32f7/chip/stm32_flash.h index 965191bdcf..d20bdfe4d3 100644 --- a/arch/arm/src/stm32f7/chip/stm32_flash.h +++ b/arch/arm/src/stm32f7/chip/stm32_flash.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_flash.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_flash.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_flash.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_gpio.h b/arch/arm/src/stm32f7/chip/stm32_gpio.h index 5b89574b0f..06431bb787 100644 --- a/arch/arm/src/stm32f7/chip/stm32_gpio.h +++ b/arch/arm/src/stm32f7/chip/stm32_gpio.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_gpio.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_gpio.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_gpio.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_memorymap.h b/arch/arm/src/stm32f7/chip/stm32_memorymap.h index f3ef8a1d53..eba94016fd 100644 --- a/arch/arm/src/stm32f7/chip/stm32_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32_memorymap.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_memorymap.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_memorymap.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_memorymap.h" #else # error "Unsupported STM32 F7 memory map" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_pinmap.h b/arch/arm/src/stm32f7/chip/stm32_pinmap.h index 59903d8d03..034e32166e 100644 --- a/arch/arm/src/stm32f7/chip/stm32_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32_pinmap.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_pinmap.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,8 +46,10 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_pinmap.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_pinmap.h" #else -# error "Unsupported STM32 F7 memory map" +# error "Unsupported STM32 F7 Pin map" #endif #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32_pwr.h b/arch/arm/src/stm32f7/chip/stm32_pwr.h index 427fab1f3f..e9415d800a 100644 --- a/arch/arm/src/stm32f7/chip/stm32_pwr.h +++ b/arch/arm/src/stm32f7/chip/stm32_pwr.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_pwr.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_pwr.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_pwr.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_rcc.h b/arch/arm/src/stm32f7/chip/stm32_rcc.h index 13468a5560..1bbbca2ec8 100644 --- a/arch/arm/src/stm32f7/chip/stm32_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32_rcc.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_rcc.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +45,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_rcc.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_rcc.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_syscfg.h b/arch/arm/src/stm32f7/chip/stm32_syscfg.h index 37c82ec50c..5b1f4c1a3d 100644 --- a/arch/arm/src/stm32f7/chip/stm32_syscfg.h +++ b/arch/arm/src/stm32f7/chip/stm32_syscfg.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_syscfg.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_syscfg.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_syscfg.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_uart.h b/arch/arm/src/stm32f7/chip/stm32_uart.h index 0d48eaa399..a260cca6ca 100644 --- a/arch/arm/src/stm32f7/chip/stm32_uart.h +++ b/arch/arm/src/stm32f7/chip/stm32_uart.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_uart.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,8 +43,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# include "chip/stm32f74xx75xx_uart.h" +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f74xx77xx_uart.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h index a9acb05787..6b7fed23c1 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h @@ -412,16 +412,16 @@ #define DMAMAP_SPDIFRX_CS STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN0) #define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0) -#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) -#define DMAMAP_I2C3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1) +#define DMAMAP_I2C1_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) +#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1) #define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1) #define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1) -#define DMAMAP_I2C1_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) -#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) -#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) +#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) +#define DMAMAP_I2C1_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) +#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) #define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2) -#define DMAMAP_I2C_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2) +#define DMAMAP_I2C4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2) #define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2) #define DMAMAP_I2C4_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2) #define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2) @@ -429,7 +429,7 @@ #define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) #define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) -#define DMAMAP_I2C3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_I2C3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) #define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3) #define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3) #define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) @@ -468,8 +468,8 @@ #define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6) #define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7) -#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) -#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_I2C2_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) #define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7) #define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7) #define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7) diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h index 69f4e217fc..74c2759fc9 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -40,44 +41,62 @@ * Pre-processor Definitions ************************************************************************************/ -/* Flash size is not known from the chip configuration: +/* Flash size is known from the chip selection: + * + * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip + * part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH * - * The user has to tell us the FLASH size by setting CONFIG_STM32F7_FLASH_SIZE + * N.B. Only Single bank mode is supported */ -#if defined(CONFIG_STM32F7_FLASH_512KB) - -# define STM32_FLASH_NPAGES 2 -# define STM32_FLASH_SIZE (512*1024) - -#elif defined(CONFIG_STM32F7_FLASH_1024KB) - -# define STM32_FLASH_NPAGES 4 -# define STM32_FLASH_SIZE (1024*1024) - -#else -# warning Assuming FLASH size 1024KB - -# define STM32_FLASH_NPAGES 4 -# define STM32_FLASH_SIZE (1024*1024) +#define _K(x) ((x)*1024) +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_F) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_F) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) +# define CONFIG_STM32_FLASH_OVERRIDE_E +# warning "Flash size not defined defaulting to 512KiB (E)" #endif -/* The STM32F745xx/46xx have mixed page sizes: - * - * Sectors: 0-3: 32 KB - * Sector 4 128 KB - * Sectors: 5-7: 256 KB - * - * We use the largest page size and set the number of pages equal to the - * FLASH size assuming that fixed, largest pages size. - */ +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) -#define STM32_FLASH_PAGESIZE (256*1024) +# undef CONFIG_STM32F7_FLASH_CONFIG_E +# undef CONFIG_STM32F7_FLASH_CONFIG_G +# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) + +# define CONFIG_STM32F7_FLASH_CONFIG_E + +# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) + +# define CONFIG_STM32F7_FLASH_CONFIG_G + +# endif +#endif + +#if defined(CONFIG_STM32_FLASH_CONFIG_E) + +# define STM32_FLASH_NPAGES 6 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256)} + +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) + +# define STM32_FLASH_NPAGES 8 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256), _K(256), _K(256)} + +#endif /* Register Offsets *****************************************************************/ @@ -133,8 +152,8 @@ #define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ #define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ #define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ -#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) -# define FLASH_CR_SNB(n) ((uint32_t)(n) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */ +#define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT) +# define FLASH_CR_SNB(n) ((uint32_t)((n) % 8) << FLASH_CR_SNB_SHIFT) | ((n / 8) << 6)) /* Sector n, n=0..23 */ #define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ #define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) # define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */ @@ -145,7 +164,6 @@ #define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ #define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ #define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ -#define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */ /* Flash Option Control Register (OPTCR) */ @@ -159,15 +177,15 @@ # define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */ #define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */ #define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT) -# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 5: WWDG_SW */ +# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */ # define FLASH_OPTCR_IWDG_SW (1 << 5) /* Bit 5: IWDG_SW */ # define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */ # define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */ #define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */ #define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT) # define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */ -#define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) +#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-23: Not write protect */ +#define FLASH_OPTCR_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT) # define FLASH_OPTCR_NWRP(n) ((uint32_t)(n) << FLASH_OPTCR_NWRP_SHIFT) #define FLASH_OPTCR_IWDG_STDBY (1 << 30) /* Bit 30: IWDG freeze in stop mode */ #define FLASH_OPTCR_IWDG_STOP (1 << 31) /* Bit 31: IWDG freeze in standby mode */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h index c996f7d105..b8818f6e49 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h @@ -61,7 +61,6 @@ #define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ #define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ #define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses ***************************************************************/ @@ -76,7 +75,6 @@ # define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 1 @@ -90,7 +88,6 @@ # define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 2 @@ -104,7 +101,6 @@ # define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 3 @@ -118,7 +114,6 @@ # define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 4 @@ -132,7 +127,6 @@ # define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 5 @@ -146,7 +140,6 @@ # define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 6 @@ -160,7 +153,6 @@ # define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 7 @@ -174,7 +166,6 @@ # define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 8 @@ -188,7 +179,6 @@ # define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOI_BRR (STM32_GPIOI_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 9 @@ -202,7 +192,6 @@ # define STM32_GPIOJ_LCKR (STM32_GPIOJ_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOJ_AFRL (STM32_GPIOJ_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOJ_BRR (STM32_GPIOJ_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 10 @@ -216,7 +205,6 @@ # define STM32_GPIOK_LCKR (STM32_GPIOK_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOK_AFRL (STM32_GPIOK_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOK_AFRH (STM32_GPIOK_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOK_BRR (STM32_GPIOK_BASE+STM32_GPIO_BRR_OFFSET) #endif /* Register Bitfield Definitions ****************************************************/ @@ -411,9 +399,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -/* GPIO port bit reset register */ - -#define GPIO_BRR(n) (1 << (n)) - #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h index 82a5d2242b..20f3b73390 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h @@ -2,7 +2,8 @@ * arch/arm/src/stm3fr2/chip/stm32f74xxx75xxx_memorymap.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -59,9 +60,8 @@ #define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */ # define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ # define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */ -#define STM32_AHB3_BASE 0xa0000000 /* 0xa0000000-0xa0001fff: 256Mb AHB3 peripheral block */ #define STM32_FSMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FSMC */ -#define STM32_FSMC_BASE6 0xc0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */ +#define STM32_FSMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */ #define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */ #define STM32_REGION_MASK 0xf0000000 @@ -97,6 +97,7 @@ #define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */ #define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x4007ffff: APB1 */ #define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x5003ffff: AHB2 */ +#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */ /* APB1 Base Addresses **************************************************************/ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h index 64b68653d1..4e0410bc16 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h * * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -50,7 +51,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* Alternate Pin Functions. All members of the STM32F40xxx family share the same +/* Alternate Pin Functions. All members of the STM32F74|5xxx family share the same * pin multiplexing (although they may differ in the pins physically available). * * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h index e7c58b19ff..547b555a92 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h @@ -1,8 +1,9 @@ /************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32_pwr.h + * arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -103,6 +104,7 @@ #define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */ #define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */ #define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */ +#define PWR_CSR1_EIWUP (1 << 8) /* Bit 8: Enable internal wakeup */ #define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */ #define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ #define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_uart.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h similarity index 98% rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_uart.h rename to arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h index 50d5f949f5..cc838f9753 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_uart.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h @@ -1,8 +1,9 @@ /************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32f74xxf75xx_uart.h + * arch/arm/src/stm32f7/chip/stm32f74xxf77xx_uart.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX75XX_UART_H -#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX75XX_UART_H +#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H +#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H /************************************************************************************ * Included Files @@ -42,7 +43,8 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /************************************************************************************ * Pre-processor Definitions @@ -366,4 +368,4 @@ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ -#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX75XX_UART_H */ +#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h new file mode 100644 index 0000000000..82ab312cb3 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h @@ -0,0 +1,593 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Davod Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XX_DMA_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XX_DMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* 2 DMA controllers */ + +#define DMA1 (0) +#define DMA2 (1) + +/* 8 DMA streams */ + +#define DMA_STREAM0 (0) +#define DMA_STREAM1 (1) +#define DMA_STREAM2 (2) +#define DMA_STREAM3 (3) +#define DMA_STREAM4 (4) +#define DMA_STREAM5 (5) +#define DMA_STREAM6 (6) +#define DMA_STREAM7 (7) + +/* 16 DMA channels */ + +#define DMA_CHAN0 (0) +#define DMA_CHAN1 (1) +#define DMA_CHAN2 (2) +#define DMA_CHAN3 (3) +#define DMA_CHAN4 (4) +#define DMA_CHAN5 (5) +#define DMA_CHAN6 (6) +#define DMA_CHAN7 (7) +#define DMA_CHAN8 (8) +#define DMA_CHAN9 (9) +#define DMA_CHAN10 (10) +#define DMA_CHAN11 (11) +#define DMA_CHAN12 (12) +#define DMA_CHAN13 (13) +#define DMA_CHAN14 (14) +#define DMA_CHAN15 (15) + +/* Register Offsets *****************************************************************/ + +#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */ +#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */ +#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */ +#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */ + +#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n)) +#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */ +#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */ +#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */ +#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */ +#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */ +#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */ + +#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */ +#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */ +#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */ +#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */ +#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */ +#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */ +#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */ +#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ + +#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */ +#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */ +#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */ +#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */ +#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */ +#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */ +#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */ +#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */ + +#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */ +#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */ +#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */ +#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */ +#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */ +#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */ +#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */ +#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */ + +#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */ +#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */ +#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */ +#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */ +#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */ +#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */ +#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */ +#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */ + +#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */ +#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */ +#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */ +#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */ +#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */ +#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */ +#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */ +#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */ + +#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */ +#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */ +#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */ +#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */ +#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */ +#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */ +#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */ +#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET) + +#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +#define DMA_STREAM_MASK 0x3f +#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */ +#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */ +#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */ +#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */ +#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */ + +/* DMA interrupt status register and interrupt flag clear register field definitions */ + +#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */ +#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT) +#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */ +#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT) +#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */ +#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT) +#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */ +#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT) + +#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */ +#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT) +#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */ +#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT) +#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */ +#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT) +#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */ +#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT) + +/* DMA stream configuration register */ + +#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */ +#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */ +#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */ +#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */ +#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */ +#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */ +#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */ +#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT) +# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */ +# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */ +# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */ +#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */ +#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */ +#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */ +#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */ +#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT) +# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */ +#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT) +# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */ +#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */ +#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT) +# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */ +# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */ +# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */ +# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */ +#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */ +#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */ +#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */ +#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT) +# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */ +#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */ +#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT) +# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */ +#define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-28: Channel selection */ +#define DMA_SCR_CHSEL_MASK (0xf << DMA_SCR_CHSEL_SHIFT) +# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT) + +#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE) + +/* DMA stream number of data register */ + +#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ +#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT) + +/* DMA stream n FIFO control register */ + +#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */ +#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT) +# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */ +# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */ +# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */ +# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */ +#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */ +#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */ +#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT) +# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */ +# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */ +# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */ +# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */ +# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */ +# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */ + /* Bit 6: Reserved */ +#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */ + /* Bits 8-31: Reserved */ + +/* DMA Stream mapping. Each DMA stream has a mapping to several possible + * sources/sinks of data. The requests from peripherals assigned to a stream + * are simply OR'ed together before entering the DMA block. This means that only + * one request on a given stream can be enabled at once. + * + * Alternative stream selections are provided with a numeric suffix like _1, _2, etc. + * The DMA driver, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * SPI3_RX connects via DMA STREAM0, then following should be application-specific + * mapping should be used: + * + * #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1 + */ + +#define STM32_DMA_MAP(d,s,c) ((d) << 7 | (s) << 4 | (c)) +#define STM32_DMA_CONTROLLER(m) (((m) >> 7) & 1) +#define STM32_DMA_STREAM(m) (((m) >> 4) & 7) +#define STM32_DMA_CHANNEL(m) ((m) & 0xf) + +#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) +#define DMAMAP_SPDIFRX_DT STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN0) +#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0) +#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_SPI3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN0) +#define DMAMAP_SPDIFRX_CS STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0) + +#define DMAMAP_I2C1_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) +#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1) +#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1) +#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1) +#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) +#define DMAMAP_I2C1_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) +#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) + +#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2) +#define DMAMAP_I2C4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2) +#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2) +#define DMAMAP_I2C4_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2) +#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2) +#define DMAMAP_TIM4_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN2) + +#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) +#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) +#define DMAMAP_I2C3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3) +#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3) +#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_TIM2_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_TIM2_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) +#define DMAMAP_TIM2_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) + +#define DMAMAP_UART5_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN4) +#define DMAMAP_USART3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN4) +#define DMAMAP_UART4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN4) +#define DMAMAP_USART3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN4) +#define DMAMAP_UART4_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN4) +#define DMAMAP_USART2_RX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN4) +#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4) +#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4) + +#define DMAMAP_UART8_TX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN5) +#define DMAMAP_UART7_TX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN5) +#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_UART7_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN5) +#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5) +#define DMAMAP_UART8_RX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN5) +#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5) + +#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM5_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM5_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM5_TRIG_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM5_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN6) +#define DMAMAP_TIM5_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM5_TRIG_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM5_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6) + +#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7) +#define DMAMAP_I2C2_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7) +#define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7) +#define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7) +#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7) + +#define DMAMAP_I2C3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN8) +#define DMAMAP_I2C4_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN8) +#define DMAMAP_I2C2_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN8) +#define DMAMAP_I2C4_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN8) + +#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN9) +#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN9) + +#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0) +#define DMAMAP_SAI1_A_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN0) +#define DMAMAP_TIM8_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_TIM8_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_SAI1_A_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN0) +#define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_SAI1_B_1 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN0) +#define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_SAI1_B_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN0) + +#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1) +#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1) +#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1) +#define DMAMAP_SAI1_B STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN1) +#define DMAMAP_SPI6_TX STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN1) +#define DMAMAP_SPI6_RX STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN1) +#define DMAMAP_DCMI_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN1) + +#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2) +#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2) +#define DMAMAP_SPI5_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN2) +#define DMAMAP_SPI5_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN2) +#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2) +#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2) +#define DMAMAP_HASH_IN STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN2) + +#define DMAMAP_SPI1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3) +#define DMAMAP_SPI1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3) +#define DMAMAP_SAI2_A STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN3) +#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3) +#define DMAMAP_SAI2_B STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_QUADSPI STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN3) + +#define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4) +#define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4) +#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4) +#define DMAMAP_SDMMC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4) +#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4) +#define DMAMAP_SDMMC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN4) +#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4) + +#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5) +#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5) +#define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5) +#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5) + +#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6) +#define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6) +#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6) + +#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7) +#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7) +#define DMAMAP_SPI5_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7) +#define DMAMAP_SPI5_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN7) +#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) +#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) +#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) + +#define DMAMAP_DFSDM1_FLT0_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT1_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT3_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT0_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT1_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT2_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT3_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN8) + +#define DMAMAP_JPEG_IN_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN9) +#define DMAMAP_JPEG_OUT_ STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN9) +#define DMAMAP_SPI4_TX_3 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN9) +#define DMAMAP_JPEG_IN_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN9) +#define DMAMAP_JPEG_OUT_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN9) +#define DMAMAP_SPI5_RX_3 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN9) + +#define DMAMAP_SAI1_B_3 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN10) +#define DMAMAP_SAI2_B_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN10) +#define DMAMAP_SAI2_A_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN10) +#define DMAMAP_SAI1_A_3 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN10) + +#define DMAMAP_SDMMC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN11) +#define DMAMAP_QUADSPI STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN11) +#define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h new file mode 100644 index 0000000000..0b6f764c36 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h @@ -0,0 +1,219 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H +#define __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Flash size is known from the chip selection: + * + * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip + * part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * + * Parts STM32F74xxE have 512Kb of FLASH + * Parts STM32F74xxG have 1024Kb of FLASH + * + * N.B. Only Single bank mode is supported + */ + +#define _K(x) ((x)*1024) + +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_F) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_F) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E +# warning "Flash size not defined defaulting to 512KiB (E)" +#endif + +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) + +# undef CONFIG_STM32F7_FLASH_CONFIG_E +# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32F7_FLASH_CONFIG_I + +# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) + +# define CONFIG_STM32F7_FLASH_CONFIG_E + +# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) + +# define CONFIG_STM32F7_FLASH_CONFIG_G + +# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) + +# define CONFIG_STM32F7_FLASH_CONFIG_I + +# endif +#endif + +#if defined(CONFIG_STM32_FLASH_CONFIG_E) + +# define STM32_FLASH_NPAGES 6 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256)} + +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) + +# define STM32_FLASH_NPAGES 8 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256), _K(256), _K(256)} + +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) + +# define STM32_FLASH_NPAGES 12 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (7 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256), _K(256), _K(256) \ + _K(256), _K(256), _K(256), _K(256)} +#endif + +/* Register Offsets *****************************************************************/ + +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_KEYR_OFFSET 0x0004 +#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 +#define STM32_FLASH_SR_OFFSET 0x000c +#define STM32_FLASH_CR_OFFSET 0x0010 +#define STM32_FLASH_OPTCR_OFFSET 0x0014 +#define STM32_FLASH_OPTCR1_OFFSET 0x0018 + +/* Register Addresses ***************************************************************/ + +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) +#define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ +/* Flash Access Control Register (ACR) */ + +#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-1: Latency */ +#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ +# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states */ +# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states */ +# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */ +# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */ +# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */ +#define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ +#define FLASH_ACR_ARTEN (1 << 9) /* Bit 9: ART Accelerator Enable */ +#define FLASH_ACR_ARTRST (1 << 11) /* Bit 11: ART Accelerator reset */ + +/* Flash Status Register (SR) */ + +#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +#define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */ +#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ + +/* Flash Control Register (CR) */ + +#define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */ +#define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ +#define FLASH_CR_MER_MER1 (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ +#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ +#define FLASH_CR_SNB_MASK (0x1f << FLASH_CR_SNB_SHIFT) +# define FLASH_CR_SNB(n) ((uint32_t)((n) % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */ +#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ +#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) +# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */ +# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* Program x16 */ +# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* Program x32 */ +# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* Program x64 */ +#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */ +#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ +#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ +#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ +#define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */ + +/* Flash Option Control Register (OPTCR) */ + +#define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */ +#define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */ +#define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */ +#define FLASH_OPTCR_BORLEV_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT) +# define FLASH_OPTCR_VBOR3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 3 */ +# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 2 */ +# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 1 */ +# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */ +#define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */ +#define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT) +# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */ +# define FLASH_OPTCR_IWDG_SW (1 << 5) /* Bit 5: IWDG_SW */ +# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */ +# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */ +#define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */ +#define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT) +# define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT) +#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */ +#define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) +# define FLASH_OPTCR_NWRP(n) ((uint32_t)(n) << FLASH_OPTCR_NWRP_SHIFT) +#define FLASH_OPTCR_NDBANK (1 << 28) /* Bit 28: Not dual bank mode */ +#define FLASH_OPTCR_NDBOOT (1 << 29) /* Bit 29: Dual Boot mode */ +#define FLASH_OPTCR_IWDG_STDBY (1 << 30) /* Bit 30: IWDG freeze in stop mode */ +#define FLASH_OPTCR_IWDG_STOP (1 << 31) /* Bit 31: IWDG freeze in standby mode */ + +/* Flash Option Control Register (OPTCR1) */ + +#define FLASH_OPTCR1_BOOTADD0_SHIFT (0) /* Bits 0-15: Boot base address when Boot pin=0 */ +#define FLASH_OPTCR1_BOOTADD0_MASK (0xffff << FLASH_OPTCR1_BOOTADD0_SHIFT) +# define FLASH_OPTCR1_BOOTADD0(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD0_SHIFT) +#define FLASH_OPTCR1_BOOTADD1_SHIFT (16) /* Bits 16-31:Boot base address when Boot pin=1 */ +#define FLASH_OPTCR1_BOOTADD1_MASK (0xffff << FLASH_OPTCR1_BOOTADD1_SHIFT) +# define FLASH_OPTCR1_BOOTADD1(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD1_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h new file mode 100644 index 0000000000..711dc0e124 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h @@ -0,0 +1,404 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f76xxx77xx_gpio.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ + +/* Register Addresses ***************************************************************/ + +#if STM32F7_NGPIO > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 9 +# define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOJ_PUPDR (STM32_GPIOJ_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOJ_IDR (STM32_GPIOJ_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOJ_ODR (STM32_GPIOJ_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOJ_BSRR (STM32_GPIOJ_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOJ_LCKR (STM32_GPIOJ_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOJ_AFRL (STM32_GPIOJ_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 10 +# define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOK_PUPDR (STM32_GPIOK_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOK_IDR (STM32_GPIOK_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOK_ODR (STM32_GPIOK_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOK_BSRR (STM32_GPIOK_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOK_LCKR (STM32_GPIOK_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOK_AFRL (STM32_GPIOK_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOK_AFRH (STM32_GPIOK_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +/* Register Bitfield Definitions ****************************************************/ + +/* GPIO port mode register */ + +#define GPIO_MODER_INPUT (0) /* Input */ +#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */ +#define GPIO_MODER_ALT (2) /* Alternate mode */ +#define GPIO_MODER_ANALOG (3) /* Analog mode */ + +#define GPIO_MODER_SHIFT(n) ((n) << 1) +#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) + +#define GPIO_MODER0_SHIFT (0) +#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT) +#define GPIO_MODER1_SHIFT (2) +#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT) +#define GPIO_MODER2_SHIFT (4) +#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT) +#define GPIO_MODER3_SHIFT (6) +#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT) +#define GPIO_MODER4_SHIFT (8) +#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT) +#define GPIO_MODER5_SHIFT (10) +#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT) +#define GPIO_MODER6_SHIFT (12) +#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT) +#define GPIO_MODER7_SHIFT (14) +#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT) +#define GPIO_MODER8_SHIFT (16) +#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT) +#define GPIO_MODER9_SHIFT (18) +#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT) +#define GPIO_MODER10_SHIFT (20) +#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT) +#define GPIO_MODER11_SHIFT (22) +#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT) +#define GPIO_MODER12_SHIFT (24) +#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT) +#define GPIO_MODER13_SHIFT (26) +#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT) +#define GPIO_MODER14_SHIFT (28) +#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT) +#define GPIO_MODER15_SHIFT (30) +#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT) + +/* GPIO port output type register */ + +#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */ +#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */ + +/* GPIO port output speed register */ + +#define GPIO_OSPEED_2MHz (0) /* 2 MHz Low speed */ +#define GPIO_OSPEED_25MHz (1) /* 25 MHz Medium speed */ +#define GPIO_OSPEED_50MHz (2) /* 50 MHz Fast speed */ +#define GPIO_OSPEED_100MHz (3) /* 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF) */ + +#define GPIO_OSPEED_SHIFT(n) ((n) << 1) +#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) + +#define GPIO_OSPEED0_SHIFT (0) +#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT) +#define GPIO_OSPEED1_SHIFT (2) +#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT) +#define GPIO_OSPEED2_SHIFT (4) +#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT) +#define GPIO_OSPEED3_SHIFT (6) +#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT) +#define GPIO_OSPEED4_SHIFT (8) +#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT) +#define GPIO_OSPEED5_SHIFT (10) +#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT) +#define GPIO_OSPEED6_SHIFT (12) +#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT) +#define GPIO_OSPEED7_SHIFT (14) +#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT) +#define GPIO_OSPEED8_SHIFT (16) +#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT) +#define GPIO_OSPEED9_SHIFT (18) +#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT) +#define GPIO_OSPEED10_SHIFT (20) +#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT) +#define GPIO_OSPEED11_SHIFT (22) +#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT) +#define GPIO_OSPEED12_SHIFT (24) +#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT) +#define GPIO_OSPEED13_SHIFT (26) +#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT) +#define GPIO_OSPEED14_SHIFT (28) +#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT) +#define GPIO_OSPEED15_SHIFT (30) +#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT) + +/* GPIO port pull-up/pull-down register */ + +#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */ +#define GPIO_PUPDR_PULLUP (1) /* Pull-up */ +#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ + +#define GPIO_PUPDR_SHIFT(n) ((n) << 1) +#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) + +#define GPIO_PUPDR0_SHIFT (0) +#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT) +#define GPIO_PUPDR1_SHIFT (2) +#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT) +#define GPIO_PUPDR2_SHIFT (4) +#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT) +#define GPIO_PUPDR3_SHIFT (6) +#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT) +#define GPIO_PUPDR4_SHIFT (8) +#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT) +#define GPIO_PUPDR5_SHIFT (10) +#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT) +#define GPIO_PUPDR6_SHIFT (12) +#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT) +#define GPIO_PUPDR7_SHIFT (14) +#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT) +#define GPIO_PUPDR8_SHIFT (16) +#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT) +#define GPIO_PUPDR9_SHIFT (18) +#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT) +#define GPIO_PUPDR10_SHIFT (20) +#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT) +#define GPIO_PUPDR11_SHIFT (22) +#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT) +#define GPIO_PUPDR12_SHIFT (24) +#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT) +#define GPIO_PUPDR13_SHIFT (26) +#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT) +#define GPIO_PUPDR14_SHIFT (28) +#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT) +#define GPIO_PUPDR15_SHIFT (30) +#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT) + +/* GPIO port input data register */ + +#define GPIO_IDR(n) (1 << (n)) + +/* GPIO port output data register */ + +#define GPIO_ODR(n) (1 << (n)) + +/* GPIO port bit set/reset register */ + +#define GPIO_BSRR_SET(n) (1 << (n)) +#define GPIO_BSRR_RESET(n) (1 << ((n)+16)) + +/* GPIO port configuration lock register */ + +#define GPIO_LCKR(n) (1 << (n)) +#define GPIO_LCKK (1 << 16) /* Lock key */ + +/* GPIO alternate function low/high register */ + +#define GPIO_AFR_SHIFT(n) ((n) << 2) +#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) + +#define GPIO_AFRL0_SHIFT (0) +#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT) +#define GPIO_AFRL1_SHIFT (4) +#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT) +#define GPIO_AFRL2_SHIFT (8) +#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT) +#define GPIO_AFRL3_SHIFT (12) +#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT) +#define GPIO_AFRL4_SHIFT (16) +#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT) +#define GPIO_AFRL5_SHIFT (20) +#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT) +#define GPIO_AFRL6_SHIFT (24) +#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT) +#define GPIO_AFRL7_SHIFT (28) +#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) + +#define GPIO_AFRH8_SHIFT (0) +#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT) +#define GPIO_AFRH9_SHIFT (4) +#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT) +#define GPIO_AFRH10_SHIFT (8) +#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT) +#define GPIO_AFRH11_SHIFT (12) +#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT) +#define GPIO_AFRH12_SHIFT (16) +#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT) +#define GPIO_AFRH13_SHIFT (20) +#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT) +#define GPIO_AFRH14_SHIFT (24) +#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT) +#define GPIO_AFRH15_SHIFT (28) +#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h new file mode 100644 index 0000000000..c4c6177ac6 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h @@ -0,0 +1,214 @@ +/************************************************************************************ + * arch/arm/src/stm3fr2/chip/stm32f76xxx77xxx_memorymap.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* STM32F40XXX Address Blocks *******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb AHB1-2 peripheral blocks */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */ +# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */ +#define STM32_FSMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FSMC */ +#define STM32_FSMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1) + +/* Code Base Addresses **************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_INSTRAM_BASE 0x00000000 /* 0x00000000-0x00003fff: Instruction RAM (ITCM-RAM) */ +#define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */ +#define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x003fffff: FLASH memory (ITCM) */ +#define STM32_LOADER_BASE 0x01000000 /* 0x01000000- Bootloader */ +#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x081fffff: FLASH memory (AXIM) */ +#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */ + +/* Information Addresses ************************************************************/ + + +#define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */ +#define STM32_OTP_ICTM 0x0010f000 /* 0x0010f000-0x0010edbf: OTP (ITCM) */ +#define STM32_OTP_AXIM 0x1ff0f000 /* 0x1ff00000-0x1ff0f41f: OTP (AXIM) */ + +/* SRAM Base Addresses **************************************************************/ + +#define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */ +#define STM32_SRAM1_BASE 0x20020000 /* 0x20020000-0x2007bfff: System SRAM1 */ +#define STM32_SRAM2_BASE 0x2007c000 /* 0x2007c000-0x2007ffff: System SRAM2 */ + +/* Peripheral Base Addresses ********************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007fff: APB1 */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x4007ffff: APB1 */ +#define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x5003ffff: AHB2 */ +#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */ + +/* APB1 Base Addresses **************************************************************/ + +#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff: TIM2 */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff: TIM3 */ +#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff: TIM4 */ +#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00-0x40000fff: TIM5 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff: TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff: TIM7 */ +#define STM32_TIM12_BASE 0x40001800 /* 0x40001800-0x40001bff: TIM12 */ +#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 */ +#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */ +#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */ +#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */ +#define STM32_CAN3_BASE 0x40003400 /* 0x40003400-0x400037ff: CAN3 */ +#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */ +#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */ +#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */ +#define STM32_I2S3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */ +#define STM32_SPDIFRX_BASE 0x40004000 /* 0x40004000-0x400043ff: SPDIFRX */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff: USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff: USART3 */ +#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff: UART4 */ +#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff: UART5 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff: I2C1 */ +#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff: I2C2 */ +#define STM32_I2C3_BASE 0x40005c00 /* 0x40005c00-0x40005fff: I2C3 */ +#define STM32_I2C4_BASE 0x40006000 /* 0x40006000-0x400063ff: I2C4 */ +#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff: CAN1 */ +#define STM32_CAN2_BASE 0x40006800 /* 0x40006800-0x40006bff: CAN2 */ +#define STM32_HDMICEC_BASE 0x40006c00 /* 0x40006c00-0x40006fff: HDMI-CEC */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff: PWR */ +#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC */ +#define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */ +#define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */ + +/* APB2 Base Addresses **************************************************************/ + +#define STM32_TIM1_BASE 0x40010000 /* 0x40010000-0x400103ff: TIM1 */ +#define STM32_TIM8_BASE 0x40010400 /* 0x40010400-0x400107ff: TIM8 */ +#define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */ +#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */ +#define STM32_SDMMC2_BASE 0x40011c00 /* 0x40011c00-0x40011fff: SDMMC2 */ +#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */ +#define STM32_SDMMC1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDMMC1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */ +#define STM32_SPI4_BASE 0x40013400 /* 0x40013400-0x400137ff: SPI4 */ +#define STM32_SYSCFG_BASE 0x40013800 /* 0x40013800-0x40013bff: SYSCFG */ +#define STM32_EXTI_BASE 0x40013c00 /* 0x40013c00-0x40013fff: EXTI */ +#define STM32_TIM9_BASE 0x40014000 /* 0x40014000-0x400143ff: TIM9 */ +#define STM32_TIM10_BASE 0x40014400 /* 0x40014400-0x400147ff: TIM10 */ +#define STM32_TIM11_BASE 0x40014800 /* 0x40014800-0x40014bff: TIM11 */ +#define STM32_SPI5_BASE 0x40015000 /* 0x40015000-0x400153ff: SPI5 */ +#define STM32_SPI6_BASE 0x40015400 /* 0x40015400-0x400157ff: SPI6 */ +#define STM32_SAI1_BASE 0x40015800 /* 0x40015800-0x40015bff: SAI1 */ +#define STM32_SAI2_BASE 0x40015c00 /* 0x40015c00-0x40015fff: SAI2 */ +#define STM32_LCDTFT_BASE 0x40016800 /* 0x40016800-0x40016bff: LCD-TFT */ +#define STM32_DSIHOST_BASE 0x40016c00 /* 0x40016c00-0x400173ff: DSI Host */ +#define STM32_DFSDM1_BASE 0x40017400 /* 0x40017400-0x400174ff: DFSDM1 */ +#define STM32_MDIOS_BASE 0x40017800 /* 0x40017800-0x40017bff: MDIOS */ + +/* AHB1 Base Addresses **************************************************************/ + +#define STM32_GPIOA_BASE 0x40020000 /* 0x40020000-0x400203ff: GPIOA */ +#define STM32_GPIOB_BASE 0x40020400 /* 0x40020400-0x400207ff: GPIOB */ +#define STM32_GPIOC_BASE 0x40020800 /* 0x40020800-0x40020bff: GPIOC */ +#define STM32_GPIOD_BASE 0x40020c00 /* 0x40020c00-0x40020fff: GPIOD */ +#define STM32_GPIOE_BASE 0x40021000 /* 0x40021000-0x400213ff: GPIOE */ +#define STM32_GPIOF_BASE 0x40021400 /* 0x40021400-0x400217ff: GPIOF */ +#define STM32_GPIOG_BASE 0x40021800 /* 0x40021800-0x40021bff: GPIOG */ +#define STM32_GPIOH_BASE 0x40021c00 /* 0x40021c00-0x40021fff: GPIOH */ +#define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIOI */ +#define STM32_GPIOJ_BASE 0x40022400 /* 0x40022400-0x400227ff: GPIOJ */ +#define STM32_GPIOK_BASE 0x40022800 /* 0x40022800-0x40022bff: GPIOK */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: RCC */ +#define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff: Flash interface */ +#define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: BKPSRAM */ +#define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */ +#define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff: DMA2 */ +#define STM32_ETHMAC_BASE 0x40028000 /* 0x40028000-0x400293ff: ETHERNET MAC */ +#define STM32_DMA2D_BASE 0x4002b000 /* 0x4002b000-0x4002Bbff: Chrom-ART (DMA2D) */ +#define STM32_USBOTGHS_BASE 0x40040000 /* 0x40040000-0x4007ffff: USB OTG HS */ + +/* AHB2 Base Addresses **************************************************************/ + +#define STM32_USBOTGFS_BASE 0x50000000 /* 0x50000000-0x5003ffff: USB OTG FS */ +#define STM32_DCMI_BASE 0x50050000 /* 0x50050000-0x500503ff: DCMI */ +#define STM32_JPEG_BASE 0x50051000 /* 0x50051000-0x500511ff: JPEG */ +#define STM32_CRYP_BASE 0x50060000 /* 0x50060000-0x500603ff: CRYP */ +#define STM32_HASH_BASE 0x50060400 /* 0x50060400-0x500607ff: HASH */ +#define STM32_RNG_BASE 0x50060800 /* 0x50060800-0x50060bff: RNG */ + +/* AHB3 Base Addresses **************************************************************/ + +#define STM32_FMCBANK1_BASE 0x60000000 /* 0x60000000-0x6fffffff: FMC bank 1 */ +#define STM32_FMCBANK2_BASE 0x70000000 /* 0x70000000-0x7fffffff: FMC bank 2 */ +#define STM32_FMCBANK3_BASE 0x80000000 /* 0x80000000-0x8fffffff: FMC bank 3 */ +#define STM32_FMCBANK4_BASE 0x90000000 /* 0x90000000-0x9fffffff: FMC bank 4 */ +#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xa0000fff: FMC control registers */ +#define STM32_QUADSPI_BASE 0xa0001000 /* 0xa0001000-0xa0001fff: QuadSPI Control */ +#define STM32_FMCBANK5_BASE 0xc0000000 /* 0xc0000000-0xcfffffff: FMC bank 5 */ +#define STM32_FMCBANK6_BASE 0xd0000000 /* 0xd0000000-0xdfffffff: FMC bank 6 */ + +/* Cortex-M7 Base Addresses *********************************************************/ +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this + * address range + */ + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h new file mode 100644 index 0000000000..4c60603c95 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h @@ -0,0 +1,1343 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_PINMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "stm32_gpio.h" + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F76XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Alternate Pin Functions. All members of the STM32F76|7xxx family share the same + * pin multiplexing (although they may differ in the pins physically available). + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * CAN1_RX connects vis PA11 on some board, then the following definitions should + * appear inthe board.h header file for that board: + * + * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 + * + * The driver will then automatically configre PA11 as the CAN1 RX pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* ADC */ + +#define GPIO_ADC1_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_ADC2_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC2_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC2_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC2_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC2_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC2_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_ADC3_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC3_IN4 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6) +#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7) +#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8) +#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9) +#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10) + +#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3) +#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4) +#define GPIO_ADC3_IN15 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN5) + +/* CAN */ + +#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_CAN1_RX_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_CAN1_RX_3 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) +#define GPIO_CAN1_RX_4 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14) +#define GPIO_CAN1_RX_5 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9) + +#define GPIO_CAN1_TX_1 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_CAN1_TX_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_CAN1_TX_3 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1) +#define GPIO_CAN1_TX_4 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13) + +#define GPIO_CAN2_RX_1 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_CAN2_RX_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_CAN2_TX_1 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_CAN2_TX_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) + +#define GPIO_CAN3_RX_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_CAN3_RX_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_CAN3_TX_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_CAN3_TX_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) + +/* DAC -" Once the DAC channel is enabled, the corresponding GPIO pin + * (PA4 or PA5) is automatically connected to the analog converter output + * (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin + * should first be configured to analog (AIN)". + */ + +#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) + +/* Digital Camera Interface (DCMI) */ + +#define GPIO_DCMI_D0_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN9) +#define GPIO_DCMI_D0_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN6) +#define GPIO_DCMI_D0_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN9) +#define GPIO_DCMI_D1_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN10) +#define GPIO_DCMI_D1_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN7) +#define GPIO_DCMI_D1_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN10) +#define GPIO_DCMI_D2_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN8) +#define GPIO_DCMI_D2_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN0) +#define GPIO_DCMI_D2_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN10) +#define GPIO_DCMI_D2_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN11) +#define GPIO_DCMI_D3_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN9) +#define GPIO_DCMI_D3_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN1) +#define GPIO_DCMI_D3_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN11) +#define GPIO_DCMI_D3_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN12) +#define GPIO_DCMI_D4_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN11) +#define GPIO_DCMI_D4_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN4) +#define GPIO_DCMI_D4_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN14) +#define GPIO_DCMI_D5_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6) +#define GPIO_DCMI_D5_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN3) +#define GPIO_DCMI_D5_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN4) +#define GPIO_DCMI_D6_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8) +#define GPIO_DCMI_D6_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN5) +#define GPIO_DCMI_D6_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN6) +#define GPIO_DCMI_D7_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9) +#define GPIO_DCMI_D7_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6) +#define GPIO_DCMI_D7_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN7) +#define GPIO_DCMI_D8_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10) +#define GPIO_DCMI_D8_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN6) +#define GPIO_DCMI_D8_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN1) +#define GPIO_DCMI_D9_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN12) +#define GPIO_DCMI_D9_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN7) +#define GPIO_DCMI_D9_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN2) +#define GPIO_DCMI_D10_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5) +#define GPIO_DCMI_D10_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN6) +#define GPIO_DCMI_D10_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN3) +#define GPIO_DCMI_D11_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN2) +#define GPIO_DCMI_D11_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN10) +#define GPIO_DCMI_D11_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN15) +#define GPIO_DCMI_D12_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN11) +#define GPIO_DCMI_D12_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN6) +#define GPIO_DCMI_D13_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN15) +#define GPIO_DCMI_D13_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN7) +#define GPIO_DCMI_D13_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN0) +#define GPIO_DCMI_HSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DCMI_HSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN8) +#define GPIO_DCMI_PIXCK (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6) +#define GPIO_DCMI_VSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7) +#define GPIO_DCMI_VSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN9) +#define GPIO_DCMI_VSYNC_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN5) + +/* DSI Host */ + +#define DSI_TE_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN11) +#define DSI_TE_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTJ|GPIO_PIN12) + +/* Digital filter for sigma delta modulators */ + +#define GPIO_DFSDM1_CKOUT_1 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_DFSDM1_CKOUT_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2) +#define GPIO_DFSDM1_CKOUT_3 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3) +#define GPIO_DFSDM1_CKOUT_4 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10) +#define GPIO_DFSDM1_CKOUT_5 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9) +#define GPIO_DFSDM1_CKIN0_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) +#define GPIO_DFSDM1_CKIN0_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3) +#define GPIO_DFSDM1_CKIN1_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2) +#define GPIO_DFSDM1_CKIN1_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_DFSDM1_CKIN1_3 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2) +#define GPIO_DFSDM1_CKIN1_4 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7) +#define GPIO_DFSDM1_CKIN2_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_DFSDM1_CKIN2_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4) +#define GPIO_DFSDM1_CKIN2_3 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8) +#define GPIO_DFSDM1_CKIN3_1 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_DFSDM1_CKIN3_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1) +#define GPIO_DFSDM1_CKIN3_3 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8) +#define GPIO_DFSDM1_CKIN3_4 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) +#define GPIO_DFSDM1_CKIN4_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_DFSDM1_CKIN4_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) +#define GPIO_DFSDM1_CKIN5_1 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_DFSDM1_CKIN5_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_DFSDM1_CKIN5_3 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) +#define GPIO_DFSDM1_CKIN6_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) +#define GPIO_DFSDM1_CKIN6_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN14) +#define GPIO_DFSDM1_CKIN7_1 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_DFSDM1_CKIN7_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_DFSDM1_CKIN7_3 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_DFSDM1_CKIN7_4 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTS|GPIO_PIN1) +#define GPIO_DFSDM1_DATAIN0_1 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1) +#define GPIO_DFSDM1_DATAIN0_2 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN4) +#define GPIO_DFSDM1_DATAIN1_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_DFSDM1_DATAIN1_2 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_DFSDM1_DATAIN1_3 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3) +#define GPIO_DFSDM1_DATAIN1_4 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_DFSDM1_DATAIN2_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_DFSDM1_DATAIN2_2 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5) +#define GPIO_DFSDM1_DATAIN2_3 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN7) +#define GPIO_DFSDM1_DATAIN3_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_DFSDM1_DATAIN3_2 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9) +#define GPIO_DFSDM1_DATAIN3_3 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4) +#define GPIO_DFSDM1_DATAIN4_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) +#define GPIO_DFSDM1_DATAIN4_2 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7) +#define GPIO_DFSDM1_DATAIN4_3 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN10) +#define GPIO_DFSDM1_DATAIN5_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_DFSDM1_DATAIN5_2 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_DFSDM1_DATAIN5_3 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12) +#define GPIO_DFSDM1_DATAIN6_1 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1) +#define GPIO_DFSDM1_DATAIN6_2 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13) +#define GPIO_DFSDM1_DATAIN7_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_DFSDM1_DATAIN7_2 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_DFSDM1_DATAIN7_3 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) + +/* Ethernet MAC */ + +#define GPIO_ETH_MDC (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ETH_MII_COL_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ETH_MII_COL_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3) +#define GPIO_ETH_MII_CRS_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ETH_MII_CRS_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2) +#define GPIO_ETH_MII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ETH_MII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5) +#define GPIO_ETH_MII_RXD2_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ETH_MII_RXD2_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6) +#define GPIO_ETH_MII_RXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ETH_MII_RXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN7) +#define GPIO_ETH_MII_RX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ETH_MII_RX_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ETH_MII_RX_ER_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_ETH_MII_RX_ER_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10) +#define GPIO_ETH_MII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_ETH_MII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) +#define GPIO_ETH_MII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_ETH_MII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) +#define GPIO_ETH_MII_TXD2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ETH_MII_TXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_ETH_MII_TXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2) +#define GPIO_ETH_MII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ETH_MII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) +#define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8) + +#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5) +#define GPIO_ETH_RMII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_ETH_RMII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) +#define GPIO_ETH_RMII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_ETH_RMII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) +#define GPIO_ETH_RMII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ETH_RMII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_ETH_RMII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) + +/* Event outputs */ + +#define GPIO_PA0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN1) +#define GPIO_PA2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN2) +#define GPIO_PA3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN3) +#define GPIO_PA4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN4) +#define GPIO_PA5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN5) +#define GPIO_PA6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN6) +#define GPIO_PA7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN7) +#define GPIO_PA8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN8) +#define GPIO_PA9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN9) +#define GPIO_PA10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN10) +#define GPIO_PA11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN11) +#define GPIO_PA12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN12) +#define GPIO_PA13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN13) +#define GPIO_PA14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN14) +#define GPIO_PA15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_PB0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN0) +#define GPIO_PB1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN1) +#define GPIO_PB2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN2) +#define GPIO_PB3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN3) +#define GPIO_PB4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN4) +#define GPIO_PB5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN5) +#define GPIO_PB6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN6) +#define GPIO_PB7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN7) +#define GPIO_PB8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN8) +#define GPIO_PB9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN9) +#define GPIO_PB10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN10) +#define GPIO_PB11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN11) +#define GPIO_PB12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN12) +#define GPIO_PB13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN13) +#define GPIO_PB14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN14) +#define GPIO_PB15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN15) + +#define GPIO_PC0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN0) +#define GPIO_PC1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN1) +#define GPIO_PC2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN2) +#define GPIO_PC3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN3) +#define GPIO_PC4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN4) +#define GPIO_PC5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN5) +#define GPIO_PC6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN6) +#define GPIO_PC7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN7) +#define GPIO_PC8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN8) +#define GPIO_PC9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN9) +#define GPIO_PC10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN10) +#define GPIO_PC11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN11) +#define GPIO_PC12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN12) +#define GPIO_PC13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN13) +#define GPIO_PC14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN14) +#define GPIO_PC15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN15) + +#define GPIO_PD0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN0) +#define GPIO_PD1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN1) +#define GPIO_PD2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN2) +#define GPIO_PD3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN3) +#define GPIO_PD4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN4) +#define GPIO_PD5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN5) +#define GPIO_PD6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN6) +#define GPIO_PD7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN7) +#define GPIO_PD8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN8) +#define GPIO_PD9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN9) +#define GPIO_PD10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN10) +#define GPIO_PD11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN11) +#define GPIO_PD12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN12) +#define GPIO_PD13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN13) +#define GPIO_PD14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN14) +#define GPIO_PD15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN15) + +#define GPIO_PE0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN0) +#define GPIO_PE1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN1) +#define GPIO_PE2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN2) +#define GPIO_PE3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN3) +#define GPIO_PE4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN4) +#define GPIO_PE5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN5) +#define GPIO_PE6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN6) +#define GPIO_PE7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN7) +#define GPIO_PE8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN8) +#define GPIO_PE9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN9) +#define GPIO_PE10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN10) +#define GPIO_PE11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN11) +#define GPIO_PE12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN12) +#define GPIO_PE13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN13) +#define GPIO_PE14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN14) +#define GPIO_PE15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN15) + +#define GPIO_PF0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN0) +#define GPIO_PF1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN1) +#define GPIO_PF2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN2) +#define GPIO_PF3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN3) +#define GPIO_PF4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN4) +#define GPIO_PF5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN5) +#define GPIO_PF6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN6) +#define GPIO_PF7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN7) +#define GPIO_PF8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN8) +#define GPIO_PF9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN9) +#define GPIO_PF10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN10) +#define GPIO_PF11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN11) +#define GPIO_PF12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN12) +#define GPIO_PF13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN13) +#define GPIO_PF14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN14) +#define GPIO_PF15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN15) + +#define GPIO_PG0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN0) +#define GPIO_PG1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN1) +#define GPIO_PG2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN2) +#define GPIO_PG3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN3) +#define GPIO_PG4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN4) +#define GPIO_PG5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN5) +#define GPIO_PG6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN6) +#define GPIO_PG7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN7) +#define GPIO_PG8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN8) +#define GPIO_PG9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN9) +#define GPIO_PG10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN10) +#define GPIO_PG11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN11) +#define GPIO_PG12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN12) +#define GPIO_PG13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN13) +#define GPIO_PG14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN14) +#define GPIO_PG15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN15) + +#define GPIO_PH0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN0) +#define GPIO_PH1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN1) +#define GPIO_PH2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN2) +#define GPIO_PH3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN3) +#define GPIO_PH4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN4) +#define GPIO_PH5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN5) +#define GPIO_PH6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN6) +#define GPIO_PH7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN7) +#define GPIO_PH8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN8) +#define GPIO_PH9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN9) +#define GPIO_PH10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN10) +#define GPIO_PH11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN11) +#define GPIO_PH12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN12) +#define GPIO_PH13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN13) +#define GPIO_PH14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN14) +#define GPIO_PH15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN15) + +#define GPIO_PI0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN0) +#define GPIO_PI1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN1) +#define GPIO_PI2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN2) +#define GPIO_PI3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN3) +#define GPIO_PI4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN4) +#define GPIO_PI5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN5) +#define GPIO_PI6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN6) +#define GPIO_PI7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN7) +#define GPIO_PI8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN8) +#define GPIO_PI9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN9) +#define GPIO_PI10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN10) +#define GPIO_PI11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN11) +#define GPIO_PI12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN12) +#define GPIO_PI13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN13) +#define GPIO_PI14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN14) +#define GPIO_PI15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN15) + +#define GPIO_PJ0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN0) +#define GPIO_PJ1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN1) +#define GPIO_PJ2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN2) +#define GPIO_PJ3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN3) +#define GPIO_PJ4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN4) +#define GPIO_PJ5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN5) +#define GPIO_PJ6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN6) +#define GPIO_PJ7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN7) +#define GPIO_PJ8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN8) +#define GPIO_PJ9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN9) +#define GPIO_PJ10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN10) +#define GPIO_PJ11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN11) +#define GPIO_PJ12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN12) +#define GPIO_PJ13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN13) +#define GPIO_PJ14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN14) +#define GPIO_PJ15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN15) + +#define GPIO_PK0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN0) +#define GPIO_PK1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN1) +#define GPIO_PK2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN2) +#define GPIO_PK3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN3) +#define GPIO_PK4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN4) +#define GPIO_PK5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN5) +#define GPIO_PK6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN6) +#define GPIO_PK7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN7) + +/* Flexible Static Memory Controller (FSMC) */ + +#define GPIO_FSMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0) +#define GPIO_FSMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1) +#define GPIO_FSMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2) +#define GPIO_FSMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3) +#define GPIO_FSMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4) +#define GPIO_FSMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5) +#define GPIO_FSMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12) +#define GPIO_FSMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13) +#define GPIO_FSMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14) +#define GPIO_FSMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15) +#define GPIO_FSMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0) +#define GPIO_FSMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1) +#define GPIO_FSMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2) +#define GPIO_FSMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3) +#define GPIO_FSMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4) +#define GPIO_FSMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5) +#define GPIO_FSMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11) +#define GPIO_FSMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12) +#define GPIO_FSMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13) +#define GPIO_FSMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3) +#define GPIO_FSMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4) +#define GPIO_FSMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5) +#define GPIO_FSMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6) +#define GPIO_FSMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2) +#define GPIO_FSMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13) +#define GPIO_FSMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14) +#define GPIO_FSMC_ALE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12) +#define GPIO_FSMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4) +#define GPIO_FSMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5) +#define GPIO_FSMC_CLE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11) +#define GPIO_FSMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3) +#define GPIO_FSMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14) +#define GPIO_FSMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15) +#define GPIO_FSMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0) +#define GPIO_FSMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1) +#define GPIO_FSMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7) +#define GPIO_FSMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8) +#define GPIO_FSMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9) +#define GPIO_FSMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10) +#define GPIO_FSMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11) +#define GPIO_FSMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12) +#define GPIO_FSMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13) +#define GPIO_FSMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14) +#define GPIO_FSMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15) +#define GPIO_FSMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8) +#define GPIO_FSMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9) +#define GPIO_FSMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10) +#define GPIO_FSMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8) +#define GPIO_FSMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9) +#define GPIO_FSMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10) +#define GPIO_FSMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11) +#define GPIO_FSMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12) +#define GPIO_FSMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13) +#define GPIO_FSMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14) +#define GPIO_FSMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15) +#define GPIO_FSMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0) +#define GPIO_FSMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1) +#define GPIO_FSMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2) +#define GPIO_FSMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3) +#define GPIO_FSMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6) +#define GPIO_FSMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7) +#define GPIO_FSMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9) +#define GPIO_FSMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10) +#define GPIO_FSMC_INT (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN7) +#define GPIO_FSMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0) +#define GPIO_FSMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1) +#define GPIO_FSMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4) +#define GPIO_FSMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5) +#define GPIO_FSMC_NCE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9) +#define GPIO_FSMC_NCE_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8) +#define GPIO_FSMC_NE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7) +#define GPIO_FSMC_NE1_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN7) +#define GPIO_FSMC_NE2_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9) +#define GPIO_FSMC_NE2_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8) +#define GPIO_FSMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10) +#define GPIO_FSMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12) +#define GPIO_FSMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_FSMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4) +#define GPIO_FSMC_NWAIT_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6) +#define GPIO_FSMC_NWAIT_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5) +#define GPIO_FSMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3) +#define GPIO_FSMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5) +#define GPIO_FSMC_SDCKE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2) +#define GPIO_FSMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_FSMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7) +#define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8) +#define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15) +#define GPIO_FSMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2) +#define GPIO_FSMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4) +#define GPIO_FSMC_SDNE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3) +#define GPIO_FSMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6) +#define GPIO_FSMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6) +#define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11) +#define GPIO_FSMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_FSMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0) +#define GPIO_FSMC_SDNWE_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5) + +/* HDMI-CEC Controller */ + +#define GPIO_HDMICEC_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN6) +#define GPIO_HDMICEC_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN15) + +/* I2C */ + +#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6) +#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7) +#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) + +#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1) +#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN4) +#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11) +#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0) +#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN5) +#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2) +#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6) + +#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8) +#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7) +#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9) +#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8) +#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) + +#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12) +#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN14) +#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11) +#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_I2C4_SCL_5 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) +#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN15) +#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12) +#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11) +#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13) +#define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10) +#define GPIO_I2C4_SMBA_4 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) + +/* I2S */ + +#define GPIO_I2S1_CK_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN5) +#define GPIO_I2S1_CK_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN3) +#define GPIO_I2S1_CK_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN11) +#define GPIO_I2S1_MCK (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN4) +#define GPIO_I2S1_SD_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN7) +#define GPIO_I2S1_SD_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN5) +#define GPIO_I2S1_SD_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN7) +#define GPIO_I2S1_WS_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN15) +#define GPIO_I2S1_WS_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN4) +#define GPIO_I2S1_WS_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN10) + +#define GPIO_I2S2_CK_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN9) +#define GPIO_I2S2_CK_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2S2_CK_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN13) +#define GPIO_I2S2_CK_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN3) +#define GPIO_I2S2_CK_5 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN1) +#define GPIO_I2S2_CK_6 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN12) +#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN6) +#define GPIO_I2S2_SD_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN15) +#define GPIO_I2S2_SD_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN1) +#define GPIO_I2S2_SD_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN3) +#define GPIO_I2S2_SD_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN3) +#define GPIO_I2S2_WS_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN12) +#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2S2_WS_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN0) +#define GPIO_I2S2_WS_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN4) +#define GPIO_I2S2_WS_5 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN11) + +#define GPIO_I2S3_CK_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN3) +#define GPIO_I2S3_CK_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN10) +#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN7) +#define GPIO_I2S3_SD_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN6) +#define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN5) +#define GPIO_I2S3_SD_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN12) +#define GPIO_I2S3_SD_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN2) +#define GPIO_I2S3_WS_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN15) +#define GPIO_I2S3_WS_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN4) + +#define GPIO_I2S4_SD_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN7) +#define GPIO_I2S4_SD_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2S_CKIN (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN9) + +/* JTAG */ + +#define GPIO_JTCK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) +#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15) +#define GPIO_JTDO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) +#define GPIO_JTMS (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) +#define GPIO_NJTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4) + +#define GPIO_SWCLK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) +#define GPIO_SWDIO (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) + +/* LCD-TFT Display Controller (LTDC) */ + +#define GPIO_LTDC_R0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) +#define GPIO_LTDC_R0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2) +#define GPIO_LTDC_R0_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN15) +#define GPIO_LTDC_R1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_LTDC_R1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3) +#define GPIO_LTDC_R1_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN0) +#define GPIO_LTDC_R2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_LTDC_R2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_LTDC_R2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN8) +#define GPIO_LTDC_R2_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN1) +#define GPIO_LTDC_R3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) +#define GPIO_LTDC_R3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN2) +#define GPIO_LTDC_R3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_LTDC_R4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_LTDC_R4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_LTDC_R4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10) +#define GPIO_LTDC_R4_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN3) +#define GPIO_LTDC_R5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_LTDC_R5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) +#define GPIO_LTDC_R5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11) +#define GPIO_LTDC_R5_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN4) +#define GPIO_LTDC_R5_5 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_LTDC_R6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_LTDC_R6_2 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_LTDC_R6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12) +#define GPIO_LTDC_R6_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN5) +#define GPIO_LTDC_R7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN15) +#define GPIO_LTDC_R7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6) +#define GPIO_LTDC_R7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN6) +#define GPIO_LTDC_R7_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN0) + +#define GPIO_LTDC_B0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4) +#define GPIO_LTDC_B0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) +#define GPIO_LTDC_B0_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN12) +#define GPIO_LTDC_B1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12) +#define GPIO_LTDC_B1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN13) +#define GPIO_LTDC_B1_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_LTDC_B2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_LTDC_B2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) +#define GPIO_LTDC_B2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN14) +#define GPIO_LTDC_B2_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_LTDC_B2_5 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_LTDC_B3_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10) +#define GPIO_LTDC_B3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) +#define GPIO_LTDC_B3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN15) +#define GPIO_LTDC_B3_4 (GPIO_ALT|GPIO_AF13|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_LTDC_B4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12) +#define GPIO_LTDC_B4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN4) +#define GPIO_LTDC_B4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN3) +#define GPIO_LTDC_B4_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12) +#define GPIO_LTDC_B4_5 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_LTDC_B5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_LTDC_B5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5) +#define GPIO_LTDC_B5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN4) +#define GPIO_LTDC_B6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_LTDC_B6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6) +#define GPIO_LTDC_B6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN5) +#define GPIO_LTDC_B7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_LTDC_B7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7) +#define GPIO_LTDC_B7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN6) + +#define GPIO_LTDC_G0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) +#define GPIO_LTDC_G0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN7) +#define GPIO_LTDC_G0_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_LTDC_G1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6) +#define GPIO_LTDC_G1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN8) +#define GPIO_LTDC_G1_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_LTDC_G2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_LTDC_G2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13) +#define GPIO_LTDC_G2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN9) +#define GPIO_LTDC_G2_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN15) +#define GPIO_LTDC_G3_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) +#define GPIO_LTDC_G3_2 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) +#define GPIO_LTDC_G3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14) +#define GPIO_LTDC_G3_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN10) +#define GPIO_LTDC_G3_5 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_LTDC_G3_6 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN12) +#define GPIO_LTDC_G4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_LTDC_G4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN15) +#define GPIO_LTDC_G4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN11) +#define GPIO_LTDC_G4_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN4) +#define GPIO_LTDC_G4_5 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN13) +#define GPIO_LTDC_G5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_LTDC_G5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0) +#define GPIO_LTDC_G5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN0) +#define GPIO_LTDC_G5_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN4) +#define GPIO_LTDC_G6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_LTDC_G6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN1) +#define GPIO_LTDC_G6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN1) +#define GPIO_LTDC_G6_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN11) +#define GPIO_LTDC_G7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3) +#define GPIO_LTDC_G7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2) +#define GPIO_LTDC_G7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN2) +#define GPIO_LTDC_G7_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_LTDC_G7_5 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8) + +#define GPIO_LTDC_HSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_LTDC_HSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10) +#define GPIO_LTDC_HSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN12) +#define GPIO_LTDC_VSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4) +#define GPIO_LTDC_VSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9) +#define GPIO_LTDC_VSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN13) +#define GPIO_LTDC_CLK_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14) +#define GPIO_LTDC_CLK_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7) +#define GPIO_LTDC_CLK_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN14) +#define GPIO_LTDC_DE_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) +#define GPIO_LTDC_DE_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10) +#define GPIO_LTDC_DE_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN7) + +/* Low Power Timer */ + +#define GPIO_LPTIM1_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0) +#define GPIO_LPTIM1_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN14) +#define GPIO_LPTIM1_IN1_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12) +#define GPIO_LPTIM1_IN1_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN12) +#define GPIO_LPTIM1_IN2_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1) +#define GPIO_LPTIM1_IN2_4 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN2) +#define GPIO_LPTIM1_OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) +#define GPIO_LPTIM1_OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) + +/* Clocks outputs */ + +#define GPIO_MCO1 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_MCO2 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) + +/* Management data input/output */ + +#define MDIOS_MDIO_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define MDIOS_MDC_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define MDIOS_MDC_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN1) +#define MDIOS_MDIO_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) + +/* OTG FS/HS (VBUS PA9 is not an alternate configuration) */ + +#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10) +#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) + +#define GPIO_OTGHSFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_OTGHSFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_OTGHSFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12) + +#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4) + +#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5) +#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3) +#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0) +#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1) +#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10) +#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11) +#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12) +#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13) +#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5) +#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2) +#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN11) +#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3) +#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4) +#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0) + +/* QuadSPI */ + +#define GPIO_QUADSPI_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8) +#define GPIO_QUADSPI_BK1_IO0_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN9) +#define GPIO_QUADSPI_BK1_IO0_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN11) +#define GPIO_QUADSPI_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9) +#define GPIO_QUADSPI_BK1_IO1_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN10) +#define GPIO_QUADSPI_BK1_IO1_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN12) +#define GPIO_QUADSPI_BK1_IO2_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN2) +#define GPIO_QUADSPI_BK1_IO2_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN7) +#define GPIO_QUADSPI_BK1_IO3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN1) +#define GPIO_QUADSPI_BK1_IO3_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN13) +#define GPIO_QUADSPI_BK1_IO3_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN6) +#define GPIO_QUADSPI_BK1_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6) +#define GPIO_QUADSPI_BK1_NCS_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN10) + +#define GPIO_QUADSPI_BK2_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN7) +#define GPIO_QUADSPI_BK2_IO0_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTH|GPIO_PIN2) +#define GPIO_QUADSPI_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN8) +#define GPIO_QUADSPI_BK2_IO1_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTH|GPIO_PIN3) +#define GPIO_QUADSPI_BK2_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN9) +#define GPIO_QUADSPI_BK2_IO2_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN9) +#define GPIO_QUADSPI_BK2_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10) +#define GPIO_QUADSPI_BK2_IO3_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN14) +#define GPIO_QUADSPI_BK2_NCS (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN11) + +#define GPIO_QUADSPI_CLK_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN2) +#define GPIO_QUADSPI_CLK_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN10) + +/* RTC */ + +#define GPIO_RTC_REFIN (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN15) + +/* Serial Audio Interface */ + +#define GPIO_SAI1_FS_A (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN4) +#define GPIO_SAI1_FS_B (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN9) +#define GPIO_SAI1_MCLK_A_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN2) +#define GPIO_SAI1_MCLK_A_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN7) +#define GPIO_SAI1_MCLK_B (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN7) +#define GPIO_SAI1_SCK_A (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN5) +#define GPIO_SAI1_SCK_B (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN8) +#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN2) +#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN1) +#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN6) +#define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN6) +#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN3) +#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN6) +#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN12) +#define GPIO_SAI2_FS_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN7) +#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13) +#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SAI2_FS_B_3 (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN12) +#define GPIO_SAI2_FS_B_4 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN0) +#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN0) +#define GPIO_SAI2_MCLK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN4) +#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1) +#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14) +#define GPIO_SAI2_MCLK_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SAI2_MCLK_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN3) +#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN13) +#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN5) +#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12) +#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN2) +#define GPIO_SAI2_SCK_B_3 (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN2) +#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN11) +#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN6) +#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN0) +#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11) +#define GPIO_SAI2_SD_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11) +#define GPIO_SAI2_SD_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN10) + +/* SD/MMC */ + +#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2) +#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_SDMMC1_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_SDMMC1_D2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_SDMMC1_D3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SDMMC1_D4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SDMMC1_D5 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) + +#define GPIO_SDMMC2_CK (GPIO_ALT|GPIO_AF11|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SDMMC2_CMD (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7) +#define GPIO_SDMMC2_D0_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SDMMC2_D1_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SDMMC2_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN) +#define GPIO_SDMMC2_D3_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SDMMC2_D0_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SDMMC2_D1_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) +#define GPIO_SDMMC2_D2_2 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) +#define GPIO_SDMMC2_D3_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12) +#define GPIO_SDMMC2_D4 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SDMMC2_D5 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SDMMC2_D6 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SDMMC2_D7 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) + + +/* SPDIFRX */ + +#define GPIO_SPDIFRX_IN0_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN11) +#define GPIO_SPDIFRX_IN0_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN7) +#define GPIO_SPDIFRX_IN1_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN12) +#define GPIO_SPDIFRX_IN1_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN8) +#define GPIO_SPDIFRX_IN2_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN8) +#define GPIO_SPDIFRX_IN2_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN4) +#define GPIO_SPDIFRX_IN3_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SPDIFRX_IN3_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN5) + +/* SPI */ + +#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI1_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI1_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN7) +#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI1_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN10) +#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5) +#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SPI1_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN11) + +#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN2) +#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN2) +#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3) +#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN3) +#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN12) +#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN0) +#define GPIO_SPI2_NSS_4 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI2_NSS_5 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10) +#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13) +#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN3) +#define GPIO_SPI2_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN1) +#define GPIO_SPI2_SCK_6 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTIA|GPIO_PIN12) + +#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN2) +#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SPI3_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10) + +#define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN5) +#define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13) +#define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SPI4_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN14) +#define GPIO_SPI4_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN4) +#define GPIO_SPI4_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN11) +#define GPIO_SPI4_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN2) +#define GPIO_SPI4_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN12) + +#define GPIO_SPI5_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN8) +#define GPIO_SPI5_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN7) +#define GPIO_SPI5_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9) +#define GPIO_SPI5_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN11) +#define GPIO_SPI5_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN6) +#define GPIO_SPI5_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN5) +#define GPIO_SPI5_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN7) +#define GPIO_SPI5_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN6) + +#define GPIO_SPI6_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN12) +#define GPIO_SPI6_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN14) +#define GPIO_SPI6_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN8) +#define GPIO_SPI6_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN13) +#define GPIO_SPI6_MISO_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_SPI6_MOSI_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_SPI6_NSS_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI6_SCK_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5) +#define GPIO_SPI6_MISO_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI6_MOSI_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI6_NSS_3 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI6_SCK_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) + +/* Timers */ + +#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN12) +#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN15) +#define GPIO_TIM1_BKIN2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) +#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10) +#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12) +#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN7) + +#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5) + +#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN2) + +#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0) + +#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN10) +#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10) + +#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN11) +#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11) + +#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN12) +#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12) + +#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN0) +#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0) + +#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN4) +#define GPIO_TIM8_BKIN2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM8_BKIN2_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN1) +#define GPIO_TIM8_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN5) +#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5) +#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM8_CH1N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13) +#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN6) +#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6) +#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14) +#define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH3IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN7) +#define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH3OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7) +#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM8_CH3N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15) +#define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH4IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN2) +#define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH4OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2) +#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM8_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN3) + +#define GPIO_TIM9_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM9_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM9_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM9_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM9_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM9_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM9_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM9_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6) + +#define GPIO_TIM10_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM10_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6) +#define GPIO_TIM10_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM10_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) + +#define GPIO_TIM11_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM11_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7) +#define GPIO_TIM11_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM11_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7) + +#define GPIO_TIM12_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM12_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN6) +#define GPIO_TIM12_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM12_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6) + +#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM12_CH2IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN9) +#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM12_CH2OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) + +#define GPIO_TIM13_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM13_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8) +#define GPIO_TIM13_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM13_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8) + +#define GPIO_TIM14_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM14_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM14_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM14_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9) + +/* Trace */ + +#define GPIO_TRACECLK (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2) +#define GPIO_TRACED0_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN1) +#define GPIO_TRACED0_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TRACED0_3 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN13) +#define GPIO_TRACED1_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TRACED1_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TRACED1_3 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN14) +#define GPIO_TRACED2_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTD|GPIO_PIN2) +#define GPIO_TRACED2_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TRACED3_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN12) +#define GPIO_TRACED3_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TRACESWO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) + +/* UARTs/USARTs */ + +#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8) +#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11) +#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12) +#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_USART1_RX_3 (GPIO_ALT|GPIO_AF4|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_USART1_TX_3 (GPIO_ALT|GPIO_AF4|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) + +#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4) +#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7) +#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0) +#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3) +#define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1) +#define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4) +#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5) + +#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12) +#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12) +#define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN10) +#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13) +#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11) +#define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14) +#define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12) +#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9) +#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8) + +#define GPIO_UART4_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN0) +#define GPIO_UART4_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN15) +#define GPIO_UART4_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15) +#define GPIO_UART4_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN14) +#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_UART4_RX_3 (GPIO_ALT|GPIO_AF6|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_UART4_RX_4 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) +#define GPIO_UART4_RX_5 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14) +#define GPIO_UART4_RX_6 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9) +#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_UART4_TX_3 (GPIO_ALT|GPIO_AF6|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_UART4_TX_4 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1) +#define GPIO_UART4_TX_5 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13) + +#define GPIO_UART5_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN9) +#define GPIO_UART5_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN8) +#define GPIO_UART5_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2) +#define GPIO_UART5_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12) +#define GPIO_UART5_RX_2 (GPIO_ALT|GPIO_AF1|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_UART5_TX_2 (GPIO_ALT|GPIO_AF1|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_UART5_RX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_UART5_TX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_UART5_RX_4 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_UART5_TX_4 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_USART6_CK_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN8) +#define GPIO_USART6_CK_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN7) +#define GPIO_USART6_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN13) +#define GPIO_USART6_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN15) +#define GPIO_USART6_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN12) +#define GPIO_USART6_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8) +#define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) +#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) + +#define GPIO_UART7_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTE|GPIO_PIN10) +#define GPIO_UART7_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTF|GPIO_PIN9) +#define GPIO_UART7_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTE|GPIO_PIN9) +#define GPIO_UART7_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTF|GPIO_PIN8) +#define GPIO_UART7_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN7) +#define GPIO_UART7_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) +#define GPIO_UART7_RX_3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_UART7_RX_4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_UART7_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8) +#define GPIO_UART7_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7) +#define GPIO_UART7_TX_3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_UART7_TX_4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) + +#define GPIO_UART8_CTS (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN14) +#define GPIO_UART8_RTS (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN15) +#define GPIO_UART8_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) +#define GPIO_UART8_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h new file mode 100644 index 0000000000..21f78951f9 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h @@ -0,0 +1,159 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F76XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 1 */ +#define STM32_PWR_CSR2_OFFSET 0x000c /* Power control/status register 1 */ + +/* Register Addresses ***************************************************************/ + +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CSR2 (STM32_PWR_BASE+STM32_PWR_CSR2_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* Power control register 1 */ + +#define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */ +#define PWR_CR1_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ +#define PWR_CR1_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ +#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ +#define PWR_CR1_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ +#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT) +# define PWR_CR1_2p0V (0 << PWR_CR1_PLS_SHIFT) /* 000: 2.0V */ +# define PWR_CR1_2p1V (1 << PWR_CR1_PLS_SHIFT) /* 001: 2.1V */ +# define PWR_CR1_2p3V (2 << PWR_CR1_PLS_SHIFT) /* 010: 2.3V */ +# define PWR_CR1_2p5V (3 << PWR_CR1_PLS_SHIFT) /* 011: 2.5V */ +# define PWR_CR1_2p6V (4 << PWR_CR1_PLS_SHIFT) /* 100: 2.6V */ +# define PWR_CR1_2p7V (5 << PWR_CR1_PLS_SHIFT) /* 101: 2.7V */ +# define PWR_CR1_2p8V (6 << PWR_CR1_PLS_SHIFT) /* 110: 2.8V */ +# define PWR_CR1_2p9V (7 << PWR_CR1_PLS_SHIFT) /* 111: 2.9V */ +#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ +#define PWR_CR1_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ +#define PWR_CR1_LPUDS (1 << 10) /* Bit 10: Low-power regulator in deepsleep under-drive mode */ +#define PWR_CR1_MRUDS (1 << 11) /* Bit 11: Main regulator in deepsleep under-drive mode */ +#define PWR_CR1_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */ +#define PWR_CR1_VOS_SHIFT (14) /* Bits 14-15: Regulator voltage scaling output selection */ +#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT) +# define PWR_CR1_VOS_SCALE_3 (1 << PWR_CR1_VOS_SHIFT) /* Fmax = 144MHz */ +# define PWR_CR1_VOS_SCALE_2 (2 << PWR_CR1_VOS_SHIFT) /* Fmax = 168/180MHz */ +# define PWR_CR1_VOS_SCALE_1 (3 << PWR_CR1_VOS_SHIFT) /* Fmax = 180/216MHz */ +#define PWR_CR1_ODEN (1 << 16) /* Bit 16: Over Drive enable */ +#define PWR_CR1_ODSWEN (1 << 17) /* Bit 17: Over Drive switch enabled */ +#define PWR_CR1_UDEN_SHIFT (18) /* Bits 18-19: Under-drive enable in stop mode */ +#define PWR_CR1_UDEN_MASK (3 << PWR_CR1_UDEN_SHIFT) +# define PWR_CR1_UDEN_DISABLE (0 << PWR_CR1_UDEN_SHIFT) /* Under-drive disable */ +# define PWR_CR1_UDEN_ENABLE (3 << PWR_CR1_UDEN_SHIFT) /* Under-drive enable */ + +/* Power control/status register 1 */ + +#define PWR_CSR1_WUIF (1 << 0) /* Bit 0: Wakeup internal flag */ +#define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */ +#define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */ +#define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */ +#define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */ +#define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ +#define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */ +#define PWR_CSR1_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ +#define PWR_CSR1_UDSRDY_SHIFT (18) /* Bits 18-19: Under-drive ready flag */ +#define PWR_CSR1_UDSRDY_MASK (3 << PWR_CSR1_UDSRDY_SHIFT) +# define PWR_CSR1_UDSRDY_DISAB (0 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive is disabled */ +# define PWR_CSR1_UDSRDY_STOP (3 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive mode is activated in Stop mode */ + +/* Power control register 2 */ + +#define PWR_CR2_CWUPF1 (1 << 0) /* Bit 0: Clear Wakeup Pin flag for PA0 */ +#define PWR_CR2_CWUPF2 (1 << 1) /* Bit 1: Clear Wakeup Pin flag for PA2 */ +#define PWR_CR2_CWUPF3 (1 << 2) /* Bit 2: Clear Wakeup Pin flag for PC1 */ +#define PWR_CR2_CWUPF4 (1 << 3) /* Bit 3: Clear Wakeup Pin flag for PC13 */ +#define PWR_CR2_CWUPF5 (1 << 4) /* Bit 4: Clear Wakeup Pin flag for PI8 */ +#define PWR_CR2_CWUPF6 (1 << 5) /* Bit 5: Clear Wakeup Pin flag for PI11 */ +#define PWR_CR2_WUPP1 (1 << 8) /* Bit 8: Wakeup pin polarity bit for PA0 */ +# define PWR_CR2_WUPP1_RISING (0 << 8) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP1_FALLING (1 << 8) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP2 (1 << 9) /* Bit 9: Wakeup pin polarity bit for PA2 */ +# define PWR_CR2_WUPP2_RISING (0 << 9) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP2_FALLING (1 << 9) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP3 (1 << 10) /* Bit 10: Wakeup pin polarity bit for PC1 */ +# define PWR_CR2_WUPP3_RISING (0 << 10) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP3_FALLING (1 << 10) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP4 (1 << 11) /* Bit 11: Wakeup pin polarity bit for PC13 */ +# define PWR_CR2_WUPP4_RISING (0 << 11) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP4_FALLING (1 << 11) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP5 (1 << 12) /* Bit 12: Wakeup pin polarity bit for PI8 */ +# define PWR_CR2_WUPP5_RISING (0 << 12) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP5_FALLING (1 << 12) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP6 (1 << 13) /* Bits 13: Wakeup pin polarity bit for PI11 */ +# define PWR_CR2_WUPP6_RISING (0 << 13) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP6_FALLING (1 << 13) /* 1= Detection on falling edge */ + +/* Power control/status register 2 */ + +#define PWR_CSR2_WUPF1 (1 << 0) /* Bit 0: Wakeup Pin flag for PA0 */ +#define PWR_CSR2_WUPF2 (1 << 1) /* Bit 1: Wakeup Pin flag for PA2 */ +#define PWR_CSR2_WUPF3 (1 << 2) /* Bit 2: Wakeup Pin flag for PC1 */ +#define PWR_CSR2_WUPF4 (1 << 3) /* Bit 3: Wakeup Pin flag for PC13 */ +#define PWR_CSR2_WUPF5 (1 << 4) /* Bit 4: Wakeup Pin flag for PI8 */ +#define PWR_CSR2_WUPF6 (1 << 5) /* Bit 5: Wakeup Pin flag for PI11 */ +#define PWR_CSR2_EWUP1 (1 << 8) /* Bit 8: Enable wakeup pin for PA0 */ +#define PWR_CSR2_EWUP2 (1 << 9) /* Bit 9: Enable wakeup pin for PA2 */ +#define PWR_CSR2_EWUP3 (1 << 10) /* Bit 10: Enable wakeup pin for PC1 */ +#define PWR_CSR2_EWUP4 (1 << 11) /* Bit 11: Enable wakeup pin for PC13 */ +#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ +#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h new file mode 100644 index 0000000000..dfe85e9da2 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h @@ -0,0 +1,737 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_RCC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_RCC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_PLLCFG_OFFSET 0x0004 /* PLL configuration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_CIR_OFFSET 0x000c /* Clock interrupt register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0010 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x0014 /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0018 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR_OFFSET 0x0020 /* APB1 Peripheral reset register */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0024 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0030 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x0034 /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0038 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR_OFFSET 0x0040 /* APB1 Peripheral Clock enable register */ +#define STM32_RCC_APB2ENR_OFFSET 0x0044 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2LPENR_OFFSET 0x0054 /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3LPENR_OFFSET 0x0058 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power mode peripheral clock enable register */ +#define STM32_RCC_APB2LPENR_OFFSET 0x0064 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0074 /* Control/status register */ +#define STM32_RCC_SSCGR_OFFSET 0x0080 /* Spread spectrum clock generation register */ +#define STM32_RCC_PLLI2SCFGR_OFFSET 0x0084 /* PLLI2S configuration register */ +#define STM32_RCC_PLLSAICFGR_OFFSET 0x0088 /* PLLSAI configuration register */ +#define STM32_RCC_DCKCFGR1_OFFSET 0x008c /* Dedicated clocks configuration register 1 */ +#define STM32_RCC_DCKCFGR2_OFFSET 0x0090 /* Dedicated clocks configuration register 2 */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET) +#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR) +#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE+STM32_RCC_AHB3LPENR_OFFSET) +#define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET) +#define STM32_RCC_APB2LPENR (STM32_RCC_BASE+STM32_RCC_APB2LPENR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_SSCGR (STM32_RCC_BASE+STM32_RCC_SSCGR_OFFSET) +#define STM32_RCC_PLLI2SCFGR (STM32_RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET) +#define STM32_RCC_PLLSAICFGR (STM32_RCC_BASE+STM32_RCC_PLLSAICFGR_OFFSET) +#define STM32_RCC_DCKCFGR1 (STM32_RCC_BASE+STM32_RCC_DCKCFGR1_OFFSET) +#define STM32_RCC_DCKCFGR2 (STM32_RCC_BASE+STM32_RCC_DCKCFGR2_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* Clock control register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */ +#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT) +#define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed clock Calibration */ +#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT) +#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ +#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */ +#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */ +#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */ +#define RCC_CR_PLLI2SON (1 << 26) /* Bit 26: PLLI2S enable */ +#define RCC_CR_PLLI2SRDY (1 << 27) /* Bit 27: PLLI2S clock ready flag */ +#define RCC_CR_PLLSAION (1 << 28) /* Bit 28: PLLSAI enable */ +#define RCC_CR_PLLSAIRDY (1 << 29) /* Bit 29: PLLSAI clock ready flag */ + +/* PLL configuration register */ + +#define RCC_PLLCFG_PLLM_SHIFT (0) /* Bits 0-5: Main PLL (PLL) and audio PLL (PLLI2S) + * input clock divider */ +#define RCC_PLLCFG_PLLM_MASK (0x3f << RCC_PLLCFG_PLLM_SHIFT) +# define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT) /* n = 2..63 */ +#define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */ +#define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT) +# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */ +#define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */ +#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT) +# define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */ +# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */ +# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */ +# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */ +# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */ +#define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S) + * entry clock source */ +# define RCC_PLLCFG_PLLSRC_HSI (0) +# define RCC_PLLCFG_PLLSRC_HSE RCC_PLLCFG_PLLSRC +#define RCC_PLLCFG_PLLQ_SHIFT (24) /* Bits 24-27: Main PLL (PLL) divider + * (USB OTG FS, SDIO and RNG clocks) */ +#define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT) +# define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */ + +#define RCC_PLLCFG_PLLR_SHIFT (28) /* Bits 28-30: PLL division factor for DSI clock */ +#define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT) +# define RCC_PLLCFG_PLLR(n) ((n) << RCC_PLLCFG_PLLR_SHIFT) /* n=2..7 */ + +#define RCC_PLLCFG_RESET (0x24003010) /* PLLCFG reset value */ + +/* Clock configuration register */ + +#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ +#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT) +# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */ +# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ +# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ +#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ +#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) +# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ +# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ +# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ +#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ +#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ +# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ +# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ +# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ +# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ +# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ +#define RCC_CFGR_PPRE1_SHIFT (10) /* Bits 10-12: APB Low speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) +# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_SHIFT (13) /* Bits 13-15: APB High speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) +# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_RTCPRE_SHIFT (16) /* Bits 16-20: APB High speed prescaler (APB2) */ +#define RCC_CFGR_RTCPRE_MASK (31 << RCC_CFGR_RTCPRE_SHIFT) +# define RCC_CFGR_RTCPRE(n) ((n) << RCC_CFGR_RTCPRE_SHIFT) /* HSE/n, n=1..31 */ +#define RCC_CFGR_MCO1_SHIFT (21) /* Bits 21-22: Microcontroller Clock Output */ +#define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO1_SHIFT) +# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 00: HSI clock selected */ +# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */ +# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */ +# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */ +#define RCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */ +#define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */ +#define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT) +# define RCC_CFGR_MCO1PRE_NONE (0 << RCC_CFGR_MCO1PRE_SHIFT) /* 0xx: no division */ +# define RCC_CFGR_MCO1PRE_DIV2 (4 << RCC_CFGR_MCO1PRE_SHIFT) /* 100: division by 2 */ +# define RCC_CFGR_MCO1PRE_DIV3 (5 << RCC_CFGR_MCO1PRE_SHIFT) /* 101: division by 3 */ +# define RCC_CFGR_MCO1PRE_DIV4 (6 << RCC_CFGR_MCO1PRE_SHIFT) /* 110: division by 4 */ +# define RCC_CFGR_MCO1PRE_DIV5 (7 << RCC_CFGR_MCO1PRE_SHIFT) /* 111: division by 5 */ +#define RCC_CFGR_MCO2PRE_SHIFT (27) /* Bits 27-29: MCO2 prescaler */ +#define RCC_CFGR_MCO2PRE_MASK (7 << RCC_CFGR_MCO2PRE_SHIFT) +# define RCC_CFGR_MCO2PRE_NONE (0 << RCC_CFGR_MCO2PRE_SHIFT) /* 0xx: no division */ +# define RCC_CFGR_MCO2PRE_DIV2 (4 << RCC_CFGR_MCO2PRE_SHIFT) /* 100: division by 2 */ +# define RCC_CFGR_MCO2PRE_DIV3 (5 << RCC_CFGR_MCO2PRE_SHIFT) /* 101: division by 3 */ +# define RCC_CFGR_MCO2PRE_DIV4 (6 << RCC_CFGR_MCO2PRE_SHIFT) /* 110: division by 4 */ +# define RCC_CFGR_MCO2PRE_DIV5 (7 << RCC_CFGR_MCO2PRE_SHIFT) /* 111: division by 5 */ +#define RCC_CFGR_MCO2_SHIFT (30) /* Bits 30-31: Microcontroller clock output 2 */ +#define RCC_CFGR_MCO2_MASK (3 << RCC_CFGR_MCO2_SHIFT) +# define RCC_CFGR_MCO2_SYSCLK (0 << RCC_CFGR_MCO2_SHIFT) /* 00: System clock (SYSCLK) selected */ +# define RCC_CFGR_MCO2_PLLI2S (1 << RCC_CFGR_MCO2_SHIFT) /* 01: PLLI2S clock selected */ +# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 10: HSE oscillator clock selected */ +# define RCC_CFGR_MCO2_PLL (3 << RCC_CFGR_MCO2_SHIFT) /* 11: PLL clock selected */ + +/* Clock interrupt register */ + +#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF (1 << 2) /* Bit 2: HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF (1 << 3) /* Bit 3: HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF (1 << 4) /* Bit 4: PLL Ready Interrupt flag */ +#define RCC_CIR_PLLI2SRDYF (1 << 5) /* Bit 5: PLLI2S Ready Interrupt flag */ +#define RCC_CIR_PLLSAIRDYF (1 << 6) /* Bit 6: PLLSAI Ready Interrupt flag */ +#define RCC_CIR_CSSF (1 << 7) /* Bit 7: Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE (1 << 8) /* Bit 8: LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE (1 << 9) /* Bit 9: LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */ +#define RCC_CIR_PLLI2SRDYIE (1 << 13) /* Bit 13: PLLI2S Ready Interrupt enable */ +#define RCC_CIR_PLLSAIRDYIE (1 << 14) /* Bit 14: PLLSAI Ready Interrupt enable */ +#define RCC_CIR_LSIRDYC (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */ +#define RCC_CIR_PLLI2SRDYC (1 << 21) /* Bit 21: PLLI2S Ready Interrupt clear */ +#define RCC_CIR_PLLSAIRDYC (1 << 22) /* Bit 22: PLLSAI Ready Interrupt clear */ +#define RCC_CIR_CSSC (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */ + +/* AHB1 peripheral reset register */ + +#define RCC_AHB1RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */ +#define RCC_AHB1RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */ +#define RCC_AHB1RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */ +#define RCC_AHB1RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */ +#define RCC_AHB1RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */ +#define RCC_AHB1RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */ +#define RCC_AHB1RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ +#define RCC_AHB1RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ +#define RCC_AHB1RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */ +#define RCC_AHB1RSTR_GPIOJRST (1 << 9) /* Bit 9: IO port J reset */ +#define RCC_AHB1RSTR_GPIOKRST (1 << 10) /* Bit 10: IO port K reset */ +#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12 CRC reset */ +#define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA1 reset */ +#define RCC_AHB1RSTR_DMA2RST (1 << 22) /* Bit 22: DMA2 reset */ +#define RCC_AHB1RSTR_DMA2DRST (1 << 23) /* Bit 23: DMA2D reset */ +#define RCC_AHB1RSTR_ETHMACRST (1 << 25) /* Bit 25: Ethernet MAC reset */ +#define RCC_AHB1RSTR_OTGHSRST (1 << 29) /* Bit 29: USB OTG HS module reset */ + +/* AHB2 peripheral reset register */ + +#define RCC_AHB2RSTR_DCMIRST (1 << 0) /* Bit 0: Camera interface reset */ +#define RCC_AHB2RSTR_JPEGRST (1 << 1) /* Bit 1: Jpeg codec reset */ +#define RCC_AHB2RSTR_CRYPRST (1 << 4) /* Bit 4: Cryptographic module reset */ +#define RCC_AHB2RSTR_HASHRST (1 << 5) /* Bit 5: Hash module reset */ +#define RCC_AHB2RSTR_RNGRST (1 << 6) /* Bit 6: Random number generator module reset */ +#define RCC_AHB2RSTR_OTGFSRST (1 << 7) /* Bit 7: USB OTG FS module reset */ + +/* AHB3 peripheral reset register */ + +#define RCC_AHB3RSTR_FSMCRST (1 << 0) /* Bit 0: Flexible static memory controller module reset */ +#define RCC_AHB3RSTR_QSPIRST (1 << 1) /* Bit 1: Quad SPI memory controller reset */ + +/* APB1 Peripheral reset register */ + +#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */ +#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */ +#define RCC_APB1RSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */ +#define RCC_APB1RSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */ +#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */ +#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */ +#define RCC_APB1RSTR_TIM12RST (1 << 6) /* Bit 6: TIM12 reset */ +#define RCC_APB1RSTR_TIM13RST (1 << 7) /* Bit 7: TIM13 reset */ +#define RCC_APB1RSTR_TIM14RST (1 << 8) /* Bit 8: TIM14 reset */ +#define RCC_APB1RSTR_LPTIM1RST (1 << 9) /* Bit 9: LPTIM1 reset */ +#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window watchdog reset */ +#define RCC_APB1RSTR_CAN3RST (1 << 13) /* Bit 13: CAN3 reset */ +#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */ +#define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI 3 reset */ +#define RCC_APB1RSTR_SPDIFRXRST (1 << 16) /* Bit 16: SPDIFRX reset */ +#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */ +#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */ +#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: USART 4 reset */ +#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: USART 5 reset */ +#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */ +#define RCC_APB1RSTR_I2C3RST (1 << 23) /* Bit 23: I2C 3 reset */ +#define RCC_APB1RSTR_I2C4RST (1 << 24) /* Bit 24: I2C 4 reset */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */ +#define RCC_APB1RSTR_CAN2RST (1 << 26) /* Bit 26: CAN2 reset */ +#define RCC_APB1RSTR_CECRST (1 << 27) /* Bit 27: CEC reset */ +#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */ +#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC reset */ +#define RCC_APB1RSTR_UART7RST (1 << 30) /* Bit 30: USART 7 reset */ +#define RCC_APB1RSTR_UART8RST (1 << 31) /* Bit 31: USART 8 reset */ + +/* APB2 Peripheral reset register */ + +#define RCC_APB2RSTR_TIM1RST (1 << 0) /* Bit 0: TIM1 reset */ +#define RCC_APB2RSTR_TIM8RST (1 << 1) /* Bit 1: TIM8 reset */ +#define RCC_APB2RSTR_USART1RST (1 << 4) /* Bit 4: USART1 reset */ +#define RCC_APB2RSTR_USART6RST (1 << 5) /* Bit 5: USART6 reset */ +#define RCC_APB2RSTR_SDMMC2RST (1 << 7) /* Bit 7: SDMMC2 reset */ +#define RCC_APB2RSTR_ADCRST (1 << 8) /* Bit 8: ADC interface reset (common to all ADCs) */ +#define RCC_APB2RSTR_SDMMC1RST (1 << 11) /* Bit 11: SDMMC1 reset */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ +#define RCC_APB2RSTR_SPI4RST (1 << 13) /* Bit 13: SPI4 reset */ +#define RCC_APB2RSTR_SYSCFGRST (1 << 14) /* Bit 14: System configuration controller reset */ +#define RCC_APB2RSTR_TIM9RST (1 << 16) /* Bit 16: TIM9 reset */ +#define RCC_APB2RSTR_TIM10RST (1 << 17) /* Bit 17: TIM10 reset */ +#define RCC_APB2RSTR_TIM11RST (1 << 18) /* Bit 18: TIM11 reset */ +#define RCC_APB2RSTR_SPI5RST (1 << 20) /* Bit 20: SPI 5 reset */ +#define RCC_APB2RSTR_SPI6RST (1 << 21) /* Bit 21: SPI 6 reset */ +#define RCC_APB2RSTR_SAI1RST (1 << 22) /* Bit 22: SAI 1 reset */ +#define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 23: SAI 2 reset */ +#define RCC_APB2RSTR_LTDCRST (1 << 26) /* Bit 26: LTDC reset */ +#define RCC_APB2RSTR_DSIRST (1 << 27) /* Bit 27: DSI reset */ +#define RCC_APB2RSTR_DFSDM1RST (1 << 29) /* Bit 29: DFSDM1 reset */ +#define RCC_APB2RSTR_MDIORST (1 << 30) /* Bit 30: MDIO reset */ + +/* AHB1 Peripheral Clock enable register */ + +#define RCC_AHB1ENR_GPIOEN(n) (1 << (n)) +#define RCC_AHB1ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */ +#define RCC_AHB1ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */ +#define RCC_AHB1ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */ +#define RCC_AHB1ENR_GPIODEN (1 << 3) /* Bit 3: IO port D clock enable */ +#define RCC_AHB1ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E clock enable */ +#define RCC_AHB1ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */ +#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */ +#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */ +#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */ +#define RCC_AHB1ENR_GPIOJEN (1 << 9) /* Bit 9: IO port J clock enable */ +#define RCC_AHB1ENR_GPIOKEN (1 << 10) /* Bit 10: IO port K clock enable */ +#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ +#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */ +#define RCC_AHB1ENR_DTCMRAMEN (1 << 20) /* Bit 20: DTCM RAM clock enable */ +#define RCC_AHB1ENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */ +#define RCC_AHB1ENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */ +#define RCC_AHB1ENR_DMA2DEN (1 << 23) /* Bit 23: DMA2D clock enable */ +#define RCC_AHB1ENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */ +#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable */ +#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) /* Bit 27: Ethernet Reception clock enable */ +#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable */ +#define RCC_AHB1ENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */ +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */ + +/* AHB2 Peripheral Clock enable register */ + +#define RCC_AHB2ENR_DCMIEN (1 << 0) /* Bit 0: Camera interface enable */ +#define RCC_AHB2ENR_JPEGEN (1 << 1) /* Bit 1: Jpeg codec enable */ +#define RCC_AHB2ENR_CRYPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable */ +#define RCC_AHB2ENR_HASHEN (1 << 5) /* Bit 5: Hash modules clock enable */ +#define RCC_AHB2ENR_RNGEN (1 << 6) /* Bit 6: Random number generator clock enable */ +#define RCC_AHB2ENR_OTGFSEN (1 << 7) /* Bit 7: USB OTG FS clock enable */ + +/* AHB3 Peripheral Clock enable register */ + +#define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */ +#define RCC_AHB3ENR_QSPIEN (1 << 1) /* Bit 1: Quad SPI memory controller clock enable */ + +/* APB1 Peripheral Clock enable register */ + +#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: TIM 2 clock enable */ +#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: TIM 3 clock enable */ +#define RCC_APB1ENR_TIM4EN (1 << 2) /* Bit 2: TIM 4 clock enable */ +#define RCC_APB1ENR_TIM5EN (1 << 3) /* Bit 3: TIM 5 clock enable */ +#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: TIM 6 clock enable */ +#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: TIM 7 clock enable */ +#define RCC_APB1ENR_TIM12EN (1 << 6) /* Bit 6: TIM 12 clock enable */ +#define RCC_APB1ENR_TIM13EN (1 << 7) /* Bit 7: TIM 13 clock enable */ +#define RCC_APB1ENR_TIM14EN (1 << 8) /* Bit 8: TIM 14 clock enable */ +#define RCC_APB1ENR_LPTIM1EN (1 << 9) /* Bit 9: LPTIM 1 clock enable */ +#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */ +#define RCC_APB1ENR_CAN3EN (1 << 13) /* Bit 13: CAN 3 clock enable */ +#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */ +#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI 3 clock enable */ +#define RCC_APB1ENR_SPDIFRXEN (1 << 16) /* Bit 16: SPDIFRX clock enable */ +#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */ +#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */ +#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */ +#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */ +#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */ +#define RCC_APB1ENR_I2C3EN (1 << 23) /* Bit 23: I2C 3 clock enable */ +#define RCC_APB1ENR_I2C4EN (1 << 24) /* Bit 24: I2C 4 clock enable */ +#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN 1 clock enable */ +#define RCC_APB1ENR_CAN2EN (1 << 26) /* Bit 26: CAN 2 clock enable */ +#define RCC_APB1ENR_CECEN (1 << 27) /* Bit 27: CEC clock enable */ +#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */ +#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */ +#define RCC_APB1ENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */ +#define RCC_APB1ENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */ + +/* APB2 Peripheral Clock enable register */ + +#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: TIM 1 clock enable */ +#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: TIM 8 clock enable */ +#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: USART 1 clock enable */ +#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: USART 6 clock enable */ +#define RCC_APB2ENR_SDMMC2EN (1 << 7) /* Bit 7: SDMMC 2 clock enable */ +#define RCC_APB2ENR_ADC1EN (1 << 8) /* Bit 8: ADC 1 clock enable */ +#define RCC_APB2ENR_ADC2EN (1 << 9) /* Bit 9: ADC 2 clock enable */ +#define RCC_APB2ENR_ADC3EN (1 << 10) /* Bit 10: ADC 3 clock enable */ +#define RCC_APB2ENR_SDMMC1EN (1 << 11) /* Bit 11: SDMMC 1 clock enable */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 clock enable */ +#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: SPI 4 clock enable */ +#define RCC_APB2ENR_SYSCFGEN (1 << 14) /* Bit 14: System configuration controller clock enable */ +#define RCC_APB2ENR_TIM9EN (1 << 16) /* Bit 16: TIM 9 clock enable */ +#define RCC_APB2ENR_TIM10EN (1 << 17) /* Bit 17: TIM1 0 clock enable */ +#define RCC_APB2ENR_TIM11EN (1 << 18) /* Bit 18: TIM 11 clock enable */ +#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: SPI 5 clock enable */ +#define RCC_APB2ENR_SPI6EN (1 << 21) /* Bit 21: SPI 6 clock enable */ +#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: SAI 1 clock enable */ +#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: SAI 2 clock enable */ +#define RCC_APB2ENR_LTDCEN (1 << 26) /* Bit 26: LTDC clock enable */ +#define RCC_APB2ENR_DSIEN (1 << 27) /* Bit 27: DSI clock enable */ +#define RCC_APB2ENR_DFSDM1EN (1 << 29) /* Bit 29: DFSDM1 clock enable */ +#define RCC_APB2ENR_MDIOEN (1 << 30) /* Bit 30: MDIO clock enable */ + +/* RCC AHB1 low power mode peripheral clock enable register */ + +#define RCC_AHB1LPENR_GPIOLPEN(n) (1 << (n)) +#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOJLPEN (1 << 9) /* Bit 8: IO port J clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOKLPEN (1 << 10) /* Bit 10: IO port K clock enable during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */ +#define RCC_AHB1LPENR_AXILPEN (1 << 13) /* Bit 12: AXI to AHB bridge clock enable during Sleep mode */ +#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DTCMLPEN (1 << 20) /* Bit 20: DTCM RAM clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DMA2DLPEN (1 << 23) /* Bit 23: DMA2D clock enable during Sleep mode */ +#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */ +#define RCC_AHB1LPENR_ETHTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */ +#define RCC_AHB1LPENR_ETHRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */ + +#define RCC_AHB1LPENR_ETHPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */ +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */ +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */ + +/* RCC AHB2 low power mode peripheral clock enable register */ + +#define RCC_AHB2LPENR_DCMILPEN (1 << 0) /* Bit 0: Camera interface enable during Sleep mode */ +#define RCC_AHB2LPENR_JPEGLPEN (1 << 1) /* Bit 1: Jpeg codec enable during Sleep mode */ +#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable during Sleep mode */ +#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* Bit 5: Hash modules clock enable during Sleep mode */ +#define RCC_AHB2LPENR_RNGLPEN (1 << 6) /* Bit 6: Random number generator clock enable during Sleep mode */ +#define RCC_AHB2LPENR_OTGFLPSEN (1 << 7) /* Bit 7: USB OTG FS clock enable during Sleep mode */ + +/* RCC AHB3 low power mode peripheral clock enable register */ + +#define RCC_AHB3LPENR_FSMLPEN (1 << 0) /* Bit 0: Flexible static memory controller module clock + * enable during Sleep mode */ +#define RCC_AHB3LPENR_QSPILPEN (1 << 1) /* Bit 1: Quad SPI memory controller clock + * enable during Sleep mode */ + +/* RCC APB1 low power mode peripheral clock enable register */ + +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM 4 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM 5 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM 6 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM 7 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM 12 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM 13 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM 14 clock enable during Sleep mode */ +#define RCC_APB1LPENR_LPTIM1LPEN (1 << 9) /* Bit 9: LPTIM 1 clock enable during Sleep mode */ +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) /* Bit 11: Window watchdog clock enable during Sleep mode */ +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_SPDIFRXLPEN (1 << 16) /* Bit 16: SPDIFRX clock enable during Sleep mode */ +#define RCC_APB1LPENR_USART2LPEN (1 << 17) /* Bit 17: USART 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_USART3LPEN (1 << 18) /* Bit 18: USART 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART4LPEN (1 << 19) /* Bit 19: UART 4 clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART5LPEN (1 << 20) /* Bit 20: UART 5 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C 1 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C3LPEN (1 << 23) /* Bit 23: I2C 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C4LPEN (1 << 24) /* Bit 24: I2C 4 clock enable during Sleep mode */ +#define RCC_APB1LPENR_CAN1LPEN (1 << 25) /* Bit 25: CAN 1 clock enable during Sleep mode */ +#define RCC_APB1LPENR_CAN2LPEN (1 << 26) /* Bit 26: CAN 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_CECLPEN (1 << 27) /* Bit 27: CEC clock enable during Sleep mode */ +#define RCC_APB1LPENR_PWRLPEN (1 << 28) /* Bit 28: Power interface clock enable during Sleep mode */ +#define RCC_APB1LPENR_DACLPEN (1 << 29) /* Bit 29: DAC interface clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART7LPEN (1 << 30) /* Bit 30: UART 7 clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART8LPEN (1 << 31) /* Bit 31: UART 8 clock enable during Sleep mode */ + +/* RCC APB2 low power mode peripheral clock enable register */ + +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* Bit 0: TIM 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* Bit 1: TIM 8 clock enable during Sleep mode */ +#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* Bit 4: USART 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* Bit 5: USART 6 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SDMMC2LPEN (1 << 7) /* Bit 7: SDMMC 2 clock enable during Sleep mode */ +#define RCC_APB2LPENR_ADC1LPEN (1 << 8) /* Bit 8: ADC 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_ADC2LPEN (1 << 9) /* Bit 9: ADC 2 clock enable during Sleep mode */ +#define RCC_APB2LPENR_ADC3LPEN (1 << 10) /* Bit 10: ADC 3 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SDMMC1LPEN (1 << 11) /* Bit 11: SDMMC 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI 4 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) /* Bit 14: System configuration controller clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM9LPEN (1 << 16) /* Bit 16: TIM 9 clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM10LPEN (1 << 17) /* Bit 17: TIM 10 clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM11LPEN (1 << 18) /* Bit 18: TIM 11 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* Bit 20: SPI 5 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI6LPEN (1 << 21) /* Bit 21: SPI 6 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* Bit 22: SAI 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* Bit 23: SAI 2 clock enable during Sleep mode */ +#define RCC_APB2LPENR_LTDCLPEN (1 << 26) /* Bit 26: LTDC clock enable during Sleep mode */ +#define RCC_APB2LPENR_DSILPEN (1 << 27) /* Bit 27: DSI clock enable during Sleep mode */ +#define RCC_APB2LPENR_DFSDM1LPEN (1 << 29) /* Bit 29: DFSDM1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_MDIOLPEN (1 << 30) /* Bit 30: MDIO clock enable during Sleep mode */ + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ + +/* Control/status register */ + +#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */ +#define RCC_CSR_BORRSTF (1 << 25) /* Bit 25: BOR reset flag */ +#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ +#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ +#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ + +/* Spread spectrum clock generation register */ + +#define RCC_SSCGR_MODPER_SHIFT (0) /* Bit 0-12: Modulation period */ +#define RCC_SSCGR_MODPER_MASK (0x1fff << RCC_SSCGR_MODPER_SHIFT) +# define RCC_SSCGR_MODPER(n) ((n) << RCC_SSCGR_MODPER_SHIFT) +#define RCC_SSCGR_INCSTEP_SHIFT (13) /* Bit 13-27: Incrementation step */ +#define RCC_SSCGR_INCSTEP_MASK (0x7fff << RCC_SSCGR_INCSTEP_SHIFT) +# define RCC_SSCGR_INCSTEP(n) ((n) << RCC_SSCGR_INCSTEP_SHIFT) +#define RCC_SSCGR_SPREADSEL (1 << 30) /* Bit 30: Spread Select */ +#define RCC_SSCGR_SSCGEN (1 << 31) /* Bit 31: Spread spectrum modulation enable */ + +/* PLLI2S configuration register */ + +#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT (6) /* Bits 6-14: PLLI2S multiplication factor for VCO */ +#define RCC_PLLI2SCFGR_PLLI2SN_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SN(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) +#define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIFRX clock */ +#define RCC_PLLI2SCFGR_PLLI2SP_MASK (3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SP(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) +#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAIs clock */ +#define RCC_PLLI2SCFGR_PLLI2SQ_MASK (15 << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SQ(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) +#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */ +#define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SR(n) (uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) + +/* PLLSAI configuration register */ + +#define RCC_PLLSAICFGR_PLLSAIN_SHIFT (6) /* Bits 6-14: PLLSAI divider (N) for VCO */ +#define RCC_PLLSAICFGR_PLLSAIN_MASK (0x1ff << RCC_PLLSAICFGR_PLLSAIN_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT) +#define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48MHz clock */ +#define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIP(n) ((n) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) +#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */ +#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) +#define RCC_PLLSAICFGR_PLLSAIR_SHIFT (28) /* Bits 28-30: PLLSAI division factor for LCD clock */ +#define RCC_PLLSAICFGR_PLLSAIR_MASK (7 << RCC_PLLSAICFGR_PLLSAIR_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIR(n) ((n) << RCC_PLLSAICFGR_PLLSAIR_SHIFT) + +/* Dedicated clocks configuration register 1 */ + +#define RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT (0) /* Bits 0-4: PLLI2S division factor for I2S clock */ +#define RCC_DCKCFGR1_PLLI2SDIVQ_MASK (0x1F << RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT) +# define RCC_DCKCFGR1_PLLI2SDIVQ(n) ((n) << RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT) +#define RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT (8) /* Bits 8-12: PLLSAI division factor for SAI clock */ +#define RCC_DCKCFGR1_PLLSAIDIVQ_MASK (0x1F << RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT) +# define RCC_DCKCFGR1_PLLSAIDIVQ(n) ((n) << RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT) + +#define RCC_DCKCFGR1_PLLSAIDIVR_SHIFT (16) /* Bits 16-17: PLLSAI division factor for LCD_CLK clock */ +#define RCC_DCKCFGR1_PLLSAIDIVR_MASK (0x3 << RCC_DCKCFGR1_PLLSAIDIVR_SHIFT) +# define RCC_DCKCFGR1_PLLSAIDIVR(n) ((n) << RCC_DCKCFGR1_PLLSAIDIVR_SHIFT) + +#define RCC_DCKCFGR1_SAI1SEL_SHIFT (20) /* Bits 20-21: SAI 1 clock source selection */ +#define RCC_DCKCFGR1_SAI1SEL_MASK (0x3 << RCC_DCKCFGR1_SAI1SEL_SHIFT) +# define RCC_DCKCFGR1_SAI1SEL(n) ((n) << RCC_DCKCFGR1_SAI1SEL_SHIFT) + +#define RCC_DCKCFGR1_SAI2SEL_SHIFT (22) /* Bits 22-23: SAI 2 clock source selection */ +#define RCC_DCKCFGR1_SAI2SEL_MASK (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT) +# define RCC_DCKCFGR1_SAI2SEL(n) ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT) +#define RCC_DCKCFGR1_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */ +#define RCC_DCKCFGR1_DFSDM1SEL (1 << 25) /* Bit 25: DFSDM1 clock prescaler selection */ +#define RCC_DCKCFGR1_ADFSDM1SEL (1 << 26) /* Bit 26: DFSDM1 AUDIO clock prescaler selection */ + +/* Dedicated clocks configuration register 2 */ + +#define RCC_DCKCFGR2_USART1SEL_SHIFT (0) /* Bits 0-1: USART 1 clock source selection */ +#define RCC_DCKCFGR2_USART1SEL_MASK (3 << RCC_DCKCFGR2_USART1SEL_SHIFT) +# define RCC_DCKCFGR2_USART1SEL_APB (0 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* APB2 clock (PCLK2) is selected as USART 1 clock */ +# define RCC_DCKCFGR2_USART1SEL_SYSCLK (1 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* System clock is selected as USART 1 clock */ +# define RCC_DCKCFGR2_USART1SEL_HSI (2 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* HSI clock is selected as USART 1 clock */ +# define RCC_DCKCFGR2_USART1SEL_LSE (3 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* LSE clock is selected as USART 1 clock */ +#define RCC_DCKCFGR2_USART2SEL_SHIFT (2) /* Bits 2-3: USART 2 clock source selection */ +#define RCC_DCKCFGR2_USART2SEL_MASK (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) +# define RCC_DCKCFGR2_USART2SEL_APB (0 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as USART 2 clock */ +# define RCC_DCKCFGR2_USART2SEL_SYSCLK (1 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* System clock is selected as USART 2 clock */ +# define RCC_DCKCFGR2_USART2SEL_HSI (2 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* HSI clock is selected as USART 2 clock */ +# define RCC_DCKCFGR2_USART2SEL_LSE (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* LSE clock is selected as USART 2 clock */ +#define RCC_DCKCFGR2_UART4SEL_SHIFT (6) /* Bits 6-7: UART 4 clock source selection */ +#define RCC_DCKCFGR2_UART4SEL_MASK (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) +# define RCC_DCKCFGR2_UART4SEL_APB (0 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 4 clock */ +# define RCC_DCKCFGR2_UART4SEL_SYSCLK (1 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* System clock is selected as UART 4 clock */ +# define RCC_DCKCFGR2_UART4SEL_HSI (2 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* HSI clock is selected as UART 4 clock */ +# define RCC_DCKCFGR2_UART4SEL_LSE (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* LSE clock is selected as UART 4 clock */ +#define RCC_DCKCFGR2_UART5SEL_SHIFT (8) /* Bits 8-9: UART 5 clock source selection */ +#define RCC_DCKCFGR2_UART5SEL_MASK (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) +# define RCC_DCKCFGR2_UART5SEL_APB (0 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 5 clock */ +# define RCC_DCKCFGR2_UART5SEL_SYSCLK (1 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* System clock is selected as UART 5 clock */ +# define RCC_DCKCFGR2_UART5SEL_HSI (2 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* HSI clock is selected as UART 5 clock */ +# define RCC_DCKCFGR2_UART5SEL_LSE (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* LSE clock is selected as UART 5 clock */ +#define RCC_DCKCFGR2_USART6SEL_SHIFT (10) /* Bits 10-11: USART 6 clock source selection */ +#define RCC_DCKCFGR2_USART6SEL_MASK (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) +# define RCC_DCKCFGR2_USART6SEL_APB (0 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* APB2 clock (PCLK2) is selected as USART 6 clock */ +# define RCC_DCKCFGR2_USART6SEL_SYSCLK (1 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* System clock is selected as USART 6 clock */ +# define RCC_DCKCFGR2_USART6SEL_HSI (2 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* HSI clock is selected as USART 6 clock */ +# define RCC_DCKCFGR2_USART6SEL_LSE (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* LSE clock is selected as USART 6 clock */ +#define RCC_DCKCFGR2_UART7SEL_SHIFT (12) /* Bits 12-13: UART 7 clock source selection */ +#define RCC_DCKCFGR2_UART7SEL_MASK (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) +# define RCC_DCKCFGR2_UART7SEL_APB (0 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 7 clock */ +# define RCC_DCKCFGR2_UART7SEL_SYSCLK (1 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* System clock is selected as UART 7 clock */ +# define RCC_DCKCFGR2_UART7SEL_HSI (2 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* HSI clock is selected as UART 7 clock */ +# define RCC_DCKCFGR2_UART7SEL_LSE (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* LSE clock is selected as UART 7 clock */ +#define RCC_DCKCFGR2_UART8SEL_SHIFT (14) /* Bits 14-15: UART 8 clock source selection */ +#define RCC_DCKCFGR2_UART8SEL_MASK (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) +# define RCC_DCKCFGR2_UART8SEL_APB (0 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 8 clock */ +# define RCC_DCKCFGR2_UART8SEL_SYSCLK (1 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* System clock is selected as UART 8 clock */ +# define RCC_DCKCFGR2_UART8SEL_HSI (2 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* HSI clock is selected as UART 8 clock */ +# define RCC_DCKCFGR2_UART8SEL_LSE (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* LSE clock is selected as UART 8 clock */ +#define RCC_DCKCFGR2_I2C1SEL_SHIFT (16) /* Bits 16-17: I2C1 clock source selection */ +#define RCC_DCKCFGR2_I2C1SEL_MASK (3 << RCC_DCKCFGR2_I2C1SEL_SHIFT) +# define RCC_DCKCFGR2_I2C1SEL_APB (0 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 1 clock */ +# define RCC_DCKCFGR2_I2C1SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* System clock is selected as I2C 1 clock */ +# define RCC_DCKCFGR2_I2C1SEL_HSI (2 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* HSI clock is selected as I2C 1 clock */ +#define RCC_DCKCFGR2_I2C2SEL_SHIFT (18) /* Bits 18-19: I2C2 clock source selection */ +#define RCC_DCKCFGR2_I2C2SEL_MASK (3 << RCC_DCKCFGR2_I2C2SEL_SHIFT) +# define RCC_DCKCFGR2_I2C2SEL_APB (0 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 2 clock */ +# define RCC_DCKCFGR2_I2C2SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* System clock is selected as I2C 2 clock */ +# define RCC_DCKCFGR2_I2C2SEL_HSI (2 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* HSI clock is selected as I2C 2 clock */ +#define RCC_DCKCFGR2_I2C3SEL_SHIFT (20) /* Bits 20-21: I2C3 clock source selection */ +#define RCC_DCKCFGR2_I2C3SEL_MASK (3 << RCC_DCKCFGR2_I2C3SEL_SHIFT) +# define RCC_DCKCFGR2_I2C3SEL_APB (0 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 3 clock */ +# define RCC_DCKCFGR2_I2C3SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* System clock is selected as I2C 3 clock */ +# define RCC_DCKCFGR2_I2C3SEL_HSI (2 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* HSI clock is selected as I2C 3 clock */ +#define RCC_DCKCFGR2_I2C4SEL_SHIFT (22) /* Bits 22-23: I2C4 clock source selection */ +#define RCC_DCKCFGR2_I2C4SEL_MASK (3 << RCC_DCKCFGR2_I2C4SEL_SHIFT) +# define RCC_DCKCFGR2_I2C4SEL_APB (0 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 4 clock */ +# define RCC_DCKCFGR2_I2C4SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* System clock is selected as I2C 4 clock */ +# define RCC_DCKCFGR2_I2C4SEL_HSI (2 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* HSI clock is selected as I2C 4 clock */ +#define RCC_DCKCFGR2_LPTIM1SEL_SHIFT (24) /* Bits 24-25: Low power timer 1 clock source selection */ +#define RCC_DCKCFGR2_LPTIM1SEL_MASK (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) +# define RCC_DCKCFGR2_LPTIM1SEL_APB (0 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as LPTIM 1 clock */ +# define RCC_DCKCFGR2_LPTIM1SEL_SYSCLK (1 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* System clock is selected as LPTIM 1 clock */ +# define RCC_DCKCFGR2_LPTIM1SEL_HSI (2 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* HSI clock is selected as LPTIM 1 clock */ +# define RCC_DCKCFGR2_LPTIM1SEL_LSE (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* LSE clock is selected as LPTIM 1 clock */ +#define RCC_DCKCFGR2_CECSEL_SHIFT (26) /* Bit 26: HDMI-CEC clock source selection */ +#define RCC_DCKCFGR2_CECSEL_MASK (1 << RCC_DCKCFGR2_CECSEL_SHIFT) +# define RCC_DCKCFGR2_CECSEL_LSE (0 << RCC_DCKCFGR2_CECSEL_SHIFT) /* LSE clock is selected as HDMI-CEC clock */ +# define RCC_DCKCFGR2_CECSEL_HSI (1 << RCC_DCKCFGR2_CECSEL_SHIFT) /* HSI clock is selected as HDMI-CEC clock */ +#define RCC_DCKCFGR2_CK48MSEL_SHIFT (27) /* Bit 27: 48MHz clock source selection */ +#define RCC_DCKCFGR2_CK48MSEL_MASK (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) +# define RCC_DCKCFGR2_CK48MSEL_PLL (0 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48MHz clock from PLL is selected */ +# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /*48MHz clock from PLLSAI is selected */ +#define RCC_DCKCFGR2_SDMMCSEL_SHIFT (28) /* Bit 28: SDMMC clock source selection */ +#define RCC_DCKCFGR2_SDMMCSEL_MASK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) +# define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ +# define RCC_DCKCFGR2_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */ +#define RCC_DCKCFGR2_SDMMC2SEL_SHIFT (29) /* Bit 29: SDMMC 2 clock source selection */ +#define RCC_DCKCFGR2_SDMMC2SEL_MASK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) +# define RCC_DCKCFGR2_SDMMC2SEL_48MHZ (0 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* 48 MHz clock is selected as SDMMC 2 clock */ +# define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* System clock is selected as SDMMC 2 clock */ +#define RCC_DCKCFGR2_DSISEL_SHIFT (30) /* Bit 30: DSI clock source selection */ +#define RCC_DCKCFGR2_DSISELL_MASK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) +# define RCC_DCKCFGR2_DSISEL_48MHZ (0 << RCC_DCKCFGR2_DSISEL_SHIFT) /* 48 MHz clock is selected as DSI clock */ +# define RCC_DCKCFGR2_DSISEL_SYSCLK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) /* System clock is selected as DSI clock */ + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h new file mode 100644 index 0000000000..78d25453f6 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h @@ -0,0 +1,180 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */ + +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ + +#define STM32_SYSCFG_CBR_OFFSET 0x001c /* Class B register */ +#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET) + +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) + +#define STM32_SYSCFG_CBR (STM32_SYSCFG_BASE+STM32_SYSCFG_CBR_OFFSET) +#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* SYSCFG memory remap register */ + +#define SYSCFG_MEMRMP_MEMBOOT (1 << 0) /* Bit 0: Memory boot mapping */ +#define SYSCFG_MEMRMP_MEMBOOT_ADD0 (0 << 0) /* 0=BOOT_ADD0 defines */ +#define SYSCFG_MEMRMP_MEMBOOT_ADD1 (1 << 0) /* 1=BOOT_ADD1 defines */ +#define SYSCFG_MEMRMP_SWP_FB (1 << 8) /* Bits 8: Flash Bank swap */ +#define SYSCFG_MEMRMP_SWP_FB_BNK1 (0 << 8) /* Flash Bank 1 mapped at 0x08000000 + * Flash Bank 2 mapped at 0x08100000 */ +#define SYSCFG_MEMRMP_SWP_FB_BNK2 (1 << 8) /* Flash Bank 2 mapped at 0x08000000 + * Flash Bank 1 mapped at 0x08100000 */ +#define SYSCFG_MEMRMP_SWPFMC_SHIFT (10) /* Bits 10-11: FMC memory mapping swap */ +#define SYSCFG_MEMRMP_SWPFMC_MASK (3 << SYSCFG_MEMRMP_SWPFMC_SHIFT) +# define SYSCFG_MEMRMP_SWPFMC_NONE (0 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* No FMC memory mapping swapping */ +# define SYSCFG_MEMRMP_SWPFMC_NORRAM (1 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* NOR/RAM and SDRAM memory mapping swapped */ + +/* SYSCFG peripheral mode configuration register */ + +#define SYSCFG_PMC_I2C1_FMP (1 << 0) /* Bit 0: I2C1 Fast-mode Plus Enable */ +#define SYSCFG_PMC_I2C2_FMP (1 << 1) /* Bit 1: I2C2 Fast-mode Plus Enable */ +#define SYSCFG_PMC_I2C3_FMP (1 << 2) /* Bit 2: I2C3 Fast-mode Plus Enable */ +#define SYSCFG_PMC_I2C4_FMP (1 << 3) /* Bit 3: I2C4 Fast-mode Plus Enable */ +#define SYSCFG_PMC_PB6_FMP (1 << 4) /* Bit 4: PB6 IO pads Fast-mode Plus Enable */ +#define SYSCFG_PMC_PB7_FMP (1 << 5) /* Bit 5: PB7 IO pads Fast-mode Plus Enable */ +#define SYSCFG_PMC_PB8_FMP (1 << 6) /* Bit 6: PB8 IO pads Fast-mode Plus Enable */ +#define SYSCFG_PMC_PB9_FMP (1 << 7) /* Bit 7: PB9 IO pads Fast-mode Plus Enable */ +#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */ +#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */ +#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */ +#define SYSCFG_PMC_MII_RMII_SEL (1 << 23) /* Bit 23: Ethernet PHY interface selection */ +# define SYSCFG_PMC_MII_SEL (0 << 23) /* 0 selects MII */ +# define SYSCFG_PMC_RMII_SEL (1 << 23) /* 1 selects RMII */ + +/* SYSCFG external interrupt configuration register 1-4 */ + +#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */ +#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */ +#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */ +#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */ +#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */ +#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */ +#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */ +#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */ +#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */ +#define SYSCFG_EXTICR_PORTJ (9) /* 1001: PJ[x] pin */ +#define SYSCFG_EXTICR_PORTK (10) /* 1010: PK[x] pin */ + +#define SYSCFG_EXTICR_PORT_MASK (15) +#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2) +#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g))) + +#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT) +#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT) +#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT) +#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT) + +#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT) +#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT) +#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT) +#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT) + +#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT) +#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT) +#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT) +#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT) + +#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT) +#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT) +#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT) +#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) + +/* Class B register */ + +#define SYSCFG_CBR_PVD (1 << 0) /* Bit 0: PVDL: PVD Lock */ +#define SYSCFG_CBR_CLL (1 << 2) /* Bit 2: CLL Core Lockup Lock*/ + +/* Compensation cell control register */ + +#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ +#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index ff904c1d6b..eab3412fbe 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -59,7 +59,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index e1772e89cd..24429b01e2 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -57,7 +57,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** * Private Data diff --git a/arch/arm/src/stm32f7/stm32_exti_gpio.c b/arch/arm/src/stm32f7/stm32_exti_gpio.c index 7c15027563..ec4cd1a7d7 100644 --- a/arch/arm/src/stm32f7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f7/stm32_exti_gpio.c @@ -65,7 +65,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** * Private Data diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index ee4e0f819b..0cd386725f 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -57,7 +57,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** * Public Data diff --git a/arch/arm/src/stm32f7/stm32_rcc.c b/arch/arm/src/stm32f7/stm32_rcc.c index bd1d1e7bca..21cac17ad7 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.c +++ b/arch/arm/src/stm32f7/stm32_rcc.c @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/stm32_rcc.c * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -75,6 +76,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "stm32f74xx75xx_rcc.c" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "stm32f76xx77xx_rcc.c" #else # error "Unsupported STM32 F7 chip" #endif diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c new file mode 100644 index 0000000000..74d58b52ad --- /dev/null +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -0,0 +1,886 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32f76xxx77xx_rcc.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "stm32_pwr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. Normally this is very fast, but I have seen at least one + * board that required this long, long timeout for the HSE to be ready. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/* Same for HSI */ + +#define HSIRDY_TIMEOUT HSERDY_TIMEOUT + +/* HSE divisor to yield ~1MHz RTC clock */ + +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 + +/* FLASH wait states */ + +#if !defined(BOARD_FLASH_WAITSTATES) +# error BOARD_FLASH_WAITSTATES not defined +#elif BOARD_FLASH_WAITSTATES < 0 || BOARD_FLASH_WAITSTATES > 15 +# error BOARD_FLASH_WAITSTATES is out of range +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Reset the RCC clock configuration to the default reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ + uint32_t regval; + + /* Enable the Internal High Speed clock (HSI) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSION; + putreg32(regval, STM32_RCC_CR); + + /* Reset CFGR register */ + + putreg32(0x00000000, STM32_RCC_CFGR); + + /* Reset HSION, HSEON, CSSON and PLLON bits */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); + putreg32(regval, STM32_RCC_CR); + + /* Reset PLLCFGR register to reset default */ + + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); + + /* Reset HSEBYP bit */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_HSEBYP; + putreg32(regval, STM32_RCC_CR); + + /* Disable all interrupts */ + + putreg32(0x00000000, STM32_RCC_CIR); +} + +/**************************************************************************** + * Name: rcc_enableahb1 + * + * Description: + * Enable selected AHB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB1ENR register to enabled the + * selected AHB1 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB1ENR); + + /* Enable GPIOA, GPIOB, .... GPIOI */ + +#if STM32F7_NGPIO > 0 + regval |= (RCC_AHB1ENR_GPIOAEN +#if STM32F7_NGPIO > 1 + | RCC_AHB1ENR_GPIOBEN +#endif +#if STM32F7_NGPIO > 2 + | RCC_AHB1ENR_GPIOCEN +#endif +#if STM32F7_NGPIO > 3 + | RCC_AHB1ENR_GPIODEN +#endif +#if STM32F7_NGPIO > 4 + | RCC_AHB1ENR_GPIOEEN +#endif +#if STM32F7_NGPIO > 5 + | RCC_AHB1ENR_GPIOFEN +#endif +#if STM32F7_NGPIO > 6 + | RCC_AHB1ENR_GPIOGEN +#endif +#if STM32F7_NGPIO > 7 + | RCC_AHB1ENR_GPIOHEN +#endif +#if STM32F7_NGPIO > 8 + | RCC_AHB1ENR_GPIOIEN +#endif +#if STM32F7_NGPIO > 9 + | RCC_AHB1ENR_GPIOJEN +#endif +#if STM32F7_NGPIO > 10 + | RCC_AHB1ENR_GPIOKEN +#endif + ); +#endif + +#ifdef CONFIG_STM32F7_CRC + /* CRC clock enable */ + + regval |= RCC_AHB1ENR_CRCEN; +#endif + +#ifdef CONFIG_STM32F7_BKPSRAM + /* Backup SRAM clock enable */ + + regval |= RCC_AHB1ENR_BKPSRAMEN; +#endif + +#ifdef CONFIG_ARMV7M_DTCM + /* DTCM data RAM clock enable */ + + regval |= RCC_AHB1ENR_DTCMRAMEN; +#endif + +#ifdef CONFIG_STM32F7_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHB1ENR_DMA1EN; +#endif + +#ifdef CONFIG_STM32F7_DMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHB1ENR_DMA2EN; +#endif + +#ifdef CONFIG_STM32F7_DMA2D + /* DMA2D clock */ + + regval |= RCC_AHB1ENR_DMA2DEN; +#endif + +#ifdef CONFIG_STM32F7_ETHMAC + /* Ethernet MAC clocking */ + + regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN); + +#ifdef CONFIG_STM32F7_ETH_PTP + /* Precision Time Protocol (PTP) */ + + regval |= RCC_AHB1ENR_ETHMACPTPEN; + +#endif +#endif + +#ifdef CONFIG_STM32F7_OTGHS + /* USB OTG HS */ + + regval |= RCC_AHB1ENR_OTGHSEN; +#endif /* CONFIG_STM32F7_OTGHS */ + + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb2 + * + * Description: + * Enable selected AHB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB2ENR register to enabled the + * selected AHB2 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB2ENR); + +#ifdef CONFIG_STM32F7_DCMI + /* Camera interface enable */ + + regval |= RCC_AHB2ENR_DCMIEN; +#endif + +#ifdef CONFIG_STM32F7_CRYP + /* Cryptographic modules clock enable */ + + regval |= RCC_AHB2ENR_CRYPEN; +#endif + +#ifdef CONFIG_STM32F7_HASH + /* Hash modules clock enable */ + + regval |= RCC_AHB2ENR_HASHEN; +#endif + +#ifdef CONFIG_STM32F7_RNG + /* Random number generator clock enable */ + + regval |= RCC_AHB2ENR_RNGEN; +#endif + +#ifdef CONFIG_STM32F7_OTGFS + /* USB OTG FS clock enable */ + + regval |= RCC_AHB2ENR_OTGFSEN; +#endif + + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb3 + * + * Description: + * Enable selected AHB3 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb3(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB3ENR register to enabled the + * selected AHB3 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB3ENR); + +#ifdef CONFIG_STM32F7_FSMC + /* Flexible static memory controller module clock enable */ + + regval |= RCC_AHB3ENR_FSMCEN; +#endif + +#ifdef CONFIG_STM32F7_QUADSPI + /* FQuad SPI memory controller clock enable */ + + regval |= RCC_AHB3ENR_QSPIEN; +#endif + + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1ENR register to enabled the + * selected APB1 peripherals. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + +#ifdef CONFIG_STM32F7_TIM2 + /* TIM2 clock enable */ + + regval |= RCC_APB1ENR_TIM2EN; +#endif + +#ifdef CONFIG_STM32F7_TIM3 + /* TIM3 clock enable */ + + regval |= RCC_APB1ENR_TIM3EN; +#endif + +#ifdef CONFIG_STM32F7_TIM4 + /* TIM4 clock enable */ + + regval |= RCC_APB1ENR_TIM4EN; +#endif + +#ifdef CONFIG_STM32F7_TIM5 + /* TIM5 clock enable */ + + regval |= RCC_APB1ENR_TIM5EN; +#endif + +#ifdef CONFIG_STM32F7_TIM6 + /* TIM6 clock enable */ + + regval |= RCC_APB1ENR_TIM6EN; +#endif + +#ifdef CONFIG_STM32F7_TIM7 + /* TIM7 clock enable */ + + regval |= RCC_APB1ENR_TIM7EN; +#endif + +#ifdef CONFIG_STM32F7_TIM12 + /* TIM12 clock enable */ + + regval |= RCC_APB1ENR_TIM12EN; +#endif + +#ifdef CONFIG_STM32F7_TIM13 + /* TIM13 clock enable */ + + regval |= RCC_APB1ENR_TIM13EN; +#endif + +#ifdef CONFIG_STM32F7_TIM14 + /* TIM14 clock enable */ + + regval |= RCC_APB1ENR_TIM14EN; +#endif + +#ifdef CONFIG_STM32F7_LPTIM1 + /* Low-power timer 1 clock enable */ + + regval |= RCC_APB1ENR_LPTIM1EN; +#endif + +#ifdef CONFIG_STM32F7_WWDG + /* Window watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + +#ifdef CONFIG_STM32F7_SPI2 + /* SPI2 clock enable */ + + regval |= RCC_APB1ENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32F7_SPI3 + /* SPI3 clock enable */ + + regval |= RCC_APB1ENR_SPI3EN; +#endif + +#ifdef CONFIG_STM32F7_SPDIFRX + /* SPDIFRX clock enable */ + + regval |= RCC_APB1ENR_SPDIFRXEN; +#endif + +#ifdef CONFIG_STM32F7_USART2 + /* USART 2 clock enable */ + + regval |= RCC_APB1ENR_USART2EN; +#endif + +#ifdef CONFIG_STM32F7_USART3 + /* USART3 clock enable */ + + regval |= RCC_APB1ENR_USART3EN; +#endif + +#ifdef CONFIG_STM32F7_UART4 + /* UART4 clock enable */ + + regval |= RCC_APB1ENR_UART4EN; +#endif + +#ifdef CONFIG_STM32F7_UART5 + /* UART5 clock enable */ + + regval |= RCC_APB1ENR_UART5EN; +#endif + +#ifdef CONFIG_STM32F7_I2C1 + /* I2C1 clock enable */ + + regval |= RCC_APB1ENR_I2C1EN; +#endif + +#ifdef CONFIG_STM32F7_I2C2 + /* I2C2 clock enable */ + + regval |= RCC_APB1ENR_I2C2EN; +#endif + +#ifdef CONFIG_STM32F7_I2C3 + /* I2C3 clock enable */ + + regval |= RCC_APB1ENR_I2C3EN; +#endif + +#ifdef CONFIG_STM32F7_I2C4 + /* I2C4 clock enable */ + + regval |= RCC_APB1ENR_I2C4EN; +#endif + +#ifdef CONFIG_STM32F7_CAN1 + /* CAN 1 clock enable */ + + regval |= RCC_APB1ENR_CAN1EN; +#endif + +#ifdef CONFIG_STM32F7_CAN2 + /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ + + regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); +#endif + +#ifdef CONFIG_STM32F7_CEC + /* CEC clock enable. */ + + regval |= RCC_APB1ENR_CECEN; +#endif + + /* Power interface clock enable. The PWR block is always enabled so that + * we can set the internal voltage regulator for maximum performance. + */ + + regval |= RCC_APB1ENR_PWREN; + +#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) + /* DAC interface clock enable */ + + regval |= RCC_APB1ENR_DACEN; +#endif + +#ifdef CONFIG_STM32F7_UART7 + /* UART7 clock enable */ + + regval |= RCC_APB1ENR_UART7EN; +#endif + +#ifdef CONFIG_STM32F7_UART8 + /* UART8 clock enable */ + + regval |= RCC_APB1ENR_UART8EN; +#endif + + putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32_RCC_APB2ENR); + +#ifdef CONFIG_STM32F7_TIM1 + /* TIM1 clock enable */ + + regval |= RCC_APB2ENR_TIM1EN; +#endif + +#ifdef CONFIG_STM32F7_TIM8 + /* TIM8 clock enable */ + + regval |= RCC_APB2ENR_TIM8EN; +#endif + +#ifdef CONFIG_STM32F7_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32F7_USART6 + /* USART6 clock enable */ + + regval |= RCC_APB2ENR_USART6EN; +#endif + +#ifdef CONFIG_STM32F7_ADC1 + /* ADC1 clock enable */ + + regval |= RCC_APB2ENR_ADC1EN; +#endif + +#ifdef CONFIG_STM32F7_ADC2 + /* ADC2 clock enable */ + + regval |= RCC_APB2ENR_ADC2EN; +#endif + +#ifdef CONFIG_STM32F7_ADC3 + /* ADC3 clock enable */ + + regval |= RCC_APB2ENR_ADC3EN; +#endif + +#ifdef CONFIG_STM32F7_SDMMC1 + /* SDIO clock enable */ + + regval |= RCC_APB2ENR_SDMMC1EN; +#endif + +#ifdef CONFIG_STM32F7_SPI1 + /* SPI1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32F7_SPI4 + /* SPI4 clock enable */ + + regval |= RCC_APB2ENR_SPI4EN; +#endif + + /* System configuration controller clock enable */ + + regval |= RCC_APB2ENR_SYSCFGEN; + +#ifdef CONFIG_STM32F7_TIM9 + /* TIM9 clock enable */ + + regval |= RCC_APB2ENR_TIM9EN; +#endif + +#ifdef CONFIG_STM32F7_TIM10 + /* TIM10 clock enable */ + + regval |= RCC_APB2ENR_TIM10EN; +#endif + +#ifdef CONFIG_STM32F7_TIM11 + /* TIM11 clock enable */ + + regval |= RCC_APB2ENR_TIM11EN; +#endif + +#ifdef CONFIG_STM32F7_SPI5 + /* SPI5 clock enable */ + + regval |= RCC_APB2ENR_SPI5EN; +#endif + +#ifdef CONFIG_STM32F7_SPI6 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SPI6EN; +#endif + +#ifdef CONFIG_STM32F7_SAI1 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SAI1EN; +#endif + +#ifdef CONFIG_STM32F7_SAI2 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SAI2EN; +#endif + +#ifdef CONFIG_STM32F7_LTDC + /* LTDC clock enable */ + + regval |= RCC_APB2ENR_LTDCEN; +#endif + + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) +{ + uint32_t regval; + volatile int32_t timeout; + +#ifdef STM32_BOARD_USEHSI + /* Enable Internal High-Speed Clock (HSI) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSION; /* Enable HSI */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSI is ready (or until a timeout elapsed) */ + + for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSIRDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + +#else /* if STM32_BOARD_USEHSE */ + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } +#endif + + /* Check for a timeout. If this timeout occurs, then we are hosed. We + * have no real back-up plan, although the following logic makes it look + * as though we do. + */ + + if (timeout > 0) + { + /* Select regulator voltage output Scale 1 mode to support system + * frequencies up to 216 MHz. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + regval |= RCC_APB1ENR_PWREN; + putreg32(regval, STM32_RCC_APB1ENR); + + regval = getreg32(STM32_PWR_CR1); + regval &= ~PWR_CR1_VOS_MASK; + regval |= PWR_CR1_VOS_SCALE_1; + putreg32(regval, STM32_PWR_CR1); + + /* Set the HCLK source/divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_HPRE_MASK; + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK2 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE2_MASK; + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK1 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); + +#ifdef CONFIG_RTC_HSECLOCK + /* Set the RTC clock divisor */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_RTCPRE_MASK; + regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); + putreg32(regval, STM32_RCC_CFGR); +#endif + + /* Set the PLL dividers and multipliers to configure the main PLL */ + +#ifdef STM32_BOARD_USEHSI + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | + RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ); +#else /* if STM32_BOARD_USEHSE */ + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | + RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ); +#endif + putreg32(regval, STM32_RCC_PLLCFG); + + /* Enable the main PLL */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLL is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) + { + } + + /* Enable the Over-drive to extend the clock frequency to 216 Mhz */ + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0) + { + } + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODSWEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0) + { + } + + /* Configure FLASH wait states */ + + regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); + +#ifdef CONFIG_STM32F7_FLASH_PREFETCH + /* Enable FLASH prefetch */ + + regval |= FLASH_ACR_PRFTEN; +#endif + +#ifdef CONFIG_ARMV7M_ITCM + /* The Flash memory interface accelerates code execution with a system of + * instruction prefetch and cache lines on ITCM interface (ART + * Accelerator™). + */ + + regval |= FLASH_ACR_ARTEN; +#endif + + putreg32(regval, STM32_FLASH_ACR); + + /* Select the main PLL as system clock source */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= RCC_CFGR_SW_PLL; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until the PLL source is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + { + } + +#ifdef CONFIG_STM32F7_LTDC + /* Configure PLLSAI */ + + regval = getreg32(STM32_RCC_PLLSAICFGR); + regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN + | STM32_RCC_PLLSAICFGR_PLLSAIR + | STM32_RCC_PLLSAICFGR_PLLSAIQ); + putreg32(regval, STM32_RCC_PLLSAICFGR); + + regval = getreg32(STM32_RCC_DCKCFGR); + regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; + putreg32(regval, STM32_RCC_DCKCFGR); + + /* Enable PLLSAI */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLSAION; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLSAI is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0) + { + } +#endif + +#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK) + /* Low speed internal clock source LSI */ + + stm32_rcc_enablelsi(); +#endif + +#if defined(CONFIG_RTC_LSECLOCK) + /* Low speed external clock source LSE + * + * TODO: There is another case where the LSE needs to + * be enabled: if the MCO1 pin selects LSE as source. + */ + + stm32_rcc_enablelse(); +#endif + } +} +#endif + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableahb1(); + rcc_enableahb2(); + rcc_enableahb3(); + rcc_enableapb1(); + rcc_enableapb2(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/