Add GPIO dump logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2107 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
86ce2c9491
commit
dabc8f51e5
3 changed files with 62 additions and 27 deletions
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@ -47,12 +47,13 @@
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#include "stm32_internal.h"
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/****************************************************************************
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* Definitions
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@ -82,6 +83,10 @@ static const uint32 g_gpiobase[STM32_NGPIO] =
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#endif
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};
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#ifdef CONFIG_DEBUG
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static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -100,11 +105,11 @@ static const uint32 g_gpiobase[STM32_NGPIO] =
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int stm32_configgpio(uint32 cfgset)
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{
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uint32 gpiobase;
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uint32 base;
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uint32 cr;
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uint32 regval;
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uint32 regaddr;
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unsigned int gpio;
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unsigned int port;
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unsigned int pin;
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unsigned int pos;
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unsigned int modecnf;
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@ -112,24 +117,24 @@ int stm32_configgpio(uint32 cfgset)
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/* Verify that this hardware supports the select GPIO port */
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gpio = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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if (gpio < STM32_NGPIO)
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port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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if (port < STM32_NGPIO)
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{
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/* Get the port base address */
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gpiobase = g_gpiobase[gpio];
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base = g_gpiobase[port];
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/* Get the pin number and select the port configuration register for that pin */
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pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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if (pin < 8)
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{
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cr = gpiobase + STM32_GPIO_CRL_OFFSET;
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cr = base + STM32_GPIO_CRL_OFFSET;
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pos = pin;
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}
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else
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{
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cr = gpiobase + STM32_GPIO_CRH_OFFSET;
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cr = base + STM32_GPIO_CRH_OFFSET;
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pos = pin - 8;
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}
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@ -169,13 +174,13 @@ int stm32_configgpio(uint32 cfgset)
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{
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/* Use the BSRR register to set the output */
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regaddr = gpiobase + STM32_GPIO_BSRR_OFFSET;
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regaddr = base + STM32_GPIO_BSRR_OFFSET;
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}
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else
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{
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/* Use the BRR register to clear */
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regaddr = gpiobase + STM32_GPIO_BRR_OFFSET;
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regaddr = base + STM32_GPIO_BRR_OFFSET;
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}
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}
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else
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@ -189,13 +194,13 @@ int stm32_configgpio(uint32 cfgset)
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{
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/* Set the ODR bit (using BSRR) to one for the PULL-UP functionality */
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regaddr = gpiobase + STM32_GPIO_BSRR_OFFSET;
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regaddr = base + STM32_GPIO_BSRR_OFFSET;
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}
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else if ((cfgset & GPIO_MODE_MASK) == GPIO_CNF_INPULLDWN)
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{
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/* Clear the ODR bit (using BRR) to zero for the PULL-DOWN functionality */
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regaddr = gpiobase + STM32_GPIO_BRR_OFFSET;
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regaddr = base + STM32_GPIO_BRR_OFFSET;
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}
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else
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{
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@ -223,17 +228,17 @@ int stm32_configgpio(uint32 cfgset)
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void stm32_gpiowrite(uint32 pinset, boolean value)
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{
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uint32 gpiobase;
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uint32 base;
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uint32 offset;
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unsigned int gpio;
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unsigned int port;
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unsigned int pin;
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gpio = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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if (gpio < STM32_NGPIO)
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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if (port < STM32_NGPIO)
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{
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/* Get the port base address */
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gpiobase = g_gpiobase[gpio];
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base = g_gpiobase[port];
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/* Get the pin number */
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@ -249,7 +254,7 @@ void stm32_gpiowrite(uint32 pinset, boolean value)
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offset = STM32_GPIO_BRR_OFFSET;
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{
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}
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putreg32((1 << pin), gpiobase + offset);
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putreg32((1 << pin), base + offset);
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}
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}
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@ -263,21 +268,21 @@ void stm32_gpiowrite(uint32 pinset, boolean value)
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boolean stm32_gpioread(uint32 pinset)
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{
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uint32 gpiobase;
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unsigned int gpio;
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uint32 base;
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unsigned int port;
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unsigned int pin;
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gpio = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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if (gpio < STM32_NGPIO)
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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if (port < STM32_NGPIO)
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{
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/* Get the port base address */
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gpiobase = g_gpiobase[gpio];
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base = g_gpiobase[port];
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/* Get the pin number and return the input state of that pin */
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pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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return ((getreg32(gpiobase + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
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return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
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}
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return 0;
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}
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@ -290,9 +295,35 @@ boolean stm32_gpioread(uint32 pinset)
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*
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****************************************************************************/
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#if 0 /* Not implemented */
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#ifdef CONFIG_DEBUG
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int stm32_dumpgpio(uint32 pinset, const char *msg)
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{
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irqstate_t flags;
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uint32 base;
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unsigned int port;
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unsigned int pin;
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/* Get the base address associated with the GPIO port */
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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base = g_gpiobase[port];
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/* The following requires exclusive access to the GPIO registers */
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flags = irqsave();
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lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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lldbg(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
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getreg32(base + STM32_GPIO_CRH_OFFSET), getreg32(base + STM32_GPIO_CRL_OFFSET),
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getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET),
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getreg32(base + STM32_GPIO_LCKR_OFFSET));
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lldbg(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
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getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
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getreg32(STM32_AFIO_EXTICR1), getreg32(STM32_AFIO_EXTICR2),
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getreg32(STM32_AFIO_EXTICR3), getreg32(STM32_AFIO_EXTICR4));
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irqrestore(flags);
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return OK;
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}
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#endif
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@ -151,7 +151,7 @@
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#define GPIO_CR_MODE_SHIFT(n) ((n) << 2)
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#define GPIO_CR_MODE_MASK(n) (3 << GPIO_CR_MODE_SHIFT(n))
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#define GPIO_CR_CNF_SHIFT(n) (2 + ((n) << 2))
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#define GPIO_CR_CNF_MASK(n) (3 << GPIO_CRL_CNF_SHIFT(n))
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#define GPIO_CR_CNF_MASK(n) (3 << GPIO_CR_CNF_SHIFT(n))
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#define GPIO_CR_MODECNF_SHIFT(n) ((n) << 2)
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#define GPIO_CR_MODECNF_MASK(n) (0x0f << GPIO_CR_MODECNF_SHIFT(n))
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@ -208,7 +208,11 @@ EXTERN boolean stm32_gpioread(uint32 pinset);
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG
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EXTERN int stm32_dumpgpio(uint32 pinset, const char *msg);
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#else
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# define stm32_dumpgpio(p,m)
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#endif
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/****************************************************************************
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* Name: gpio_irqinitialize
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