Merge branch 'master' of bitbucket.org:nuttx/arch
This commit is contained in:
Gregory Nutt
commit
db61cdefe7
36 changed files with 1654 additions and 8159 deletions
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@ -2328,7 +2328,7 @@
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 4 /* SPI1-4 */
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# define STM32_NSPI 6 /* SPI1-6 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
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# define STM32_NI2C 3 /* I2C1-3 */
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@ -2345,6 +2345,60 @@
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F469A) || \
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defined(CONFIG_ARCH_CHIP_STM32F469I) || \
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defined(CONFIG_ARCH_CHIP_STM32F469B) || \
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defined(CONFIG_ARCH_CHIP_STM32F469N)
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# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
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# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 6 /* SPI1-6 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 1 /* No LCD */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# if defined(CONFIG_ARCH_CHIP_STM32F469A)
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# define STM32_NGPIO 114 /* GPIOA-I */
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# elif defined(CONFIG_ARCH_CHIP_STM32F469I)
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# define STM32_NGPIO 131 /* GPIOA-I */
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# elif defined(CONFIG_ARCH_CHIP_STM32F469B) || \
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defined(CONFIG_ARCH_CHIP_STM32F469N)
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# define STM32_NGPIO 161 /* GPIOA-K */
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# endif
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# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# if defined(CONFIG_ARCH_CHIP_STM32F469A)
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \
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# defined(CONFIG_ARCH_CHIP_STM32F469B) || \
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defined(CONFIG_ARCH_CHIP_STM32F469N)
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# endif
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#else
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# error "Unsupported STM32 chip"
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#endif
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@ -87,10 +87,6 @@
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# include <arch/stm32/stm32f30xxx_irq.h>
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#elif defined(CONFIG_STM32_STM32F37XX)
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# include <arch/stm32/stm32f37xxx_irq.h>
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#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
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# include <arch/stm32/stm32f42xxx_irq.h>
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#elif defined(CONFIG_STM32_STM32F446)
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# include <arch/stm32/stm32f44xxx_irq.h>
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#elif defined(CONFIG_STM32_STM32F40XX)
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# include <arch/stm32/stm32f40xxx_irq.h>
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#else
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@ -1,8 +1,11 @@
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/****************************************************************************************************
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* arch/arm/include/stm32s/stm32f40xxx_irq.h
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*
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* Copyright (C) 2009, 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2014-2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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* Paul Alexander Patience <paul-a.patience@polymtl.ca>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -61,100 +64,171 @@
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* External interrupts (vectors >= 16)
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
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#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
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#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
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#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
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#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
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#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
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#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
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#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
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#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
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#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
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#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
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#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
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#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
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#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
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#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
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#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
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#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
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#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
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#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
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#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
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#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
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#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
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#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
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#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
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#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
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#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
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#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
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#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
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#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
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#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
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#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
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#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
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#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
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#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
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#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
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#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
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#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
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#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
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#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
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#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
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#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
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#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
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#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
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#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
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#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
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#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
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#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
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#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
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#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
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#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
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#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
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#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
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#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
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#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
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#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
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#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
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#define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
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#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
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#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
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#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
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#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
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#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
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#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
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#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
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#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
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#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
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#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
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#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
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#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
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#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
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#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
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#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
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#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
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#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
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#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
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#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
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#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
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#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
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#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
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#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
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#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
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#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
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#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
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#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
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#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
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#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
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#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
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#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
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#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
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#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
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#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
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#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
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#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
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#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
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#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
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#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
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#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
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#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
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#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
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#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
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#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
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#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
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#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
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#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
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#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
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#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
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#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
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#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
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#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
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#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
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#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
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#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
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#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
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#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
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#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
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#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
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#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
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#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
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#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
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#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
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#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
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#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
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#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
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#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
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#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
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#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
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#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
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#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
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#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
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#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
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#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
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#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
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#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
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#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
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#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
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#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
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#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
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#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
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#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
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#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
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#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
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#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
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#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_IRQ_RESERVED61 (STM32_IRQ_FIRST+61) /* 61: Reserved */
|
||||
# define STM32_IRQ_RESERVED62 (STM32_IRQ_FIRST+62) /* 62: Reserved */
|
||||
#else
|
||||
# define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
|
||||
# define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
|
||||
#endif
|
||||
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
|
||||
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
|
||||
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */
|
||||
# define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */
|
||||
#else
|
||||
# define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
|
||||
# define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||
# define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||
#endif
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 interrupt */
|
||||
# define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 interrupt */
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_IRQ_RESERVED82 (STM32_IRQ_FIRST+82) /* 82: Reserved */
|
||||
# define STM32_IRQ_RESERVED83 (STM32_IRQ_FIRST+83) /* 83: Reserved */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */
|
||||
# define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 interrupt */
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_IRQ_RESERVED85 (STM32_IRQ_FIRST+85) /* 85: Reserved */
|
||||
# define STM32_IRQ_RESERVED86 (STM32_IRQ_FIRST+86) /* 86: Reserved */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469)
|
||||
# define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LTDCINT interrupt */
|
||||
# define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LTDCERRINT interrupt */
|
||||
# define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D interrupt */
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_IRQ_RESERVED88 (STM32_IRQ_FIRST+88) /* 88: Reserved */
|
||||
# define STM32_IRQ_RESERVED89 (STM32_IRQ_FIRST+89) /* 89: Reserved */
|
||||
# define STM32_IRQ_RESERVED90 (STM32_IRQ_FIRST+90) /* 90: Reserved */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */
|
||||
# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */
|
||||
#elif defined(CONFIG_STM32_STM32F469)
|
||||
# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+91) /* 92: QuadSPI Global interrupt */
|
||||
# define STM32_IRQ_DSI (STM32_IRQ_FIRST+92) /* 91: DSI Global interrupt */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+93) /* 93: HDMI-CEC Global interrupt */
|
||||
# define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+94) /* 94: SPDIF-Rx Global interrupt */
|
||||
# define STM32_IRQ_FMPI2C1 (STM32_IRQ_FIRST+95) /* 95: FMPI2C1 event interrupt */
|
||||
# define STM32_IRQ_FMPI2C1ERR (STM32_IRQ_FIRST+96) /* 96: FMPI2C1 Error event interrupt */
|
||||
#endif
|
||||
|
||||
#define NR_VECTORS (STM32_IRQ_FIRST+82)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST+82)
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407)
|
||||
# define NR_VECTORS (STM32_IRQ_FIRST+82)
|
||||
# define NR_IRQS (STM32_IRQ_FIRST+82)
|
||||
#elif defined(CONFIG_STM32_STM32F427)
|
||||
# define NR_VECTORS (STM32_IRQ_FIRST+87)
|
||||
# define NR_IRQS (STM32_IRQ_FIRST+87)
|
||||
#elif defined(CONFIG_STM32_STM32F429)
|
||||
# define NR_VECTORS (STM32_IRQ_FIRST+91)
|
||||
# define NR_IRQS (STM32_IRQ_FIRST+91)
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# define NR_VECTORS (STM32_IRQ_FIRST+97)
|
||||
# define NR_IRQS (STM32_IRQ_FIRST+97)
|
||||
#elif defined(CONFIG_STM32_STM32F469)
|
||||
# define NR_VECTORS (STM32_IRQ_FIRST+93)
|
||||
# define NR_IRQS (STM32_IRQ_FIRST+93)
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
|
|
@ -184,4 +258,3 @@ extern "C"
|
|||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,208 +0,0 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/include/stm32s/stm32f42xxx_irq.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather,
|
||||
* only indirectly through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
|
||||
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
|
||||
* to handle mapping tables.
|
||||
*
|
||||
* Processor Exceptions (vectors 0-15). These common definitions can be found
|
||||
* in nuttx/arch/arm/include/stm32/irq.h
|
||||
*
|
||||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
|
||||
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
|
||||
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
|
||||
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
|
||||
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
|
||||
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
|
||||
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
|
||||
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 interrupt */
|
||||
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 interrupt */
|
||||
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */
|
||||
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */
|
||||
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 interrupt */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
|
||||
# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */
|
||||
# define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LTDCINT interrupt */
|
||||
# define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LTDCERRINT interrupt */
|
||||
# define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D interrupt */
|
||||
|
||||
# define NR_VECTORS (STM32_IRQ_FIRST+91)
|
||||
# define NR_IRQS (STM32_IRQ_FIRST+91)
|
||||
|
||||
#else /* if defined(CONFIG_STM32_STM32F427) */
|
||||
|
||||
# define NR_VECTORS (STM32_IRQ_FIRST+87)
|
||||
# define NR_IRQS (STM32_IRQ_FIRST+87)
|
||||
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F427 || CONFIG_STM32_STM32F429 */
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H */
|
||||
|
|
@ -1,205 +0,0 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/include/stm32s/stm32f44xxx_irq.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather,
|
||||
* only indirectly through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32F44XXX_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32F44XXX_IRQ_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
|
||||
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
|
||||
* to handle mapping tables.
|
||||
*
|
||||
* Processor Exceptions (vectors 0-15). These common definitions can be found
|
||||
* in nuttx/arch/arm/include/stm32/irq.h
|
||||
*
|
||||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
|
||||
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
|
||||
#define STM32_IRQ_RES01 (STM32_IRQ_FIRST+61) /* 61: 1st Reserved (Ethernet global) interrupt */
|
||||
#define STM32_IRQ_RES02 (STM32_IRQ_FIRST+62) /* 62: 2nd Reserved (Ethernet Wakeup through EXTI line) interrupt */
|
||||
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
|
||||
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
|
||||
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
|
||||
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
|
||||
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
|
||||
#define STM32_IRQ_RES03 (STM32_IRQ_FIRST+79) /* 79: 3rd Reserved (CRYP crypto global) interrupt */
|
||||
#define STM32_IRQ_RES04 (STM32_IRQ_FIRST+80) /* 80: 4th Reserved (Hash and Rng global) interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_RES05 (STM32_IRQ_FIRST+82) /* 82: 5th Reserved (UART7)interrupt */
|
||||
#define STM32_IRQ_RES06 (STM32_IRQ_FIRST+83) /* 83: 6th Reserved (UART8) interrupt */
|
||||
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */
|
||||
#define STM32_IRQ_RES07 (STM32_IRQ_FIRST+85) /* 85: 7th Reserved (SPI5) interrupt */
|
||||
#define STM32_IRQ_RES08 (STM32_IRQ_FIRST+86) /* 86: 8th Reserved (SPI6) interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */
|
||||
#define STM32_IRQ_RES09 (STM32_IRQ_FIRST+88) /* 88: 9th Reserved (LTDCINT interrupt */
|
||||
#define STM32_IRQ_RES10 (STM32_IRQ_FIRST+89) /* 89: 10th Reserved (LTDCERRINT) interrupt */
|
||||
#define STM32_IRQ_RES11 (STM32_IRQ_FIRST+90) /* 90: 11th Reserved (DMA2D) interrupt */
|
||||
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */
|
||||
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+93) /* 93: HDMI-CEC Global interrupt */
|
||||
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+94) /* 94: SPDIF-Rx Global interrupt */
|
||||
#define STM32_IRQ_FMPI2C1 (STM32_IRQ_FIRST+95) /* 95: FMPI2C1 event interrupt */
|
||||
#define STM32_IRQ_FMPI2C1ERR (STM32_IRQ_FIRST+96) /* 96: FMPI2C1 Error event interrupt */
|
||||
|
||||
#define NR_VECTORS (STM32_IRQ_FIRST+97)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST+97)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F446 */
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32F44XXX_IRQ_H */
|
||||
|
|
@ -1004,8 +1004,6 @@ config ARCH_CHIP_STM32F446M
|
|||
select STM32_STM32F40XX
|
||||
select STM32_STM32F446
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32_HAVE_SAIPLL
|
||||
select STM32_HAVE_I2SPLL
|
||||
|
||||
config ARCH_CHIP_STM32F446R
|
||||
bool "STM32F446R"
|
||||
|
|
@ -1013,8 +1011,6 @@ config ARCH_CHIP_STM32F446R
|
|||
select STM32_STM32F40XX
|
||||
select STM32_STM32F446
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32_HAVE_SAIPLL
|
||||
select STM32_HAVE_I2SPLL
|
||||
|
||||
config ARCH_CHIP_STM32F446V
|
||||
bool "STM32F446V"
|
||||
|
|
@ -1022,8 +1018,6 @@ config ARCH_CHIP_STM32F446V
|
|||
select STM32_STM32F40XX
|
||||
select STM32_STM32F446
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32_HAVE_SAIPLL
|
||||
select STM32_HAVE_I2SPLL
|
||||
|
||||
config ARCH_CHIP_STM32F446Z
|
||||
bool "STM32F446Z"
|
||||
|
|
@ -1031,8 +1025,37 @@ config ARCH_CHIP_STM32F446Z
|
|||
select STM32_STM32F40XX
|
||||
select STM32_STM32F446
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32_HAVE_SAIPLL
|
||||
select STM32_HAVE_I2SPLL
|
||||
|
||||
config ARCH_CHIP_STM32F469A
|
||||
bool "STM32F469A"
|
||||
select ARCH_CORTEXM4
|
||||
select STM32_STM32F40XX
|
||||
select STM32_STM32F469
|
||||
select ARCH_HAVE_FPU
|
||||
|
||||
config ARCH_CHIP_STM32F469I
|
||||
bool "STM32F469I"
|
||||
select ARCH_CORTEXM4
|
||||
select STM32_STM32F40XX
|
||||
select STM32_STM32F469
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32_HAVE_ETHMAC
|
||||
|
||||
config ARCH_CHIP_STM32F469B
|
||||
bool "STM32F469B"
|
||||
select ARCH_CORTEXM4
|
||||
select STM32_STM32F40XX
|
||||
select STM32_STM32F469
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32_HAVE_ETHMAC
|
||||
|
||||
config ARCH_CHIP_STM32F469N
|
||||
bool "STM32F469N"
|
||||
select ARCH_CORTEXM4
|
||||
select STM32_STM32F40XX
|
||||
select STM32_STM32F469
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32_HAVE_ETHMAC
|
||||
|
||||
endchoice
|
||||
|
||||
|
|
@ -1493,6 +1516,7 @@ config STM32_STM32F429
|
|||
bool
|
||||
default n
|
||||
select STM32_HAVE_FSMC
|
||||
select STM32_HAVE_LTDC
|
||||
select STM32_HAVE_CCM
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_UART4
|
||||
|
|
@ -1546,6 +1570,42 @@ config STM32_STM32F446
|
|||
select STM32_HAVE_DAC1
|
||||
select STM32_HAVE_DAC2
|
||||
select STM32_HAVE_SPI4
|
||||
select STM32_HAVE_SAIPLL
|
||||
select STM32_HAVE_I2SPLL
|
||||
|
||||
# This is really 469/479, but we treat the two the same.
|
||||
config STM32_STM32F469
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_FSMC
|
||||
select STM32_HAVE_LTDC
|
||||
select STM32_HAVE_CCM
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_UART4
|
||||
select STM32_HAVE_UART5
|
||||
select STM32_HAVE_USART6
|
||||
select STM32_HAVE_UART7
|
||||
select STM32_HAVE_UART8
|
||||
select STM32_HAVE_TIM1
|
||||
select STM32_HAVE_TIM6
|
||||
select STM32_HAVE_TIM7
|
||||
select STM32_HAVE_TIM8
|
||||
select STM32_HAVE_TIM9
|
||||
select STM32_HAVE_TIM10
|
||||
select STM32_HAVE_TIM11
|
||||
select STM32_HAVE_TIM12
|
||||
select STM32_HAVE_TIM13
|
||||
select STM32_HAVE_TIM14
|
||||
select STM32_HAVE_ADC2
|
||||
select STM32_HAVE_ADC3
|
||||
select STM32_HAVE_CAN1
|
||||
select STM32_HAVE_CAN2
|
||||
select STM32_HAVE_DAC1
|
||||
select STM32_HAVE_DAC2
|
||||
select STM32_HAVE_RNG
|
||||
select STM32_HAVE_SPI4
|
||||
select STM32_HAVE_SPI5
|
||||
select STM32_HAVE_SPI6
|
||||
|
||||
config STM32_DFU
|
||||
bool "DFU bootloader"
|
||||
|
|
@ -1576,6 +1636,10 @@ config STM32_HAVE_FSMC
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_LTDC
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_USART3
|
||||
bool
|
||||
default n
|
||||
|
|
@ -1906,7 +1970,7 @@ config STM32_I2C3
|
|||
config STM32_LTDC
|
||||
bool "LTDC"
|
||||
default n
|
||||
depends on STM32_STM32F429
|
||||
depends on STM32_HAVE_LTDC
|
||||
---help---
|
||||
The STM32 LTDC is an LCD-TFT Display Controller available on
|
||||
the STM32F429 and STM32F439 devices. It is a standard parallel
|
||||
|
|
|
|||
|
|
@ -129,10 +129,6 @@
|
|||
|
||||
/* STM32 F4 Family ******************************************************************/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_pinmap.h"
|
||||
#else
|
||||
|
|
@ -154,10 +150,6 @@
|
|||
# include "chip/stm32f30xxx_vectors.h"
|
||||
# elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f37xxx_vectors.h"
|
||||
# elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_vectors.h"
|
||||
# elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_vectors.h"
|
||||
# elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_vectors.h"
|
||||
# else
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@
|
|||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
# define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */
|
||||
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446)
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define PWR_CR_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */
|
||||
# define PWR_CR_VOS_MASK (3 << 14) /* Bits 14-15: Regulator voltage scaling output selection */
|
||||
# define PWR_CR_VOS_SCALE_1 (3 << 14) /* Fmax = 168MHz */
|
||||
|
|
@ -115,7 +115,8 @@
|
|||
# define PWR_CR_LPRUN (1 << 14) /* Low power run mode */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define PWR_CR_ODEN (1 << 16) /* Over Drive enable */
|
||||
# define PWR_CR_ODSWEN (1 << 17) /* Over Drive switch enabled */
|
||||
#endif
|
||||
|
|
@ -155,7 +156,8 @@
|
|||
# define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define PWR_CSR_ODRDY (1 << 16) /* Over Drive generator ready */
|
||||
# define PWR_CSR_ODSWRDY (1 << 17) /* Over Drive Switch ready */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ VECTOR(stm32_i2c3er, STM32_IRQ_I2C3ER) /* Vector 16+73: I2C3 error int
|
|||
VECTOR(stm32_otghsep1out, STM32_IRQ_OTGHSEP1OUT) /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
VECTOR(stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN) /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */
|
||||
VECTOR(stm32_otghswkup, STM32_IRQ_OTGHSWKUP) /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
VECTOR(stm32_otghs, STM32_IRQ_OTGHS ) /* Vector 16+77: USB On The Go HS global interrupt */
|
||||
VECTOR(stm32_otghs, STM32_IRQ_OTGHS) /* Vector 16+77: USB On The Go HS global interrupt */
|
||||
VECTOR(stm32_dcmi, STM32_IRQ_DCMI) /* Vector 16+78: DCMI global interrupt */
|
||||
VECTOR(stm32_cryp, STM32_IRQ_CRYP) /* Vector 16+79: CRYP crypto global interrupt */
|
||||
VECTOR(stm32_hash, STM32_IRQ_HASH) /* Vector 16+80: Hash and Rng global interrupt */
|
||||
|
|
|
|||
|
|
@ -2,7 +2,9 @@
|
|||
* arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015-2016 Omni Hoverboards Inc. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -75,6 +77,11 @@
|
|||
#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
|
||||
|
|
@ -84,22 +91,27 @@
|
|||
#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC2_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC2_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC2_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC2_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC2_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
|
||||
|
||||
#define GPIO_ADC12_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC12_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC12_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC12_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN2)
|
||||
|
||||
#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN10)
|
||||
|
|
@ -111,16 +123,15 @@
|
|||
#define GPIO_ADC4_IN3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ADC4_IN4 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_ADC4_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_ADC4_IN6 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_ADC4_IN7 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_ADC4_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_ADC4_IN9 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_ADC4_IN10 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_ADC4_IN11 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_ADC4_IN12 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_ADC4_IN13 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9)
|
||||
|
||||
#define GPIO_ADC34_IN6 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_ADC34_IN7 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_ADC34_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_ADC34_IN9 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_ADC34_IN10 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_ADC34_IN11 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
|
||||
|
||||
/* CAN */
|
||||
|
||||
#define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
|
||||
|
|
|
|||
|
|
@ -1,8 +1,11 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f40xxx_dma.h
|
||||
*
|
||||
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -438,11 +441,24 @@
|
|||
#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4)
|
||||
#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define DMAMAP_UART8_TX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN5)
|
||||
# define DMAMAP_UART7_TX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN5)
|
||||
#endif
|
||||
#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define DMAMAP_UART7_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN5)
|
||||
#endif
|
||||
#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define DMAMAP_UART8_RX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN5)
|
||||
#endif
|
||||
#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5)
|
||||
|
||||
#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6)
|
||||
|
|
@ -475,10 +491,20 @@
|
|||
#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1)
|
||||
#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1)
|
||||
#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define DMAMAP_SPI6_TX STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN1)
|
||||
# define DMAMAP_SPI6_RX STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN1)
|
||||
#endif
|
||||
#define DMAMAP_DCMI_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN1)
|
||||
|
||||
#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2)
|
||||
#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define DMAMAP_SPI5_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN2)
|
||||
# define DMAMAP_SPI5_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN2)
|
||||
#endif
|
||||
#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2)
|
||||
#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2)
|
||||
#define DMAMAP_HASH_IN STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN2)
|
||||
|
|
@ -488,7 +514,11 @@
|
|||
#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3)
|
||||
|
||||
#define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4)
|
||||
# define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4)
|
||||
#endif
|
||||
#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4)
|
||||
#define DMAMAP_SDIO_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4)
|
||||
|
|
@ -497,6 +527,11 @@
|
|||
|
||||
#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5)
|
||||
# define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5)
|
||||
#endif
|
||||
#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5)
|
||||
|
||||
|
|
@ -514,6 +549,11 @@
|
|||
#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define DMAMAP_SPI5_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7)
|
||||
# define DMAMAP_SPI5_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN7)
|
||||
#endif
|
||||
#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
|
|
|
|||
|
|
@ -1,8 +1,11 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -54,12 +57,12 @@
|
|||
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if
|
||||
* CAN1_RX connects vis PA11 on some board, then the following definitions should
|
||||
* appear inthe board.h header file for that board:
|
||||
* CAN1_RX connects via PA11 on some board, then the following definitions should
|
||||
* appear in the board.h header file for that board:
|
||||
*
|
||||
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
*
|
||||
* The driver will then automatically configre PA11 as the CAN1 RX pin.
|
||||
* The driver will then automatically configure PA11 as the CAN1 RX pin.
|
||||
*/
|
||||
|
||||
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
|
||||
|
|
@ -112,6 +115,7 @@
|
|||
#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
|
|
@ -136,14 +140,14 @@
|
|||
#define GPIO_CAN2_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_CAN2_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
|
||||
|
||||
/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
|
||||
/* DAC - "Once the DAC channelx is enabled, the corresponding GPIO pin
|
||||
* (PA4 or PA5) is automatically connected to the analog converter output
|
||||
* (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin
|
||||
* should first be configured to analog (AIN)".
|
||||
*/
|
||||
|
||||
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
|
||||
/* Digital Camera Interface (DCMI) */
|
||||
|
||||
|
|
@ -178,15 +182,31 @@
|
|||
#define GPIO_DCMI_D10_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_DCMI_D11_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_DCMI_D11_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN15)
|
||||
#define GPIO_DCMI_D12 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_DCMI_D13_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_DCMI_D13_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_DCMI_HSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DCMI_HSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_DCMI_PIXCK (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_DCMI_PIXCLK (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_DCMI_VSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_DCMI_VSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN5)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_DCMI_D2_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN10)
|
||||
# define GPIO_DCMI_D3_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN11)
|
||||
# define GPIO_DCMI_D5_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN3)
|
||||
# define GPIO_DCMI_D8_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN6)
|
||||
# define GPIO_DCMI_D9_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN7)
|
||||
# define GPIO_DCMI_D10_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN6)
|
||||
# define GPIO_DCMI_D11_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN10)
|
||||
# define GPIO_DCMI_D12_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN11)
|
||||
# define GPIO_DCMI_D12_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN6)
|
||||
# define GPIO_DCMI_D13_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN7)
|
||||
# define GPIO_DCMI_VSYNC_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_DCMI_D12 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN11)
|
||||
#endif
|
||||
|
||||
/* Clocks outputs */
|
||||
|
||||
#define GPIO_MCO1 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
|
|
@ -194,45 +214,50 @@
|
|||
|
||||
/* Ethernet MAC */
|
||||
|
||||
#define GPIO_ETH_MDC (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ETH_MII_COL_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ETH_MII_COL_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3)
|
||||
#define GPIO_ETH_MII_CRS_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ETH_MII_CRS_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2)
|
||||
#define GPIO_ETH_MII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ETH_MII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ETH_MII_RXD2_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ETH_MII_RXD2_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_ETH_MII_RXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_ETH_MII_RXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_ETH_MII_RX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ETH_MII_RX_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ETH_MII_RX_ER_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_ETH_MII_RX_ER_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10)
|
||||
#define GPIO_ETH_MII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_MII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_ETH_MII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_MII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_ETH_MII_TXD2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ETH_MII_TXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_ETH_MII_TXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_ETH_MII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ETH_MII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_RMII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_ETH_RMII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_RMII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_ETH_RMII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ETH_RMII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_ETH_RMII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_ETH_MDC (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1)
|
||||
# define GPIO_ETH_MDIO (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_ETH_MII_COL_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_ETH_MII_COL_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3)
|
||||
# define GPIO_ETH_MII_CRS_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_ETH_MII_CRS_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2)
|
||||
# define GPIO_ETH_MII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
|
||||
# define GPIO_ETH_MII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
|
||||
# define GPIO_ETH_MII_RXD2_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_ETH_MII_RXD2_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
|
||||
# define GPIO_ETH_MII_RXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_ETH_MII_RXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN7)
|
||||
# define GPIO_ETH_MII_RX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_ETH_MII_RX_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_ETH_MII_RX_ER_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_ETH_MII_RX_ER_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10)
|
||||
# define GPIO_ETH_MII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_ETH_MII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13)
|
||||
# define GPIO_ETH_MII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_ETH_MII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
|
||||
# define GPIO_ETH_MII_TXD2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
|
||||
# define GPIO_ETH_MII_TXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_ETH_MII_TXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2)
|
||||
# define GPIO_ETH_MII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
|
||||
# define GPIO_ETH_MII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
|
||||
# define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
|
||||
# define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
|
||||
# define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
|
||||
# define GPIO_ETH_RMII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_ETH_RMII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13)
|
||||
# define GPIO_ETH_RMII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_ETH_RMII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
|
||||
# define GPIO_ETH_RMII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
|
||||
# define GPIO_ETH_RMII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_ETH_RMII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
|
||||
#endif
|
||||
|
||||
/* Flexible Static Memory Controller (FSMC) */
|
||||
|
||||
|
|
@ -263,7 +288,6 @@
|
|||
#define GPIO_FSMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_FSMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_FSMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_FSMC_CD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_FSMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_FSMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_FSMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
|
|
@ -281,26 +305,87 @@
|
|||
#define GPIO_FSMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_FSMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_FSMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_FSMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
|
||||
#define GPIO_FSMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_FSMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_FSMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_FSMC_NCE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FSMC_NCE4_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_FSMC_NCE4_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_FSMC_NE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FSMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_FSMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_FSMC_NIORD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_FSMC_NIOWR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_FSMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_FSMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
|
||||
#define GPIO_FSMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# define GPIO_FSMC_CD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
|
||||
# define GPIO_FSMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
|
||||
# define GPIO_FSMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
|
||||
# define GPIO_FSMC_NCE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
# define GPIO_FSMC_NCE4_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
# define GPIO_FSMC_NCE4_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN11)
|
||||
# define GPIO_FSMC_NIORD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
# define GPIO_FSMC_NIOWR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
# define GPIO_FSMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_FSMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
# define GPIO_FSMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
# define GPIO_FSMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
# define GPIO_FSMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
# define GPIO_FSMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_FSMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
|
||||
# define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
# define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
|
||||
# define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
|
||||
# define GPIO_FSMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
# define GPIO_FSMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_FSMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
|
||||
# define GPIO_FSMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
|
||||
# define GPIO_FSMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
|
||||
# define GPIO_FSMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
|
||||
# define GPIO_FSMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
|
||||
# define GPIO_FSMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
|
||||
# define GPIO_FSMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
|
||||
# define GPIO_FSMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
|
||||
# define GPIO_FSMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
|
||||
# define GPIO_FSMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
|
||||
# define GPIO_FSMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
|
||||
# define GPIO_FSMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
|
||||
# define GPIO_FSMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
|
||||
# define GPIO_FSMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
|
||||
# define GPIO_FSMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
|
||||
# define GPIO_FSMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
|
||||
# define GPIO_FSMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
|
||||
# define GPIO_FSMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
|
||||
# define GPIO_FSMC_SDCKE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
|
||||
# define GPIO_FSMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_FSMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
|
||||
# define GPIO_FSMC_SDNE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
|
||||
# define GPIO_FSMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_FSMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
|
||||
# define GPIO_FSMC_SDNWE_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_FSMC_SDCKE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_FSMC_SDNE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_FSMC_CLE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_FSMC_ALE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
|
||||
|
|
@ -318,6 +403,10 @@
|
|||
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_I2C2_SDA_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN12)
|
||||
#endif
|
||||
|
||||
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7)
|
||||
|
|
@ -325,20 +414,49 @@
|
|||
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
/* I2S */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_I2S1_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN5)
|
||||
# define GPIO_I2S1_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_I2S1_MCK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_I2S1_MCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN4)
|
||||
# define GPIO_I2S1_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_I2S1_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_I2S1_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_I2S1_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN15)
|
||||
#endif
|
||||
|
||||
#define GPIO_I2S2_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2S2_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_I2S2_CK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_I2S2_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_I2S2_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_I2S2_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_I2S2_SD_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_I2S2_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2S2_WS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2S2_WS_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2S2_WS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN0)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_I2S2_CK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3)
|
||||
# define GPIO_I2S2_SD_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN1)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_I2S2_CK_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_I2S2_CK_6 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_I2S2_MCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_I2S2_MCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_I2S2_WS_7 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_I2S2_WS_8 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_I2S2_MCK (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN6)
|
||||
#endif
|
||||
|
||||
#define GPIO_I2S2EXT_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_I2S2EXT_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN2)
|
||||
|
|
@ -351,9 +469,23 @@
|
|||
#define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_I2S3_WS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_I2S3_WS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_I2S3_SD_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN6)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_I2S3_SD_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_I2S3_SD_5 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN2)
|
||||
# define GPIO_I2S3_SD_6 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN1)
|
||||
# define GPIO_I2S3_SD_7 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN1)
|
||||
# define GPIO_I2S3_SD_8 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN0)
|
||||
# define GPIO_I2S3_SD_9 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_I2S3_SD_10 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN6)
|
||||
#else
|
||||
# define GPIO_I2S3EXT_SD_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
#define GPIO_I2S3EXT_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_I2S3EXT_SD_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4)
|
||||
|
||||
#define GPIO_I2S_CKIN (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN9)
|
||||
|
||||
|
|
@ -370,8 +502,6 @@
|
|||
#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTGFS_SCL (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_OTGFS_SDA (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
|
||||
#define GPIO_OTGHSFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
|
|
@ -381,10 +511,6 @@
|
|||
#define GPIO_OTGHS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_OTGHS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_OTGHS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTGHS_INTN_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_OTGFS_INTN_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_OTGHS_SCL (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_OTGHS_SDA (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
|
||||
|
||||
#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
|
||||
|
|
@ -392,7 +518,6 @@
|
|||
#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5)
|
||||
|
|
@ -402,23 +527,40 @@
|
|||
#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_OTGHS_ULPI_D4_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_OTGHS_ULPI_D4_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
|
||||
#else
|
||||
# define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
|
||||
#endif
|
||||
|
||||
/* RTC */
|
||||
|
||||
#define GPIO_RTC_50HZ (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN15)
|
||||
|
||||
/* SDIO */
|
||||
|
||||
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_SDIO_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_SDIO_D2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_SDIO_D3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SDIO_D4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SDIO_D5 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SDIO_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SDIO_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_SDIO_CK_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
|
||||
# define GPIO_SDIO_CK_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN2)
|
||||
# define GPIO_SDIO_D1_1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_SDIO_D1_2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_SDIO_D2_1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_SDIO_D2_2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_SDIO_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
|
||||
# define GPIO_SDIO_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_SDIO_D2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
#endif
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
|
|
@ -442,6 +584,19 @@
|
|||
#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN1)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_SPI2_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN1)
|
||||
# define GPIO_SPI2_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_SPI2_NSS_4 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI2_NSS_5 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
# define GPIO_SPI2_SCK_6 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11)
|
||||
|
|
@ -451,29 +606,48 @@
|
|||
#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_SPI3_MOSI_4 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_SPI3_MOSI_5 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN2)
|
||||
# define GPIO_SPI3_MOSI_6 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN1)
|
||||
# define GPIO_SPI3_MOSI_7 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#endif
|
||||
|
||||
#define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_SPI4_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_SPI4_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_SPI4_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_SPI4_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_SPI4_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
# define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
# define GPIO_SPI4_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_SPI4_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
# define GPIO_SPI4_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_SPI4_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
# define GPIO_SPI4_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_SPI4_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#endif
|
||||
|
||||
#define GPIO_SPI5_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_SPI5_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_SPI5_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_SPI5_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_SPI5_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_SPI5_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN5)
|
||||
#define GPIO_SPI5_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_SPI5_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN6)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_SPI5_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
# define GPIO_SPI5_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN7)
|
||||
# define GPIO_SPI5_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9)
|
||||
# define GPIO_SPI5_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
# define GPIO_SPI5_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
# define GPIO_SPI5_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN5)
|
||||
# define GPIO_SPI5_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
# define GPIO_SPI5_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN6)
|
||||
|
||||
#define GPIO_SPI6_MISO (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_SPI6_MOSI (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_SPI6_NSS (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_SPI6_SCK (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
# define GPIO_SPI6_MISO (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
# define GPIO_SPI6_MOSI (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
# define GPIO_SPI6_NSS (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN8)
|
||||
# define GPIO_SPI6_SCK (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
/* Timers */
|
||||
|
||||
|
|
@ -495,7 +669,7 @@
|
|||
#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13)
|
||||
|
|
@ -597,13 +771,13 @@
|
|||
#define GPIO_TIM8_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14)
|
||||
#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14)
|
||||
#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_TIM8_CH3N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15)
|
||||
|
|
@ -656,15 +830,48 @@
|
|||
#define GPIO_TIM14_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM14_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_TIM2_CH1IN_4 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM2_CH1OUT_4 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM2_CH2IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_TIM2_CH2OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_TIM2_CH4IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
|
||||
# define GPIO_TIM2_ETR_4 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
|
||||
#endif
|
||||
|
||||
/* Trace */
|
||||
|
||||
#define GPIO_TRACECLK (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_TRACED0 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TRACED1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TRACED2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TRACED3 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_TRACESWO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_TRACED0_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3)
|
||||
# define GPIO_TRACED1_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4)
|
||||
#else
|
||||
# define GPIO_TRACED0 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3)
|
||||
# define GPIO_TRACED1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_TRACED0_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TRACED1_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTD|GPIO_PIN3)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_TRACED0_3 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN1)
|
||||
# define GPIO_TRACED0_4 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN13)
|
||||
# define GPIO_TRACED1_3 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TRACED1_4 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN14)
|
||||
# define GPIO_TRACED2_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5)
|
||||
# define GPIO_TRACED2_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTD|GPIO_PIN2)
|
||||
# define GPIO_TRACED3_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6)
|
||||
# define GPIO_TRACED3_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN12)
|
||||
#else
|
||||
# define GPIO_TRACED2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5)
|
||||
# define GPIO_TRACED3 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6)
|
||||
#endif
|
||||
|
||||
/* UARTs/USARTs */
|
||||
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8)
|
||||
|
|
@ -696,15 +903,26 @@
|
|||
#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9)
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
|
||||
#endif
|
||||
#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_UART4_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_UART4_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
|
||||
#endif
|
||||
#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_UART5_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_UART5_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#endif
|
||||
#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12)
|
||||
|
||||
|
|
@ -719,4 +937,233 @@
|
|||
#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_UART7_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN7)
|
||||
# define GPIO_UART7_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
|
||||
# define GPIO_UART7_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8)
|
||||
# define GPIO_UART7_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
|
||||
|
||||
# define GPIO_UART8_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
|
||||
# define GPIO_UART8_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
|
||||
#endif
|
||||
|
||||
/* LCD-TFT Display Controller (LTDC) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_LTDC_R0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2)
|
||||
# define GPIO_LTDC_R0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN15)
|
||||
# define GPIO_LTDC_R1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3)
|
||||
# define GPIO_LTDC_R1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN0)
|
||||
# define GPIO_LTDC_R2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_LTDC_R2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN8)
|
||||
# define GPIO_LTDC_R2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN1)
|
||||
# define GPIO_LTDC_R3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_LTDC_R3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
|
||||
# define GPIO_LTDC_R3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN2)
|
||||
# define GPIO_LTDC_R4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_LTDC_R4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10)
|
||||
# define GPIO_LTDC_R4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN3)
|
||||
# define GPIO_LTDC_R5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_LTDC_R5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11)
|
||||
# define GPIO_LTDC_R5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN4)
|
||||
# define GPIO_LTDC_R6_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_LTDC_R6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12)
|
||||
# define GPIO_LTDC_R6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN5)
|
||||
# define GPIO_LTDC_R6_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_LTDC_R7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
|
||||
# define GPIO_LTDC_R7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN15)
|
||||
# define GPIO_LTDC_R7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN6)
|
||||
|
||||
# define GPIO_LTDC_G0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
|
||||
# define GPIO_LTDC_G0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN7)
|
||||
# define GPIO_LTDC_G1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
|
||||
# define GPIO_LTDC_G1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN8)
|
||||
# define GPIO_LTDC_G2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_LTDC_G2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
|
||||
# define GPIO_LTDC_G2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN9)
|
||||
# define GPIO_LTDC_G3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
|
||||
# define GPIO_LTDC_G3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14)
|
||||
# define GPIO_LTDC_G3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN10)
|
||||
# define GPIO_LTDC_G3_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_LTDC_G4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_LTDC_G4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN15)
|
||||
# define GPIO_LTDC_G4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN11)
|
||||
# define GPIO_LTDC_G5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_LTDC_G5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0)
|
||||
# define GPIO_LTDC_G5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN0)
|
||||
# define GPIO_LTDC_G6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_LTDC_G6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN1)
|
||||
# define GPIO_LTDC_G6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN1)
|
||||
# define GPIO_LTDC_G7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3)
|
||||
# define GPIO_LTDC_G7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2)
|
||||
# define GPIO_LTDC_G7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN2)
|
||||
|
||||
# define GPIO_LTDC_B0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4)
|
||||
# define GPIO_LTDC_B0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN12)
|
||||
# define GPIO_LTDC_B1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12)
|
||||
# define GPIO_LTDC_B1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN13)
|
||||
# define GPIO_LTDC_B2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
|
||||
# define GPIO_LTDC_B2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
|
||||
# define GPIO_LTDC_B2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN14)
|
||||
# define GPIO_LTDC_B3_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
|
||||
# define GPIO_LTDC_B3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_LTDC_B3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN15)
|
||||
# define GPIO_LTDC_B4_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12)
|
||||
# define GPIO_LTDC_B4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12)
|
||||
# define GPIO_LTDC_B4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN4)
|
||||
# define GPIO_LTDC_B4_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN3)
|
||||
# define GPIO_LTDC_B5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_LTDC_B5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5)
|
||||
# define GPIO_LTDC_B5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN4)
|
||||
# define GPIO_LTDC_B6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_LTDC_B6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6)
|
||||
# define GPIO_LTDC_B6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN5)
|
||||
# define GPIO_LTDC_B7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_LTDC_B7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7)
|
||||
# define GPIO_LTDC_B7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN6)
|
||||
|
||||
# define GPIO_LTDC_VSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_LTDC_VSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
|
||||
# define GPIO_LTDC_VSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN13)
|
||||
# define GPIO_LTDC_HSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_LTDC_HSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10)
|
||||
# define GPIO_LTDC_HSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN12)
|
||||
# define GPIO_LTDC_DE_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
|
||||
# define GPIO_LTDC_DE_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_LTDC_DE_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN7)
|
||||
# define GPIO_LTDC_CLK_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
|
||||
# define GPIO_LTDC_CLK_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_LTDC_CLK_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN14)
|
||||
#endif
|
||||
|
||||
/* Quad SPI */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_QUADSPI_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8)
|
||||
# define GPIO_QUADSPI_BK1_IO0_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_QUADSPI_BK1_IO0_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_QUADSPI_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9)
|
||||
# define GPIO_QUADSPI_BK1_IO1_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_QUADSPI_BK1_IO1_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_QUADSPI_BK1_IO2_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN2)
|
||||
# define GPIO_QUADSPI_BK1_IO2_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN7)
|
||||
# define GPIO_QUADSPI_BK1_IO3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_QUADSPI_BK1_IO3_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_QUADSPI_BK1_IO3_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN6)
|
||||
# define GPIO_QUADSPI_BK1_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_QUADSPI_BK1_NCS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN6)
|
||||
#elif defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_QUADSPI_BK1_NCS_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_QUADSPI_BK2_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN7)
|
||||
# define GPIO_QUADSPI_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN8)
|
||||
# define GPIO_QUADSPI_BK2_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_QUADSPI_BK2_IO2_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN9)
|
||||
# define GPIO_QUADSPI_BK2_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
|
||||
# define GPIO_QUADSPI_BK2_IO3_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN14)
|
||||
# define GPIO_QUADSPI_BK2_NCS (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN11)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_QUADSPI_BK2_IO0_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTH|GPIO_PIN2)
|
||||
# define GPIO_QUADSPI_BK2_IO1_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTH|GPIO_PIN3)
|
||||
#endif
|
||||
|
||||
/* SPDIFRX */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_SPDIFRX_IN0_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN11)
|
||||
# define GPIO_SPDIFRX_IN0_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN7)
|
||||
# define GPIO_SPDIFRX_IN0_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_SPDIFRX_IN1_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN12)
|
||||
# define GPIO_SPDIFRX_IN1_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN8)
|
||||
# define GPIO_SPDIFRX_IN1_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_SPDIFRX_IN2_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN8)
|
||||
# define GPIO_SPDIFRX_IN2_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN4)
|
||||
# define GPIO_SPDIFRX_IN3_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN9)
|
||||
# define GPIO_SPDIFRX_IN3_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
/* Serial Audio Interface */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_SAI1_FS_A_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN4)
|
||||
# define GPIO_SAI1_FS_A_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_SAI1_FS_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN9)
|
||||
# define GPIO_SAI1_FS_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_SAI1_MCLK_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN2)
|
||||
# define GPIO_SAI1_MCLK_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN7)
|
||||
# define GPIO_SAI1_MCLK_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN0)
|
||||
# define GPIO_SAI1_SCK_A_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN5)
|
||||
# define GPIO_SAI1_SCK_A_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_SAI1_SCK_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN8)
|
||||
# define GPIO_SAI1_SCK_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN2)
|
||||
# define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN9)
|
||||
#elif defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_SAI1_FS_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN4)
|
||||
# define GPIO_SAI1_FS_B (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN9)
|
||||
# define GPIO_SAI1_MCLK_A_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN2)
|
||||
# define GPIO_SAI1_MCLK_A_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTG|GPIO_PIN7)
|
||||
# define GPIO_SAI1_MCLK_B (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN7)
|
||||
# define GPIO_SAI1_SCK_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN5)
|
||||
# define GPIO_SAI1_SCK_B (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN8)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN1)
|
||||
# define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN6)
|
||||
# define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN6)
|
||||
# define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN3)
|
||||
# define GPIO_SAI1_SD_B_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN6)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN9)
|
||||
# define GPIO_SAI2_FS_B_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN0)
|
||||
# define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
|
||||
# define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN10)
|
||||
# define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_SAI2_SD_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11)
|
||||
#endif
|
||||
|
||||
/* HDMI-CEC Controller */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_HDMICEC_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_HDMICEC_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN15)
|
||||
#endif
|
||||
|
||||
/* FMPI2C */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define GPIO_FMPI2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_FMPI2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_FMPI2C1_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_FMPI2C1_SCL_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN14)
|
||||
|
||||
# define GPIO_FMPI2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_FMPI2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_FMPI2C1_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN15)
|
||||
# define GPIO_FMPI2C1_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
|
||||
|
||||
# define GPIO_FMPI2C1_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_FMPI2C1_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_PINMAP_H */
|
||||
|
|
|
|||
|
|
@ -1,8 +1,11 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -56,15 +59,24 @@
|
|||
#define STM32_RCC_AHB3ENR_OFFSET 0x0038 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR_OFFSET 0x0040 /* APB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0044 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_AH2BLPENR_OFFSET 0x0054 /* RCC AHB2 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_AH3BLPENR_OFFSET 0x0058 /* RCC AHB3 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_APB2LPENR_OFFSET 0x0064 /* RCC APB2 low power modeperipheral clock enable register */
|
||||
#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2LPENR_OFFSET 0x0054 /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3LPENR_OFFSET 0x0058 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB2LPENR_OFFSET 0x0064 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0074 /* Control/status register */
|
||||
#define STM32_RCC_SSCGR_OFFSET 0x0080 /* Spread spectrum clock generation register */
|
||||
#define STM32_RCC_PLLI2SCFGR_OFFSET 0x0084 /* PLLI2S configuration register */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define STM32_RCC_PLLSAICFGR_OFFSET 0x0088 /* PLLSAI configuration register */
|
||||
# define STM32_RCC_DCKCFGR_OFFSET 0x008c /* Dedicated clocks configuration register */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_RCC_CKGATENR_OFFSET 0x0090 /* Clock gating for the specified IPs */
|
||||
# define STM32_RCC_DCKCFGR2_OFFSET 0x0094 /* Dedicated clocks configuration register */
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
|
|
@ -83,14 +95,23 @@
|
|||
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET)
|
||||
#define STM32_RCC_AH2BLPENR (STM32_RCC_BASE+STM32_RCC_AH2BLPENR)
|
||||
#define STM32_RCC_AH3BLPENR (STM32_RCC_BASE+STM32_RCC_AH3BLPENR_OFFSET)
|
||||
#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR)
|
||||
#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE+STM32_RCC_AHB3LPENR_OFFSET)
|
||||
#define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET)
|
||||
#define STM32_RCC_APB2LPENR (STM32_RCC_BASE+STM32_RCC_APB2LPENR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_SSCGR (STM32_RCC_BASE+STM32_RCC_SSCGR_OFFSET)
|
||||
#define STM32_RCC_PLLI2SCFGR (STM32_RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
#define STM32_RCC_PLLSAICFGR (STM32_RCC_BASE+STM32_RCC_PLLSAICFGR_OFFSET)
|
||||
#define STM32_RCC_DCKCFGR (STM32_RCC_BASE+STM32_RCC_DCKCFGR_OFFSET)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_RCC_CKGATENR (STM32_RCC_BASE+STM32_RCC_CKGATENR_OFFSET)
|
||||
# define STM32_RCC_DCKCFGR2 (STM32_RCC_BASE+STM32_RCC_DCKCFGR2_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
|
|
@ -115,11 +136,11 @@
|
|||
|
||||
/* PLL configuration register */
|
||||
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (0) /* Bits 0-5: Main PLL (PLL) and audio PLL (PLLI2S)
|
||||
* input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (0) /* Bits 0-5: Main PLL (PLL) and audio PLL (PLLI2S)
|
||||
* input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x3f << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT) /* n = 2..63 */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */
|
||||
#define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */
|
||||
|
|
@ -130,14 +151,21 @@
|
|||
# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */
|
||||
# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */
|
||||
#define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S)
|
||||
* entry clock source */
|
||||
* entry clock source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (0)
|
||||
# define RCC_PLLCFG_PLLSRC_HSE RCC_PLLCFG_PLLSRC
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (24) /* Bits 24-27: Main PLL (PLL) divider
|
||||
* (USB OTG FS, SDIO and RNG clocks) */
|
||||
* (USB OTG FS, SDIO and RNG clocks) */
|
||||
#define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
# define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_PLLCFG_PLLR_SHIFT (28) /* Bits 28-30: Main PLLR (PLLR) divider
|
||||
* (I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks) */
|
||||
# define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT)
|
||||
# define RCC_PLLCFG_PLLR(n) ((n) << RCC_PLLCFG_PLLR_SHIFT) /* n=1..7 */
|
||||
#endif
|
||||
|
||||
#define RCC_PLLCFG_RESET (0x24003010) /* PLLCFG reset value */
|
||||
|
||||
/* Clock configuration register */
|
||||
|
|
@ -243,27 +271,49 @@
|
|||
#define RCC_AHB1RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */
|
||||
#define RCC_AHB1RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */
|
||||
#define RCC_AHB1RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */
|
||||
#define RCC_AHB1RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */
|
||||
#define RCC_AHB1RSTR_GPIOJRST (1 << 9) /* Bit 9: IO port J reset */
|
||||
#define RCC_AHB1RSTR_GPIOKRST (1 << 10) /* Bit 10: IO port K reset */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1RSTR_GPIOJRST (1 << 9) /* Bit 9: IO port J reset */
|
||||
# define RCC_AHB1RSTR_GPIOKRST (1 << 10) /* Bit 10: IO port K reset */
|
||||
#endif
|
||||
#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12 CRC reset */
|
||||
#define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA1 reset */
|
||||
#define RCC_AHB1RSTR_DMA2RST (1 << 22) /* Bit 22: DMA2 reset */
|
||||
#define RCC_AHB1RSTR_DMA2DRST (1 << 23) /* Bit 23: DMA2D reset */
|
||||
#define RCC_AHB1RSTR_ETHMACRST (1 << 25) /* Bit 25: Ethernet MAC reset */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1RSTR_DMA2DRST (1 << 23) /* Bit 23: DMA2D reset */
|
||||
# define RCC_AHB1RSTR_ETHMACRST (1 << 25) /* Bit 25: Ethernet MAC reset */
|
||||
#endif
|
||||
#define RCC_AHB1RSTR_OTGHSRST (1 << 29) /* Bit 29: USB OTG HS module reset */
|
||||
|
||||
/* AHB2 peripheral reset register */
|
||||
|
||||
#define RCC_AHB2RSTR_DCMIRST (1 << 0) /* Bit 0: Camera interface reset */
|
||||
#define RCC_AHB2RSTR_CRYPRST (1 << 4) /* Bit 4: Cryptographic module reset */
|
||||
#define RCC_AHB2RSTR_HASHRST (1 << 5) /* Bit 5: Hash module reset */
|
||||
#define RCC_AHB2RSTR_RNGRST (1 << 6) /* Bit 6: Random number generator module reset */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB2RSTR_CRYPRST (1 << 4) /* Bit 4: Cryptographic module reset */
|
||||
# define RCC_AHB2RSTR_HASHRST (1 << 5) /* Bit 5: Hash module reset */
|
||||
# define RCC_AHB2RSTR_RNGRST (1 << 6) /* Bit 6: Random number generator module reset */
|
||||
#endif
|
||||
#define RCC_AHB2RSTR_OTGFSRST (1 << 7) /* Bit 7: USB OTG FS module reset */
|
||||
|
||||
/* AHB3 peripheral reset register */
|
||||
|
||||
#define RCC_AHB3RSTR_FSMCRST (1 << 0) /* Bit 0: Flexible static memory controller module reset */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_AHB3RSTR_QSPIRST (1 << 1) /* Bit 1: QUADSPI memory controller module reset */
|
||||
#endif
|
||||
|
||||
/* APB1 Peripheral reset register */
|
||||
|
||||
|
|
@ -290,6 +340,11 @@
|
|||
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* Bit 26: CAN2 reset */
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
|
||||
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC reset */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB1RSTR_UART7RST (1 << 30) /* Bit 30: USART 7 reset */
|
||||
# define RCC_APB1RSTR_UART8RST (1 << 31) /* Bit 31: USART 8 reset */
|
||||
#endif
|
||||
|
||||
/* APB2 Peripheral reset register */
|
||||
|
||||
|
|
@ -300,10 +355,32 @@
|
|||
#define RCC_APB2RSTR_ADCRST (1 << 8) /* Bit 8: ADC interface reset (common to all ADCs) */
|
||||
#define RCC_APB2RSTR_SDIORST (1 << 11) /* Bit 11: SDIO reset */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2RSTR_SPI4RST (1 << 13) /* Bit 13: SPI4 reset */
|
||||
#endif
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 14) /* Bit 14: System configuration controller reset */
|
||||
#define RCC_APB2RSTR_TIM9RST (1 << 16) /* Bit 16: TIM9 reset */
|
||||
#define RCC_APB2RSTR_TIM10RST (1 << 17) /* Bit 17: TIM10 reset */
|
||||
#define RCC_APB2RSTR_TIM11RST (1 << 18) /* Bit 18: TIM11 reset */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2RSTR_SPI5RST (1 << 20) /* Bit 20: SPI 5 reset */
|
||||
# define RCC_APB2RSTR_SPI6RST (1 << 21) /* Bit 21: SPI 6 reset */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2RSTR_SAI1RST (1 << 22) /* Bit 22: SAI 1 reset */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_APB2RSTR_SAI2RST (1 << 23) /* Bit 23: SAI 2 reset */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2RSTR_LTDCRST (1 << 26) /* Bit 26: LTDC reset */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2RSTR_DSIRST (1 << 27) /* Bit 27: DSI reset */
|
||||
#endif
|
||||
|
||||
/* AHB1 Peripheral Clock enable register */
|
||||
|
||||
|
|
@ -316,33 +393,60 @@
|
|||
#define RCC_AHB1ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */
|
||||
#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */
|
||||
#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */
|
||||
#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
|
||||
#define RCC_AHB1ENR_GPIOJEN (1 << 9) /* Bit 9: IO port J clock enable */
|
||||
#define RCC_AHB1ENR_GPIOKEN (1 << 10) /* Bit 10: IO port K clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1ENR_GPIOJEN (1 << 9) /* Bit 9: IO port J clock enable */
|
||||
# define RCC_AHB1ENR_GPIOKEN (1 << 10) /* Bit 10: IO port K clock enable */
|
||||
#endif
|
||||
#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
|
||||
#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
|
||||
#define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */
|
||||
#endif
|
||||
#define RCC_AHB1ENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */
|
||||
#define RCC_AHB1ENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */
|
||||
#define RCC_AHB1ENR_DMA2DEN (1 << 23) /* Bit 23: DMA2D clock enable */
|
||||
#define RCC_AHB1ENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */
|
||||
#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable */
|
||||
#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) /* Bit 27: Ethernet Reception clock enable */
|
||||
#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1ENR_DMA2DEN (1 << 23) /* Bit 23: DMA2D clock enable */
|
||||
# define RCC_AHB1ENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */
|
||||
# define RCC_AHB1ENR_ETHMACTXEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable */
|
||||
# define RCC_AHB1ENR_ETHMACRXEN (1 << 27) /* Bit 27: Ethernet Reception clock enable */
|
||||
# define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable */
|
||||
#endif
|
||||
#define RCC_AHB1ENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */
|
||||
#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */
|
||||
|
||||
/* AHB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB2ENR_DCMIEN (1 << 0) /* Bit 0: Camera interface enable */
|
||||
#define RCC_AHB2ENR_CRYPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable */
|
||||
#define RCC_AHB2ENR_HASHEN (1 << 5) /* Bit 5: Hash modules clock enable */
|
||||
#define RCC_AHB2ENR_RNGEN (1 << 6) /* Bit 6: Random number generator clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB2ENR_CRYPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable */
|
||||
# define RCC_AHB2ENR_HASHEN (1 << 5) /* Bit 5: Hash modules clock enable */
|
||||
# define RCC_AHB2ENR_RNGEN (1 << 6) /* Bit 6: Random number generator clock enable */
|
||||
#endif
|
||||
#define RCC_AHB2ENR_OTGFSEN (1 << 7) /* Bit 7: USB OTG FS clock enable */
|
||||
|
||||
/* AHB3 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */
|
||||
#define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_AHB3ENR_QSPIEN (1 << 1) /* Bit 1: QUADSPI memory controller module clock enable */
|
||||
#endif
|
||||
|
||||
/* APB1 Peripheral Clock enable register */
|
||||
|
||||
|
|
@ -358,6 +462,9 @@
|
|||
#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */
|
||||
#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_APB1ENR_SPDIFRX (1 << 16) /* Bit 16: SPDIF-Rx clock enable */
|
||||
#endif
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
|
||||
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART3 clock enable */
|
||||
#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART4 clock enable */
|
||||
|
|
@ -365,10 +472,21 @@
|
|||
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */
|
||||
#define RCC_APB1ENR_I2C3EN (1 << 23) /* Bit 23: I2C3 clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_APB1ENR_FMPI2C1EN (1 << 24) /* Bit 24: FMPI2C1 clock enable */
|
||||
#endif
|
||||
#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN 1 clock enable */
|
||||
#define RCC_APB1ENR_CAN2EN (1 << 26) /* Bit 26: CAN 2 clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_APB1ENR_CECEN (1 << 27) /* Bit 27: CEC clock enable */
|
||||
#endif
|
||||
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
|
||||
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB1ENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */
|
||||
# define RCC_APB1ENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */
|
||||
#endif
|
||||
|
||||
/* APB2 Peripheral Clock enable register */
|
||||
|
||||
|
|
@ -381,10 +499,32 @@
|
|||
#define RCC_APB2ENR_ADC3EN (1 << 10) /* Bit 10: ADC3 clock enable */
|
||||
#define RCC_APB2ENR_SDIOEN (1 << 11) /* Bit 11: SDIO clock enable */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: SPI4 clock enable */
|
||||
#endif
|
||||
#define RCC_APB2ENR_SYSCFGEN (1 << 14) /* Bit 14: System configuration controller clock enable */
|
||||
#define RCC_APB2ENR_TIM9EN (1 << 16) /* Bit 16: TIM9 clock enable */
|
||||
#define RCC_APB2ENR_TIM10EN (1 << 17) /* Bit 17: TIM10 clock enable */
|
||||
#define RCC_APB2ENR_TIM11EN (1 << 18) /* Bit 18: TIM11 clock enable */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: SPI5 clock enable */
|
||||
# define RCC_APB2ENR_SPI6EN (1 << 21) /* Bit 21: SPI6 clock enable */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: SAI1 clock enable */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: SAI2 clock enable */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2ENR_LTDCEN (1 << 26) /* Bit 26: LTDC clock enable */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2ENR_DSIEN (1 << 27) /* Bit 27: DSI clock enable */
|
||||
#endif
|
||||
|
||||
/* RCC AHB1 low power mode peripheral clock enable register */
|
||||
|
||||
|
|
@ -397,37 +537,67 @@
|
|||
#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1LPENR_GPIOJLPEN (1 << 9) /* Bit 9: IO port J clock enable during Sleep mode */
|
||||
# define RCC_AHB1LPENR_GPIOKLPEN (1 << 10) /* Bit 10: IO port K clock enable during Sleep mode */
|
||||
#endif
|
||||
#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_CCMDATARAMLPEN (1 << 20) /* Bit 20: CCM data RAM clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1LPENR_SRAM3LPEN (1 << 19) /* Bit 19: SRAM 3 interface clock enable during Sleep mode */
|
||||
#endif
|
||||
#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_DMA2DLPEN (1 << 23) /* Bit 23: DMA2D clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB1LPENR_DMA2DLPEN (1 << 23) /* Bit 23: DMA2D clock enable during Sleep mode */
|
||||
# define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */
|
||||
# define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */
|
||||
# define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */
|
||||
# define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */
|
||||
#endif
|
||||
#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */
|
||||
|
||||
/* RCC AHB2 low power modeperipheral clock enable register */
|
||||
/* RCC AHB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB2LPENR_DCMILPEN (1 << 0) /* Bit 0: Camera interface enable during Sleep mode */
|
||||
#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable during Sleep mode */
|
||||
#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* Bit 5: Hash modules clock enable during Sleep mode */
|
||||
#define RCC_AHB2LPENR_RNGLPEN (1 << 6) /* Bit 6: Random number generator clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_AHB2LPENR_CRYPLPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable during Sleep mode */
|
||||
# define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* Bit 5: Hash modules clock enable during Sleep mode */
|
||||
# define RCC_AHB2LPENR_RNGLPEN (1 << 6) /* Bit 6: Random number generator clock enable during Sleep mode */
|
||||
#endif
|
||||
#define RCC_AHB2LPENR_OTGFLPSEN (1 << 7) /* Bit 7: USB OTG FS clock enable during Sleep mode */
|
||||
|
||||
/* RCC AHB3 low power modeperipheral clock enable register */
|
||||
/* RCC AHB3 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB3LPENR_FSMLPEN (1 << 0) /* Bit 0: Flexible static memory controller module clock
|
||||
#define RCC_AHB3LPENR_FSMCLPEN (1 << 0) /* Bit 0: Flexible static memory controller module clock
|
||||
* enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_AHB3LPENR_QSPILPEN (1 << 1) /* Bit 1: QUADSPI memory controller module clock enable
|
||||
* during Sleep mode */
|
||||
#endif
|
||||
|
||||
/* RCC APB1 low power modeperipheral clock enable register */
|
||||
/* RCC APB1 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB1LPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM3 clock enable during Sleep mode */
|
||||
|
|
@ -441,6 +611,9 @@
|
|||
#define RCC_APB1LPENR_WWDGLPEN (1 << 11) /* Bit 11: Window watchdog clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI3 clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_APB1LPENR_SPDIFRXLPEN (1 << 16) /* Bit 16: SPDIF-Rx clock enable during Sleep mode */
|
||||
#endif
|
||||
#define RCC_APB1LPENR_USART2LPEN (1 << 17) /* Bit 17: USART 2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_USART3LPEN (1 << 18) /* Bit 18: USART3 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_UART4LPEN (1 << 19) /* Bit 19: UART4 clock enable during Sleep mode */
|
||||
|
|
@ -448,10 +621,21 @@
|
|||
#define RCC_APB1LPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C1 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_I2C3LPEN (1 << 23) /* Bit 23: I2C3 clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_APB1LPENR_FMPI2C1LPEN (1 << 24) /* Bit 24: FMPI2C1 clock enable during Sleep mode */
|
||||
#endif
|
||||
#define RCC_APB1LPENR_CAN1LPEN (1 << 25) /* Bit 25: CAN 1 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_CAN2LPEN (1 << 26) /* Bit 26: CAN 2 clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_APB1LPENR_CECLPEN (1 << 27) /* Bit 27: CEC clock enable during Sleep mode */
|
||||
#endif
|
||||
#define RCC_APB1LPENR_PWRLPEN (1 << 28) /* Bit 28: Power interface clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_DACLPEN (1 << 29) /* Bit 29: DAC interface clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB1LPENR_UART7LPEN (1 << 30) /* Bit 30: UART7 clock enable during Sleep mode */
|
||||
# define RCC_APB1LPENR_UART8LPEN (1 << 31) /* Bit 31: UART8 clock enable during Sleep mode */
|
||||
#endif
|
||||
|
||||
/* RCC APB2 low power mode peripheral clock enable register */
|
||||
|
||||
|
|
@ -464,16 +648,44 @@
|
|||
#define RCC_APB2LPENR_ADC3LPEN (1 << 10) /* Bit 10: ADC3 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SDIOLPEN (1 << 11) /* Bit 11: SDIO clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI4 clock enable during Sleep mode */
|
||||
#endif
|
||||
#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) /* Bit 14: System configuration controller clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM9LPEN (1 << 16) /* Bit 16: TIM9 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM10LPEN (1 << 17) /* Bit 17: TIM10 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM11LPEN (1 << 18) /* Bit 18: TIM11 clock enable during Sleep mode */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* Bit 20: SPI5 clock enable during Sleep mode */
|
||||
# define RCC_APB2LPENR_SPI6LPEN (1 << 21) /* Bit 21: SPI6 clock enable during Sleep mode */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* Bit 22: SAI1 clock enable during Sleep mode */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* Bit 23: SAI2 clock enable during Sleep mode */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2LPENR_LTDCLPEN (1 << 26) /* Bit 26: LTDC clock enable during Sleep mode */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_APB2LPENR_DSILPEN (1 << 27) /* Bit 27: DSI clock enable during Sleep mode */
|
||||
#endif
|
||||
|
||||
/* Backup domain control register */
|
||||
|
||||
#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */
|
||||
#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */
|
||||
#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_BDCR_LSEMOD_SHIFT (3) /* Bit 3: External Low Speed oscillator mode */
|
||||
# define RCC_BDCR_LSEMOD_MASK (1 << RCC_BDCR_LSEMOD_SHIFT)
|
||||
# define RCC_BDCR_LSEMOD_LOWPWR (0 << RCC_BDCR_LSEMOD_SHIFT) /* LSE oscillator "low power" mode selection */
|
||||
# define RCC_BDCR_LSEMOD_HIDRIVE (1 << RCC_BDCR_LSEMOD_SHIFT) /* LSE oscillator "high drive" mode selection */
|
||||
#endif
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
|
||||
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
|
||||
|
|
@ -498,43 +710,182 @@
|
|||
|
||||
/* Spread spectrum clock generation register */
|
||||
|
||||
#define RCC_SSCGR_MODPER_SHIFT (0) /* Bit 0-12: Modulation period */
|
||||
#define RCC_SSCGR_MODPER_SHIFT (0) /* Bit 0-12: Modulation period */
|
||||
#define RCC_SSCGR_MODPER_MASK (0x1fff << RCC_SSCGR_MODPER_SHIFT)
|
||||
# define RCC_SSCGR_MODPER(n) ((n) << RCC_SSCGR_MODPER_SHIFT)
|
||||
#define RCC_SSCGR_INCSTEP_SHIFT (13) /* Bit 13-27: Incrementation step */
|
||||
#define RCC_SSCGR_INCSTEP_SHIFT (13) /* Bit 13-27: Incrementation step */
|
||||
#define RCC_SSCGR_INCSTEP_MASK (0x7fff << RCC_SSCGR_INCSTEP_SHIFT)
|
||||
# define RCC_SSCGR_INCSTEP(n) ((n) << RCC_SSCGR_INCSTEP_SHIFT)
|
||||
#define RCC_SSCGR_SPREADSEL (1 << 30) /* Bit 30: Spread Select */
|
||||
#define RCC_SSCGR_SSCGEN (1 << 31) /* Bit 31: Spread spectrum modulation enable */
|
||||
#define RCC_SSCGR_SPREADSEL (1 << 30) /* Bit 30: Spread Select */
|
||||
#define RCC_SSCGR_SSCGEN (1 << 31) /* Bit 31: Spread spectrum modulation enable */
|
||||
|
||||
/* PLLI2S configuration register */
|
||||
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT (6) /* Bits 6-14: PLLI2S multiplication factor for VCO */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
|
||||
#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SM_SHIFT (0) /* Bits 0-5: Division factor M for audio PLL
|
||||
* (PLLI2S) input clock */
|
||||
# define RCC_PLLI2SCFGR_PLLI2SM_MASK (0x3f << RCC_PLLI2SCFGR_PLLI2SM_SHIFT)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SM(n) ((n) << RCC_PLLI2SCFGR_PLLI2SM_SHIFT)
|
||||
#endif
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT (6) /* Bits 6-14: PLLI2S N multiplication factor for VCO */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SN(n) ((n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIF-Rx clock */
|
||||
# define RCC_PLLI2SCFGR_PLLI2SP_MASK (0x3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
|
||||
/* Set PLLI2S P to 2,4,6,8 */
|
||||
# define RCC_PLLI2SCFGR_PLLI2SP(n) (((((n)-2)/2) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) & RCC_PLLI2SCFGR_PLLI2SP_MASK)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAI1 clock */
|
||||
# define RCC_PLLI2SCFGR_PLLI2SQ_MASK (0xf << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SQ(n) ((n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
|
||||
#endif
|
||||
#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SR(n) ((n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
|
||||
|
||||
/* PLLSAI configuration register */
|
||||
|
||||
#define RCC_PLLSAICFGR_PLLSAIN_SHIFT (6) /* Bits 6-14: PLLSAI divider (N) for VCO */
|
||||
#define RCC_PLLSAICFGR_PLLSAIN_MASK (0x1ff << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
|
||||
#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */
|
||||
#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
|
||||
#define RCC_PLLSAICFGR_PLLSAIR_SHIFT (28) /* Bits 28-30: PLLSAI division factor for LCD clock */
|
||||
#define RCC_PLLSAICFGR_PLLSAIR_MASK (7 << RCC_PLLSAICFGR_PLLSAIR_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIR(n) ((n) << RCC_PLLSAICFGR_PLLSAIR_SHIFT)
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_PLLSAICFGR_PLLSAIM_SHIFT (0) /* Bits 0-5: Division factor M for audio PLLSAI
|
||||
* input clock */
|
||||
# define RCC_PLLSAICFGR_PLLSAIM_MASK (0x3f << RCC_PLLSAICFGR_PLLSAIM_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIM(n) ((n) << RCC_PLLSAICFGR_PLLSAIM_SHIFT)
|
||||
# endif
|
||||
# define RCC_PLLSAICFGR_PLLSAIN_SHIFT (6) /* Bits 6-14: PLLSAI divider (N) for VCO */
|
||||
# define RCC_PLLSAICFGR_PLLSAIN_MASK (0x1ff << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
|
||||
# if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48 MHz clock */
|
||||
# define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
|
||||
/* Set PLLSAI P to 2,4,6,8 */
|
||||
# define RCC_PLLSAICFGR_PLLSAIP(n) (((((n)-2)/2) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) & RCC_PLLSAICFGR_PLLSAIP_MASK)
|
||||
# endif
|
||||
# define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */
|
||||
# define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
|
||||
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_PLLSAICFGR_PLLSAIR_SHIFT (28) /* Bits 28-30: PLLSAI division factor for LCD clock */
|
||||
# define RCC_PLLSAICFGR_PLLSAIR_MASK (7 << RCC_PLLSAICFGR_PLLSAIR_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIR(n) ((n) << RCC_PLLSAICFGR_PLLSAIR_SHIFT)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Dedicated clocks configuration register */
|
||||
|
||||
#define RCC_SAICLKSRC_PLLSAI 0
|
||||
#define RCC_SAICLKSRC_PLLI2S 1
|
||||
#define RCC_SAICLKSRC_ALTERNATE 2
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_DCKCFGR_PLLI2SDIVQ_SHIFT (0) /* Bits 0-4: PLLI2S division 1..32 factor for I2S clock */
|
||||
# define RCC_DCKCFGR_PLLI2SDIVQ_MASK (0x1f << RCC_DCKCFGR_PLLI2SDIVQ_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLI2SDIVQ(n) (((n)-1) << RCC_DCKCFGR_PLLI2SDIVQ_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVQ_SHIFT (8) /* Bits 8-12: PLLSAI division 1..32 factor for SAI clock */
|
||||
# define RCC_DCKCFGR_PLLSAIDIVQ_MASK (0x1f << RCC_DCKCFGR_PLLSAIDIVQ_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVQ(n) (((n)-1) << RCC_DCKCFGR_PLLSAIDIVQ_SHIFT)
|
||||
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVR_SHIFT (16) /* Bits 16-17: PLLSAI division factor for LCD_CLK clock */
|
||||
# define RCC_DCKCFGR_PLLSAIDIVR_MASK (0x3 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVR_DIV2 (0 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVR_DIV4 (1 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVR_DIV8 (2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVR_DIV16 (3 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1ASRC_SHIFT (20) /* Bits 20-21: SAI1-A clock source selection */
|
||||
# define RCC_DCKCFGR_SAI1ASRC_MASK (0x3 << RCC_DCKCFGR_SAI1ASRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1ASRC_PLLSAI (0 << RCC_DCKCFGR_SAI1ASRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1ASRC_PLLI2S (1 << RCC_DCKCFGR_SAI1ASRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1ASRC_ALTERNATE (2 << RCC_DCKCFGR_SAI1ASRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1BSRC_SHIFT (22) /* Bits 22-23: SAI1-B clock source selection */
|
||||
# define RCC_DCKCFGR_SAI1BSRC_MASK (0x3 << RCC_DCKCFGR_SAI1BSRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1BSRC_PLLSAI (0 << RCC_DCKCFGR_SAI1BSRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1BSRC_PLLI2S (1 << RCC_DCKCFGR_SAI1BSRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1BSRC_ALTERNATE (2 << RCC_DCKCFGR_SAI1BSRC_SHIFT)
|
||||
# endif
|
||||
# if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_DCKCFGR_SAI1SRC_SHIFT (20) /* Bits 20-21: SAI1 clock source selection */
|
||||
# define RCC_DCKCFGR_SAI1SRC_MASK (0x3 << RCC_DCKCFGR_SAI1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1SRC_PLLSAI (0 << RCC_DCKCFGR_SAI1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1SRC_PLLI2S (1 << RCC_DCKCFGR_SAI1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1SRC_PLL (2 << RCC_DCKCFGR_SAI1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1SRC_I2S_CKIN (3 << RCC_DCKCFGR_SAI1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI2SRC_SHIFT (22) /* Bits 22-23: SAI2 clock source selection */
|
||||
# define RCC_DCKCFGR_SAI2SRC_MASK (0x3 << RCC_DCKCFGR_SAI2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI2SRC_PLLSAI (0 << RCC_DCKCFGR_SAI2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI2SRC_PLLI2S (1 << RCC_DCKCFGR_SAI2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI2SRC_PLL (2 << RCC_DCKCFGR_SAI2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI2SRC_HSX (3 << RCC_DCKCFGR_SAI2SRC_SHIFT)
|
||||
# endif
|
||||
# define RCC_DCKCFGR_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */
|
||||
# if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_DCKCFGR_I2S1SRC_SHIFT (25) /* Bits 25-26: I2S APB1 clock source selection */
|
||||
# define RCC_DCKCFGR_I2S1SRC_MASK (0x3 << RCC_DCKCFGR_I2S1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S1SRC_PLLI2S (0 << RCC_DCKCFGR_I2S1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S1SRC_I2S_CKIN (1 << RCC_DCKCFGR_I2S1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S1SRC_PLL (2 << RCC_DCKCFGR_I2S1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S1SRC_HSX (3 << RCC_DCKCFGR_I2S1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S2SRC_SHIFT (28) /* Bits 28-29: I2S APB2 clock source selection */
|
||||
# define RCC_DCKCFGR_I2S2SRC_MASK (0x3 << RCC_DCKCFGR_I2S2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S2SRC_PLLI2S (0 << RCC_DCKCFGR_I2S2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S2SRC_I2S_CKIN (1 << RCC_DCKCFGR_I2S2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S2SRC_PLL (2 << RCC_DCKCFGR_I2S2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S2SRC_HSX (3 << RCC_DCKCFGR_I2S2SRC_SHIFT)
|
||||
# endif
|
||||
# if defined(CONFIG_STM32_STM32F469)
|
||||
# define RCC_DCKCFGR_48MSEL_SHIFT (27) /* Bit 27: 48 MHz clock source selection */
|
||||
# define RCC_DCKCFGR_48MSEL_MASK (1 << RCC_DCKCFGR_48MSEL_SHIFT)
|
||||
# define RCC_DCKCFGR_48MSEL_PLL (0 << RCC_DCKCFGR_48MSEL_SHIFT) /* 48 MHz clock from PLL is selected */
|
||||
# define RCC_DCKCFGR_48MSEL_PLLSAI (1 << RCC_DCKCFGR_48MSEL_SHIFT) /* 48 MHz clock from PLLSAI is selected */
|
||||
# define RCC_DCKCFGR_SDMMCSEL_SHIFT (28) /* Bit 28: SDMMC clock source selection */
|
||||
# define RCC_DCKCFGR_SDMMCSEL_MASK (1 << RCC_DCKCFGR_SDMMCSEL_SHIFT)
|
||||
# define RCC_DCKCFGR_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */
|
||||
# define RCC_DCKCFGR_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */
|
||||
# define RCC_DCKCFGR_DSISEL_SHIFT (29) /* Bit 29: DSI clock selection */
|
||||
# define RCC_DCKCFGR_DSISEL_MASK (1 << RCC_DCKCFGR_DSISEL_SHIFT)
|
||||
# define RCC_DCKCFGR_DSISEL_DSIPHY (0 << RCC_DCKCFGR_DSISEL_SHIFT) /* DSI-PHY clock is selected as DSI clock */
|
||||
# define RCC_DCKCFGR_DSISEL_PLL (1 << RCC_DCKCFGR_DSISEL_SHIFT) /* PLL clock is selected as DSI clock */
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#define RCC_PLLSAIDIVR_DIV2 0
|
||||
#define RCC_PLLSAIDIVR_DIV4 1
|
||||
#define RCC_PLLSAIDIVR_DIV8 2
|
||||
#define RCC_PLLSAIDIVR_DIV16 3
|
||||
/* RCC clocks gated enable register */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_CKGATENR_AHB2APB1_CKEN (1 << 0) /* Bit 0: AHB to APB1 Bridge clock enable */
|
||||
# define RCC_CKGATENR_AHB2APB2_CKEN (1 << 1) /* Bit 1: AHB to APB2 Bridge clock enable */
|
||||
# define RCC_CKGATENR_CM4DBG_CKEN (1 << 2) /* Bit 2: Cortex M4 ETM clock enable */
|
||||
# define RCC_CKGATENR_SPARE_CKEN (1 << 3) /* Bit 3: Spare clock enable */
|
||||
# define RCC_CKGATENR_SRAM_CKEN (1 << 4) /* Bit 4: SRAM controller clock enable */
|
||||
# define RCC_CKGATENR_FLITF_CKEN (1 << 5) /* Bit 5: Flash Interface clock enable */
|
||||
# define RCC_CKGATENR_RCC_CKEN (1 << 6) /* Bit 6: RCC clock enable */
|
||||
#endif
|
||||
|
||||
/* Dedicated clocks configuration register 2 */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define RCC_DCKCFGR2_FMPI2C1SEL_SHIFT (22) /* Bits 22-23: I2C4 clock source selection */
|
||||
# define RCC_DCKCFGR2_FMPI2C1SEL_MASK (3 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_FMPI2C1SEL_APB (0 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 4 clock */
|
||||
# define RCC_DCKCFGR2_FMPI2C1SEL_SYSCLK (1 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) /* System clock is selected as I2C 4 clock */
|
||||
# define RCC_DCKCFGR2_FMPI2C1SEL_HSI (2 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) /* HSI clock is selected as I2C 4 clock */
|
||||
# define RCC_DCKCFGR2_CECSEL_SHIFT (26) /* Bit 26: HDMI-CEC clock source selection */
|
||||
# define RCC_DCKCFGR2_CECSEL_MASK (1 << RCC_DCKCFGR2_CECSEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_CECSEL_LSE (0 << RCC_DCKCFGR2_CECSEL_SHIFT) /* LSE clock is selected as HDMI-CEC clock */
|
||||
# define RCC_DCKCFGR2_CECSEL_HSI (1 << RCC_DCKCFGR2_CECSEL_SHIFT) /* HSI clock is selected as HDMI-CEC clock */
|
||||
# define RCC_DCKCFGR2_CK48MSEL_SHIFT (27) /* Bit 27: 48 MHz clock source selection */
|
||||
# define RCC_DCKCFGR2_CK48MSEL_MASK (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_CK48MSEL_PLL (0 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48 MHz clock from PLL is selected */
|
||||
# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48 MHz clock from PLLSAI is selected */
|
||||
# define RCC_DCKCFGR2_SDIOSEL_SHIFT (28) /* Bit 28: SDIO clock source selection */
|
||||
# define RCC_DCKCFGR2_SDIOSEL_MASK (1 << RCC_DCKCFGR2_SDIOSEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_SDIOSEL_48MHZ (0 << RCC_DCKCFGR2_SDIOSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */
|
||||
# define RCC_DCKCFGR2_SDIOSEL_SYSCLK (1 << RCC_DCKCFGR2_SDIOSEL_SHIFT) /* System clock is selected as SDMMC clock */
|
||||
# define RCC_DCKCFGR2_SPDIFRXSEL_SHIFT (29) /* Bit 29: SPDIF-Rx clock selection */
|
||||
# define RCC_DCKCFGR2_SPDIFRXSEL_MASK (1 << RCC_DCKCFGR2_SPDIFRXSEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_SPDIFRXSEL_PLL (0 << RCC_DCKCFGR2_SPDIFRXSEL_SHIFT) /* PLL clock is selected as SPDIF-Rx clock */
|
||||
# define RCC_DCKCFGR2_SPDIFRXSEL_PLLI2S (1 << RCC_DCKCFGR2_SPDIFRXSEL_SHIFT) /* PLLI2S clock is selected as SPDIF-Rx clock */
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_RCC_H */
|
||||
|
|
|
|||
|
|
@ -1,8 +1,11 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f40xxx_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011, 2013, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -61,6 +64,9 @@
|
|||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
|
||||
#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_SYSCFG_CFGR_OFFSET 0x002c /* SYSCFG configuration register */
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
|
|
@ -74,6 +80,9 @@
|
|||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define STM32_SYSCFG_CFGR (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
|
|
@ -86,9 +95,33 @@
|
|||
# define SYSCFG_MEMRMP_FSMC (2 << SYSCFG_MEMRMP_SHIFT) /* 10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 11: Embedded SRAM (112kB) mapped at 0x0000 0000 */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define SYSCFG_FBMODE_SHIFT (8) /* Bit 8 FB_MODE: Flash Bank mode selection */
|
||||
# define SYSCFG_FBMODE_MASK (1 << SYSCFG_FBMODE_SHIFT)
|
||||
# define SYSCFG_FBMODE_FB12 (0 << SYSCFG_FBMODE_SHIFT) /* 0: Flash Bank 1 is mapped at 0x0800 0000 and
|
||||
* Flash Bank 2 is mapped at 0x0810 0000 */
|
||||
# define SYSCFG_FBMODE_FB21 (1 << SYSCFG_FBMODE_SHIFT) /* 1: Flash Bank 2 is mapped at 0x0800 0000 and
|
||||
* Flash Bank 1 is mapped at 0x0810 0000 */
|
||||
#endif
|
||||
|
||||
#define SYSCFG_SWPFMC_SHIFT (10) /* Bits 10:11 SWP_FMC: FMC memory mapping swap */
|
||||
#define SYSCFG_SWPFMC_MASK (3 << SYSCFG_SWPFMC_SHIFT)
|
||||
# define SYSCFG_SWPFMC_NOSWAP (0 << SYSCFG_SWPFMC_SHIFT) /* 00: No FMC memory mapping swap */
|
||||
# define SYSCFG_SWPFMC_SWAP (1 << SYSCFG_SWPFMC_SHIFT) /* 01: SDRAM banks and NAND Bank 2/PCCARD mapping are swapped */
|
||||
|
||||
/* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define SYSCFG_PMC_MII_RMII_SEL (1 << 23) /* Bit 23: Ethernet PHY interface selection */
|
||||
#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# define SYSCFG_PMC_MII_RMII_SEL (1 << 23) /* Bit 23: Ethernet PHY interface selection */
|
||||
#endif
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
|
|
@ -100,46 +133,57 @@
|
|||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
# define SYSCFG_EXTICR_PORTJ (9) /* 1001: PJ[x] pin */
|
||||
# define SYSCFG_EXTICR_PORTK (10) /* 1010: PK[x] pin */
|
||||
#endif
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* Compensation cell control register */
|
||||
|
|
@ -147,5 +191,12 @@
|
|||
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
|
||||
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
|
||||
|
||||
/* SYSCFG configuration register */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define SYSCFG_CFGR_FMPI2C1_SCL (1 << 0) /* Bit 0: Forces FM+ drive capability on SCL */
|
||||
# define SYSCFG_CFGR_FMPI2C1_SDA (1 << 1) /* Bit 8: Forces FM+ drive capability on SDA */
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F40XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_SYSCFG_H */
|
||||
|
|
|
|||
|
|
@ -1,8 +1,11 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f40xxx_vectors.h
|
||||
*
|
||||
* Copyright (C) 2011-2012, 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -38,7 +41,7 @@
|
|||
************************************************************************************/
|
||||
|
||||
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
|
||||
* supplies ach STM32F40xxx vector in terms of a (lower-case) ISR label and an
|
||||
* supplies each STM32F40xxx vector in terms of a (lower-case) ISR label and an
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f40xxx_irq.h.
|
||||
* stm32_vectors.S will define the VECTOR macro in different ways in order to generate
|
||||
* the interrupt vectors and handlers in their final form.
|
||||
|
|
@ -52,7 +55,18 @@
|
|||
|
||||
/* Reserve interrupt table entries for I/O interrupts. */
|
||||
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS 82
|
||||
# if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
|
||||
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407)
|
||||
# define ARMV7M_PERIPHERAL_INTERRUPTS 82
|
||||
# elif defined(CONFIG_STM32_STM32F427)
|
||||
# define ARMV7M_PERIPHERAL_INTERRUPTS 87
|
||||
# elif defined(CONFIG_STM32_STM32F429)
|
||||
# define ARMV7M_PERIPHERAL_INTERRUPTS 91
|
||||
# elif defined(CONFIG_STM32_STM32F446)
|
||||
# define ARMV7M_PERIPHERAL_INTERRUPTS 97
|
||||
# elif defined(CONFIG_STM32_STM32F469)
|
||||
# define ARMV7M_PERIPHERAL_INTERRUPTS 93
|
||||
# endif
|
||||
|
||||
#else
|
||||
|
||||
|
|
@ -117,8 +131,13 @@ VECTOR(stm32_dma2s1, STM32_IRQ_DMA2S1) /* Vector 16+57: DMA2 Stream 1
|
|||
VECTOR(stm32_dma2s2, STM32_IRQ_DMA2S2) /* Vector 16+58: DMA2 Stream 2 global interrupt */
|
||||
VECTOR(stm32_dma2s3, STM32_IRQ_DMA2S3) /* Vector 16+59: DMA2 Stream 3 global interrupt */
|
||||
VECTOR(stm32_dma2s4, STM32_IRQ_DMA2S4) /* Vector 16+60: DMA2 Stream 4 global interrupt */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
UNUSED(STM32_IRQ_RESERVED61) /* Vector 16+61: Reserved */
|
||||
UNUSED(STM32_IRQ_RESERVED62) /* Vector 16+62: Reserved */
|
||||
#else
|
||||
VECTOR(stm32_eth, STM32_IRQ_ETH) /* Vector 16+61: Ethernet global interrupt */
|
||||
VECTOR(stm32_ethwkup, STM32_IRQ_ETHWKUP) /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
|
||||
#endif
|
||||
VECTOR(stm32_can2tx, STM32_IRQ_CAN2TX) /* Vector 16+63: CAN2 TX interrupts */
|
||||
VECTOR(stm32_can2rx0, STM32_IRQ_CAN2RX0) /* Vector 16+64: CAN2 RX0 interrupts */
|
||||
VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 interrupt */
|
||||
|
|
@ -135,8 +154,59 @@ VECTOR(stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN) /* Vector 16+75: USB On The Go
|
|||
VECTOR(stm32_otghswkup, STM32_IRQ_OTGHSWKUP) /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
VECTOR(stm32_otghs, STM32_IRQ_OTGHS) /* Vector 16+77: USB On The Go HS global interrupt */
|
||||
VECTOR(stm32_dcmi, STM32_IRQ_DCMI) /* Vector 16+78: DCMI global interrupt */
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
UNUSED(STM32_IRQ_RESERVED79) /* Vector 16+79: Reserved */
|
||||
UNUSED(STM32_IRQ_RESERVED80) /* Vector 16+80: Reserved */
|
||||
#else
|
||||
VECTOR(stm32_cryp, STM32_IRQ_CRYP) /* Vector 16+79: CRYP crypto global interrupt */
|
||||
VECTOR(stm32_hash, STM32_IRQ_HASH) /* Vector 16+80: Hash and Rng global interrupt */
|
||||
#endif
|
||||
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* Vector 16+81: FPU global interrupt */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
VECTOR(stm32_uart7, STM32_IRQ_UART7) /* Vector 16+82: UART7 interrupt */
|
||||
VECTOR(stm32_uart8, STM32_IRQ_UART8) /* Vector 16+83: UART8 interrupt */
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
UNUSED(STM32_IRQ_RESERVED82) /* Vector 16+82: Reserved */
|
||||
UNUSED(STM32_IRQ_RESERVED83) /* Vector 16+83: Reserved */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
VECTOR(stm32_spi4, STM32_IRQ_SPI4) /* Vector 16+84: SPI4 interrupt */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F469)
|
||||
VECTOR(stm32_spi5, STM32_IRQ_SPI5) /* Vector 16+85: SPI5 interrupt */
|
||||
VECTOR(stm32_spi6, STM32_IRQ_SPI6) /* Vector 16+86: SPI6 interrupt */
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
UNUSED(STM32_IRQ_RESERVED85) /* Vector 16+85: Reserved */
|
||||
UNUSED(STM32_IRQ_RESERVED86) /* Vector 16+86: Reserved */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
VECTOR(stm32_sai1, STM32_IRQ_SAI1) /* Vector 16+87: SAI1 interrupt */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469)
|
||||
VECTOR(stm32_ltdcint, STM32_IRQ_LTDCINT) /* Vector 16+88: LTDC interrupt */
|
||||
VECTOR(stm32_ltdcerrint, STM32_IRQ_LTDCERRINT) /* Vector 16+89: LTDC Error interrupt */
|
||||
VECTOR(stm32_dma2d, STM32_IRQ_DMA2D) /* Vector 16+90: DMA2D interrupt */
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
UNUSED(STM32_IRQ_RESERVED88) /* Vector 16+88: Reserved */
|
||||
UNUSED(STM32_IRQ_RESERVED89) /* Vector 16+89: Reserved */
|
||||
UNUSED(STM32_IRQ_RESERVED90) /* Vector 16+90: Reserved */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
VECTOR(stm32_sai2, STM32_IRQ_SAI2) /* Vector 16+91: SAI2 Global interrupt */
|
||||
VECTOR(stm32_quadspi, STM32_IRQ_QUADSPI) /* Vector 16+92: QuadSPI Global interrupt */
|
||||
#elif defined(CONFIG_STM32_STM32F469)
|
||||
VECTOR(stm32_quadspi, STM32_IRQ_QUADSPI) /* Vector 16+91: QuadSPI Global interrupt */
|
||||
VECTOR(stm32_dsi, STM32_IRQ_DSI) /* Vector 16+92: DSI Global interrupt */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
VECTOR(stm32_hdmicec, STM32_IRQ_HDMICEC) /* Vector 16+93: HDMI-CEC Global interrupt */
|
||||
VECTOR(stm32_spdifrx, STM32_IRQ_SPDIFRX) /* Vector 16+94: SPDIF-Rx Global interrupt */
|
||||
VECTOR(stm32_fmpi2c1, STM32_IRQ_FMPI2C1) /* Vector 16+95: FMPI2C1 event interrupt */
|
||||
VECTOR(stm32_fmpi2c1err, STM32_IRQ_FMPI2C1ERR) /* Vector 16+96: FMPI2C1 Error event interrupt */
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_ARMV7M_CMNVECTOR */
|
||||
|
|
|
|||
|
|
@ -1,544 +0,0 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f42xxx_dma.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* 2 DMA controllers */
|
||||
|
||||
#define DMA1 (0)
|
||||
#define DMA2 (1)
|
||||
|
||||
/* 8 DMA streams */
|
||||
|
||||
#define DMA_STREAM0 (0)
|
||||
#define DMA_STREAM1 (1)
|
||||
#define DMA_STREAM2 (2)
|
||||
#define DMA_STREAM3 (3)
|
||||
#define DMA_STREAM4 (4)
|
||||
#define DMA_STREAM5 (5)
|
||||
#define DMA_STREAM6 (6)
|
||||
#define DMA_STREAM7 (7)
|
||||
|
||||
/* 8 DMA channels */
|
||||
|
||||
#define DMA_CHAN0 (0)
|
||||
#define DMA_CHAN1 (1)
|
||||
#define DMA_CHAN2 (2)
|
||||
#define DMA_CHAN3 (3)
|
||||
#define DMA_CHAN4 (4)
|
||||
#define DMA_CHAN5 (5)
|
||||
#define DMA_CHAN6 (6)
|
||||
#define DMA_CHAN7 (7)
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */
|
||||
#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */
|
||||
#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */
|
||||
#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */
|
||||
|
||||
#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n))
|
||||
#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */
|
||||
#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */
|
||||
#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */
|
||||
#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */
|
||||
#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */
|
||||
#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */
|
||||
|
||||
#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */
|
||||
#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */
|
||||
#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */
|
||||
#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */
|
||||
#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */
|
||||
#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */
|
||||
#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */
|
||||
#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */
|
||||
|
||||
#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */
|
||||
#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */
|
||||
#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */
|
||||
#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */
|
||||
#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */
|
||||
#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */
|
||||
#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */
|
||||
#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */
|
||||
|
||||
#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */
|
||||
#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */
|
||||
#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */
|
||||
#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */
|
||||
#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */
|
||||
#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */
|
||||
#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */
|
||||
#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */
|
||||
|
||||
#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */
|
||||
#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */
|
||||
#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */
|
||||
#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */
|
||||
#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */
|
||||
#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */
|
||||
#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */
|
||||
#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */
|
||||
|
||||
#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */
|
||||
#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */
|
||||
#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */
|
||||
#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */
|
||||
#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */
|
||||
#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */
|
||||
#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */
|
||||
#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */
|
||||
|
||||
#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */
|
||||
#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */
|
||||
#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */
|
||||
#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */
|
||||
#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */
|
||||
#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */
|
||||
#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */
|
||||
#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET)
|
||||
#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET)
|
||||
#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET)
|
||||
#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET)
|
||||
#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET)
|
||||
#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET)
|
||||
#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET)
|
||||
#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET)
|
||||
#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET)
|
||||
#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET)
|
||||
#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET)
|
||||
#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET)
|
||||
#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET)
|
||||
#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET)
|
||||
#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET)
|
||||
#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET)
|
||||
#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET)
|
||||
#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET)
|
||||
#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET)
|
||||
#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET)
|
||||
#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET)
|
||||
#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET)
|
||||
#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET)
|
||||
#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET)
|
||||
#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET)
|
||||
#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET)
|
||||
#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET)
|
||||
#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET)
|
||||
#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET)
|
||||
#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET)
|
||||
#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET)
|
||||
#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET)
|
||||
#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET)
|
||||
#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET)
|
||||
#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET)
|
||||
#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET)
|
||||
#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET)
|
||||
#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET)
|
||||
#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET)
|
||||
#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET)
|
||||
#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET)
|
||||
#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET)
|
||||
#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET)
|
||||
#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET)
|
||||
#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET)
|
||||
#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET)
|
||||
#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET)
|
||||
#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET)
|
||||
#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET)
|
||||
#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET)
|
||||
#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET)
|
||||
#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET)
|
||||
#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET)
|
||||
#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET)
|
||||
#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET)
|
||||
#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET)
|
||||
#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET)
|
||||
#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET)
|
||||
#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET)
|
||||
#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET)
|
||||
#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET)
|
||||
#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET)
|
||||
#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET)
|
||||
#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET)
|
||||
#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET)
|
||||
#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET)
|
||||
#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET)
|
||||
#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET)
|
||||
#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET)
|
||||
#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET)
|
||||
#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET)
|
||||
#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET)
|
||||
#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET)
|
||||
#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET)
|
||||
#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET)
|
||||
#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET)
|
||||
#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET)
|
||||
#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET)
|
||||
#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET)
|
||||
#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET)
|
||||
#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET)
|
||||
#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET)
|
||||
#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET)
|
||||
#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET)
|
||||
#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET)
|
||||
#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET)
|
||||
#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET)
|
||||
#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET)
|
||||
#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET)
|
||||
#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET)
|
||||
#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_STREAM_MASK 0x3f
|
||||
#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */
|
||||
#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */
|
||||
#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */
|
||||
#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */
|
||||
#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */
|
||||
|
||||
/* DMA interrupt status register and interrupt flag clear register field defintions */
|
||||
|
||||
#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */
|
||||
#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT)
|
||||
#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */
|
||||
#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT)
|
||||
#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */
|
||||
#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT)
|
||||
#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */
|
||||
#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT)
|
||||
|
||||
#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */
|
||||
#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT)
|
||||
#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */
|
||||
#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT)
|
||||
#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */
|
||||
#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT)
|
||||
#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */
|
||||
#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT)
|
||||
|
||||
/* DMA stream configuration register */
|
||||
|
||||
#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */
|
||||
#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */
|
||||
#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */
|
||||
#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */
|
||||
#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */
|
||||
#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */
|
||||
#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */
|
||||
#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT)
|
||||
# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */
|
||||
# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */
|
||||
# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */
|
||||
#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */
|
||||
#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */
|
||||
#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */
|
||||
#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */
|
||||
#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT)
|
||||
# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */
|
||||
#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT)
|
||||
# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */
|
||||
#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */
|
||||
#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT)
|
||||
# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */
|
||||
# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */
|
||||
# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */
|
||||
# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */
|
||||
#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */
|
||||
#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */
|
||||
#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT)
|
||||
# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */
|
||||
# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */
|
||||
# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */
|
||||
# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */
|
||||
#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */
|
||||
#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT)
|
||||
# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */
|
||||
# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */
|
||||
# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */
|
||||
# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */
|
||||
#define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-27: Channel selection */
|
||||
#define DMA_SCR_CHSEL_MASK (7 << DMA_SCR_CHSEL_SHIFT)
|
||||
# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT)
|
||||
|
||||
#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE)
|
||||
|
||||
/* DMA stream number of data register */
|
||||
|
||||
#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA stream n FIFO control register */
|
||||
|
||||
#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */
|
||||
#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT)
|
||||
# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */
|
||||
# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */
|
||||
# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */
|
||||
# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */
|
||||
#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */
|
||||
#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */
|
||||
#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT)
|
||||
# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */
|
||||
# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */
|
||||
# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */
|
||||
# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */
|
||||
# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */
|
||||
# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */
|
||||
/* Bit 6: Reserved */
|
||||
#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DMA Stream mapping. Each DMA stream has a mapping to several possible
|
||||
* sources/sinks of data. The requests from peripherals assigned to a stream
|
||||
* are simply OR'ed together before entering the DMA block. This means that only
|
||||
* one request on a given stream can be enabled at once.
|
||||
*
|
||||
* Alternative stream selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* The DMA driver, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if
|
||||
* SPI3_RX connects via DMA STREAM0, then following should be application-specific
|
||||
* mapping should be used:
|
||||
*
|
||||
* #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1
|
||||
*/
|
||||
|
||||
#define STM32_DMA_MAP(d,s,c) ((d) << 6 | (s) << 3 | (c))
|
||||
#define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1)
|
||||
#define STM32_DMA_STREAM(m) (((m) >> 3) & 7)
|
||||
#define STM32_DMA_CHANNEL(m) ((m) & 7)
|
||||
|
||||
#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0)
|
||||
#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0)
|
||||
|
||||
#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1)
|
||||
#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1)
|
||||
#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1)
|
||||
|
||||
#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2)
|
||||
#define DMAMAP_I2S2_EXT_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2)
|
||||
#define DMAMAP_I2S2_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN2)
|
||||
#define DMAMAP_I2S3_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN2)
|
||||
|
||||
#define DMAMAP_I2S3_EXT_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_I2S2_EXT_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN3)
|
||||
#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3)
|
||||
|
||||
#define DMAMAP_UART5_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN4)
|
||||
#define DMAMAP_USART3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN4)
|
||||
#define DMAMAP_UART4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN4)
|
||||
#define DMAMAP_USART3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN4)
|
||||
#define DMAMAP_UART4_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN4)
|
||||
#define DMAMAP_USART2_RX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN4)
|
||||
#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4)
|
||||
#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4)
|
||||
|
||||
#define DMAMAP_UART8_TX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN5)
|
||||
#define DMAMAP_UART7_TX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_UART7_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5)
|
||||
#define DMAMAP_UART8_RX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5)
|
||||
|
||||
#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_TRIG_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_TRIG_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6)
|
||||
|
||||
#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7)
|
||||
#define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7)
|
||||
#define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7)
|
||||
|
||||
#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0)
|
||||
#define DMAMAP_TIM8_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_TIM8_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0)
|
||||
#define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0)
|
||||
#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0)
|
||||
#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0)
|
||||
|
||||
#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1)
|
||||
#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1)
|
||||
#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1)
|
||||
#define DMAMAP_SPI6_TX STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN1)
|
||||
#define DMAMAP_SPI6_RX STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN1)
|
||||
#define DMAMAP_DCMI_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN1)
|
||||
|
||||
#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2)
|
||||
#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2)
|
||||
#define DMAMAP_SPI5_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN2)
|
||||
#define DMAMAP_SPI5_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN2)
|
||||
#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2)
|
||||
#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2)
|
||||
#define DMAMAP_HASH_IN STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN2)
|
||||
|
||||
#define DMAMAP_SPI1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3)
|
||||
|
||||
#define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4)
|
||||
#define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4)
|
||||
#define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4)
|
||||
#define DMAMAP_SDIO_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4)
|
||||
#define DMAMAP_SDIO_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4)
|
||||
|
||||
#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5)
|
||||
#define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5)
|
||||
|
||||
#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6)
|
||||
|
||||
#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7)
|
||||
#define DMAMAP_SPI5_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7)
|
||||
#define DMAMAP_SPI5_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F427 || CONFIG_STM32_STM32F429 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_DMA_H */
|
||||
|
|
@ -1,865 +0,0 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f42xxx_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions. All members of the STM32F40xxx family share the same
|
||||
* pin multiplexing (although they may differ in the pins physically available).
|
||||
*
|
||||
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if
|
||||
* CAN1_RX connects vis PA11 on some board, then the following definitions should
|
||||
* appear inthe board.h header file for that board:
|
||||
*
|
||||
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
*
|
||||
* The driver will then automatically configure PA11 as the CAN1 RX pin.
|
||||
*/
|
||||
|
||||
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
|
||||
* Additional effort is required to select specific GPIO options such as frequency,
|
||||
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
|
||||
* pins in this file.
|
||||
*/
|
||||
|
||||
/* ADC */
|
||||
|
||||
#define GPIO_ADC1_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
|
||||
|
||||
#define GPIO_ADC2_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_ADC2_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC2_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC2_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC2_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_ADC2_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
|
||||
|
||||
#define GPIO_ADC3_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC3_IN4 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_ADC3_IN15 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN5)
|
||||
|
||||
/* CAN */
|
||||
|
||||
#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_CAN1_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_CAN1_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_CAN1_RX_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
|
||||
#define GPIO_CAN1_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_CAN1_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_CAN1_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_CAN1_TX_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
|
||||
|
||||
#define GPIO_CAN2_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_CAN2_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_CAN2_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_CAN2_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
|
||||
|
||||
/* DAC - "Once the DAC channelx is enabled, the corresponding GPIO pin
|
||||
* (PA4 or PA5) is automatically connected to the analog converter output
|
||||
* (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin
|
||||
* should first be configured to analog (AIN)".
|
||||
*/
|
||||
|
||||
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
|
||||
/* Digital Camera Interface (DCMI) */
|
||||
|
||||
#define GPIO_DCMI_D0_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D0_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D0_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D1_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_DCMI_D1_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_DCMI_D1_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN10)
|
||||
#define GPIO_DCMI_D2_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_DCMI_D2_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_DCMI_D2_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN11)
|
||||
#define GPIO_DCMI_D3_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D3_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_DCMI_D3_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN12)
|
||||
#define GPIO_DCMI_D4_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_DCMI_D4_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_DCMI_D4_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN14)
|
||||
#define GPIO_DCMI_D5_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D5_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN4)
|
||||
#define GPIO_DCMI_D6_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_DCMI_D6_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_DCMI_D6_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D7_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D7_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D7_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN7)
|
||||
#define GPIO_DCMI_D8_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_DCMI_D8_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_DCMI_D9_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_DCMI_D9_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN2)
|
||||
#define GPIO_DCMI_D10_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_DCMI_D10_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_DCMI_D11_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_DCMI_D11_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN15)
|
||||
#define GPIO_DCMI_D12 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_DCMI_D13_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_DCMI_D13_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_DCMI_HSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DCMI_HSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_DCMI_PIXCK (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_DCMI_VSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_DCMI_VSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN5)
|
||||
|
||||
/* Clocks outputs */
|
||||
|
||||
#define GPIO_MCO1 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_MCO2 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
|
||||
/* Ethernet MAC */
|
||||
|
||||
#define GPIO_ETH_MDC (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ETH_MII_COL_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ETH_MII_COL_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3)
|
||||
#define GPIO_ETH_MII_CRS_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ETH_MII_CRS_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2)
|
||||
#define GPIO_ETH_MII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ETH_MII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ETH_MII_RXD2_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ETH_MII_RXD2_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_ETH_MII_RXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_ETH_MII_RXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_ETH_MII_RX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ETH_MII_RX_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ETH_MII_RX_ER_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_ETH_MII_RX_ER_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10)
|
||||
#define GPIO_ETH_MII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_MII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_ETH_MII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_MII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_ETH_MII_TXD2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ETH_MII_TXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_ETH_MII_TXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_ETH_MII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ETH_MII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_RMII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_ETH_RMII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_RMII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_ETH_RMII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ETH_RMII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_ETH_RMII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
|
||||
|
||||
/* Flexible Static Memory Controller (FSMC) */
|
||||
|
||||
#define GPIO_FSMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_FSMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_FSMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_FSMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_FSMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_FSMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5)
|
||||
#define GPIO_FSMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12)
|
||||
#define GPIO_FSMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13)
|
||||
#define GPIO_FSMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_FSMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_FSMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0)
|
||||
#define GPIO_FSMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1)
|
||||
#define GPIO_FSMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2)
|
||||
#define GPIO_FSMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3)
|
||||
#define GPIO_FSMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_FSMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_FSMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_FSMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_FSMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_FSMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_FSMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_FSMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_FSMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_FSMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_FSMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_FSMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_FSMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_FSMC_CD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_FSMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_FSMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_FSMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_FSMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_FSMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_FSMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_FSMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_FSMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_FSMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_FSMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_FSMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_FSMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_FSMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_FSMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_FSMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_FSMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_FSMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_FSMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_FSMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
|
||||
#define GPIO_FSMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
|
||||
#define GPIO_FSMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
|
||||
#define GPIO_FSMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
|
||||
#define GPIO_FSMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
|
||||
#define GPIO_FSMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
|
||||
#define GPIO_FSMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
|
||||
#define GPIO_FSMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_FSMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_FSMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
|
||||
#define GPIO_FSMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_FSMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_FSMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
|
||||
#define GPIO_FSMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
|
||||
#define GPIO_FSMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
|
||||
#define GPIO_FSMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
|
||||
#define GPIO_FSMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_FSMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_FSMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_FSMC_NCE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FSMC_NCE4_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_FSMC_NCE4_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_FSMC_NE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FSMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_FSMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_FSMC_NIORD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_FSMC_NIOWR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_FSMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_FSMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_FSMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
|
||||
#define GPIO_FSMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F429
|
||||
# define GPIO_FSMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
|
||||
# define GPIO_FSMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
# define GPIO_FSMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
|
||||
# define GPIO_FSMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
# define GPIO_FSMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_FSMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
|
||||
# define GPIO_FSMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_FSMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
|
||||
# define GPIO_FSMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
|
||||
# define GPIO_FSMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
|
||||
# define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
# define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
|
||||
# define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
|
||||
# define GPIO_FSMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
# define GPIO_FSMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN5)
|
||||
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
|
||||
|
||||
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
|
||||
|
||||
/* I2S */
|
||||
|
||||
#define GPIO_I2S2_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2S2_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_I2S2_CK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_I2S2_CK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_I2S2_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_I2S2_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_I2S2_SD_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_I2S2_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2S2_WS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2S2_WS_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_I2S2_WS_6 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN6)
|
||||
|
||||
#define GPIO_I2S2EXT_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_I2S2EXT_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_I2S2EXT_SD_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTI|GPIO_PIN2)
|
||||
|
||||
#define GPIO_I2S3_CK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_I2S3_CK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_I2S3_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_I2S3_SD_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_I2S3_WS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_I2S3_WS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
#define GPIO_I2S3EXT_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_I2S3EXT_SD_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4)
|
||||
|
||||
#define GPIO_I2S_CKIN (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN9)
|
||||
|
||||
/* JTAG */
|
||||
|
||||
#define GPIO_JTCK_SWCLK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_JTDO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_JTMS_SWDIO (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
|
||||
#define GPIO_JTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
|
||||
|
||||
/* OTG FS/HS (VBUS PA9 is not an alternate configuration) */
|
||||
|
||||
#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTGFS_SCL (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_OTGFS_SDA (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
|
||||
#define GPIO_OTGHSFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_OTGHSFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_OTGHSFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
|
||||
|
||||
#define GPIO_OTGHS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_OTGHS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_OTGHS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTGHS_INTN_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_OTGFS_INTN_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_OTGHS_SCL (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_OTGHS_SDA (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
|
||||
|
||||
#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0)
|
||||
|
||||
/* RTC */
|
||||
|
||||
#define GPIO_RTC_50HZ (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN15)
|
||||
|
||||
/* SDIO */
|
||||
|
||||
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_SDIO_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_SDIO_D2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_SDIO_D3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SDIO_D4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SDIO_D5 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SDIO_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SDIO_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
|
||||
#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN2)
|
||||
#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
|
||||
#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
|
||||
#define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_SPI4_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_SPI4_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_SPI4_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_SPI4_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_SPI4_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
|
||||
#define GPIO_SPI5_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_SPI5_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_SPI5_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_SPI5_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_SPI5_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_SPI5_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN5)
|
||||
#define GPIO_SPI5_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_SPI5_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN6)
|
||||
|
||||
#define GPIO_SPI6_MISO (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_SPI6_MOSI (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_SPI6_NSS (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_SPI6_SCK (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN7)
|
||||
|
||||
#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
|
||||
|
||||
#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM3_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN2)
|
||||
|
||||
#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
|
||||
|
||||
#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN10)
|
||||
#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10)
|
||||
#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN11)
|
||||
#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11)
|
||||
#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN12)
|
||||
#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12)
|
||||
#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN10)
|
||||
|
||||
#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN4)
|
||||
#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH1N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13)
|
||||
#define GPIO_TIM8_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14)
|
||||
#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_TIM8_CH3N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15)
|
||||
#define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM8_CH3IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM8_CH3OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM8_CH4IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN2)
|
||||
#define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM8_CH4OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2)
|
||||
#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM8_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN3)
|
||||
|
||||
#define GPIO_TIM9_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM9_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TIM9_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM9_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TIM9_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM9_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_TIM9_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM9_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
|
||||
|
||||
#define GPIO_TIM10_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM10_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_TIM10_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM10_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
|
||||
|
||||
#define GPIO_TIM11_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM11_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_TIM11_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM11_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
|
||||
|
||||
#define GPIO_TIM12_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_TIM12_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM12_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_TIM12_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_TIM12_CH2IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN9)
|
||||
#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_TIM12_CH2OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
|
||||
|
||||
#define GPIO_TIM13_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM13_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_TIM13_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM13_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8)
|
||||
|
||||
#define GPIO_TIM14_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM14_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_TIM14_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM14_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
|
||||
|
||||
/* Trace */
|
||||
|
||||
#define GPIO_TRACECLK (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_TRACED0 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TRACED1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TRACED2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TRACED3 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_TRACESWO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
|
||||
|
||||
/* UARTs/USARTs */
|
||||
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
|
||||
|
||||
#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5)
|
||||
|
||||
#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8)
|
||||
|
||||
#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
|
||||
#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12)
|
||||
|
||||
#define GPIO_USART6_CK_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_USART6_CK_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_USART6_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_USART6_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_USART6_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_USART6_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
|
||||
|
||||
#define GPIO_UART7_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_UART7_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_UART7_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_UART7_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
|
||||
|
||||
#define GPIO_UART8_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_UART8_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
|
||||
|
||||
/* LCD-TFT Display Controller (LTDC) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
# define GPIO_LTDC_R0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2)
|
||||
# define GPIO_LTDC_R0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN15)
|
||||
# define GPIO_LTDC_R1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3)
|
||||
# define GPIO_LTDC_R1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN0)
|
||||
# define GPIO_LTDC_R2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_LTDC_R2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN8)
|
||||
# define GPIO_LTDC_R2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN1)
|
||||
# define GPIO_LTDC_R3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
//# define GPIO_LTDC_R3_ (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_LTDC_R3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
|
||||
# define GPIO_LTDC_R3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN2)
|
||||
# define GPIO_LTDC_R4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_LTDC_R4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10)
|
||||
# define GPIO_LTDC_R4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN3)
|
||||
# define GPIO_LTDC_R5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_LTDC_R5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11)
|
||||
# define GPIO_LTDC_R5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN4)
|
||||
# define GPIO_LTDC_R6_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
//# define GPIO_LTDC_R6_ (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_LTDC_R6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12)
|
||||
# define GPIO_LTDC_R6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN5)
|
||||
# define GPIO_LTDC_R7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
|
||||
# define GPIO_LTDC_R7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN15)
|
||||
# define GPIO_LTDC_R7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN6)
|
||||
|
||||
# define GPIO_LTDC_G0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
|
||||
# define GPIO_LTDC_G0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN7)
|
||||
# define GPIO_LTDC_G1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
|
||||
# define GPIO_LTDC_G1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN8)
|
||||
# define GPIO_LTDC_G2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_LTDC_G2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
|
||||
# define GPIO_LTDC_G2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN9)
|
||||
# define GPIO_LTDC_G3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
|
||||
//# define GPIO_LTDC_G3_ (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_LTDC_G3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14)
|
||||
# define GPIO_LTDC_G3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN10)
|
||||
# define GPIO_LTDC_G4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_LTDC_G4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN15)
|
||||
# define GPIO_LTDC_G4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN11)
|
||||
# define GPIO_LTDC_G5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_LTDC_G5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0)
|
||||
# define GPIO_LTDC_G5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN0)
|
||||
# define GPIO_LTDC_G6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_LTDC_G6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN1)
|
||||
# define GPIO_LTDC_G6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN1)
|
||||
# define GPIO_LTDC_G7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3)
|
||||
# define GPIO_LTDC_G7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2)
|
||||
# define GPIO_LTDC_G7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN2)
|
||||
|
||||
# define GPIO_LTDC_B0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4)
|
||||
# define GPIO_LTDC_B0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN12)
|
||||
# define GPIO_LTDC_B1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12)
|
||||
# define GPIO_LTDC_B1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN13)
|
||||
# define GPIO_LTDC_B2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
|
||||
# define GPIO_LTDC_B2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
|
||||
# define GPIO_LTDC_B2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN14)
|
||||
# define GPIO_LTDC_B3_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
|
||||
# define GPIO_LTDC_B3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_LTDC_B3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN15)
|
||||
# define GPIO_LTDC_B4_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12)
|
||||
# define GPIO_LTDC_B4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12)
|
||||
# define GPIO_LTDC_B4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN4)
|
||||
# define GPIO_LTDC_B4_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN3)
|
||||
# define GPIO_LTDC_B5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_LTDC_B5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5)
|
||||
# define GPIO_LTDC_B5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN4)
|
||||
# define GPIO_LTDC_B6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_LTDC_B6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6)
|
||||
# define GPIO_LTDC_B6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN5)
|
||||
# define GPIO_LTDC_B7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_LTDC_B7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7)
|
||||
# define GPIO_LTDC_B7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN6)
|
||||
|
||||
# define GPIO_LTDC_VSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_LTDC_VSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
|
||||
# define GPIO_LTDC_VSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN13)
|
||||
# define GPIO_LTDC_HSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_LTDC_HSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10)
|
||||
# define GPIO_LTDC_HSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN12)
|
||||
# define GPIO_LTDC_DE_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
|
||||
# define GPIO_LTDC_DE_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_LTDC_DE_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN7)
|
||||
# define GPIO_LTDC_CLK_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
|
||||
# define GPIO_LTDC_CLK_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_LTDC_CLK_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN14)
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F427 || CONFIG_STM32_STM32F429 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_PINMAP_H */
|
||||
|
|
@ -1,599 +0,0 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f42xxx_rcc.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_RCC_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x0004 /* PLL configuration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_CIR_OFFSET 0x000c /* Clock interrupt register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0010 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x0014 /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0018 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR_OFFSET 0x0020 /* APB1 Peripheral reset register */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0024 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0030 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x0034 /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0038 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR_OFFSET 0x0040 /* APB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0044 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2LPENR_OFFSET 0x0054 /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3LPENR_OFFSET 0x0058 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB2LPENR_OFFSET 0x0064 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0074 /* Control/status register */
|
||||
#define STM32_RCC_SSCGR_OFFSET 0x0080 /* Spread spectrum clock generation register */
|
||||
#define STM32_RCC_PLLI2SCFGR_OFFSET 0x0084 /* PLLI2S configuration register */
|
||||
#define STM32_RCC_PLLSAICFGR_OFFSET 0x0088 /* PLLSAI configuration register */
|
||||
#define STM32_RCC_DCKCFGR_OFFSET 0x008c /* Dedicated clocks configuration register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET)
|
||||
#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR)
|
||||
#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE+STM32_RCC_AHB3LPENR_OFFSET)
|
||||
#define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET)
|
||||
#define STM32_RCC_APB2LPENR (STM32_RCC_BASE+STM32_RCC_APB2LPENR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_SSCGR (STM32_RCC_BASE+STM32_RCC_SSCGR_OFFSET)
|
||||
#define STM32_RCC_PLLI2SCFGR (STM32_RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET)
|
||||
#define STM32_RCC_PLLSAICFGR (STM32_RCC_BASE+STM32_RCC_PLLSAICFGR_OFFSET)
|
||||
#define STM32_RCC_DCKCFGR (STM32_RCC_BASE+STM32_RCC_DCKCFGR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */
|
||||
#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */
|
||||
#define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */
|
||||
#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT)
|
||||
#define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed clock Calibration */
|
||||
#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT)
|
||||
#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */
|
||||
#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */
|
||||
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */
|
||||
#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */
|
||||
#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
|
||||
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
|
||||
#define RCC_CR_PLLI2SON (1 << 26) /* Bit 26: PLLI2S enable */
|
||||
#define RCC_CR_PLLI2SRDY (1 << 27) /* Bit 27: PLLI2S clock ready flag */
|
||||
#define RCC_CR_PLLSAION (1 << 28) /* Bit 28: PLLSAI enable */
|
||||
#define RCC_CR_PLLSAIRDY (1 << 29) /* Bit 29: PLLSAI clock ready flag */
|
||||
|
||||
/* PLL configuration register */
|
||||
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (0) /* Bits 0-5: Main PLL (PLL) and audio PLL (PLLI2S)
|
||||
* input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x3f << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT) /* n = 2..63 */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */
|
||||
#define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */
|
||||
#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT)
|
||||
# define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */
|
||||
# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */
|
||||
# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */
|
||||
# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */
|
||||
#define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S)
|
||||
* entry clock source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (0)
|
||||
# define RCC_PLLCFG_PLLSRC_HSE RCC_PLLCFG_PLLSRC
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (24) /* Bits 24-27: Main PLL (PLL) divider
|
||||
* (USB OTG FS, SDIO and RNG clocks) */
|
||||
#define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
# define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */
|
||||
|
||||
#define RCC_PLLCFG_RESET (0x24003010) /* PLLCFG reset value */
|
||||
|
||||
/* Clock configuration register */
|
||||
|
||||
#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */
|
||||
#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT)
|
||||
# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
|
||||
# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
|
||||
# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
|
||||
#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */
|
||||
#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT)
|
||||
# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
|
||||
#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
|
||||
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
|
||||
#define RCC_CFGR_PPRE1_SHIFT (10) /* Bits 10-12: APB Low speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
|
||||
# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
|
||||
#define RCC_CFGR_PPRE2_SHIFT (13) /* Bits 13-15: APB High speed prescaler (APB2) */
|
||||
#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT)
|
||||
# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
|
||||
#define RCC_CFGR_RTCPRE_SHIFT (16) /* Bits 16-20: APB High speed prescaler (APB2) */
|
||||
#define RCC_CFGR_RTCPRE_MASK (31 << RCC_CFGR_RTCPRE_SHIFT)
|
||||
# define RCC_CFGR_RTCPRE(n) ((n) << RCC_CFGR_RTCPRE_SHIFT) /* HSE/n, n=1..31 */
|
||||
#define RCC_CFGR_MCO1_SHIFT (21) /* Bits 21-22: Microcontroller Clock Output */
|
||||
#define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO1_SHIFT)
|
||||
# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 00: HSI clock selected */
|
||||
# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */
|
||||
# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */
|
||||
# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */
|
||||
#define RCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */
|
||||
#define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */
|
||||
#define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT)
|
||||
# define RCC_CFGR_MCO1PRE_NONE (0 << RCC_CFGR_MCO1PRE_SHIFT) /* 0xx: no division */
|
||||
# define RCC_CFGR_MCO1PRE_DIV2 (4 << RCC_CFGR_MCO1PRE_SHIFT) /* 100: division by 2 */
|
||||
# define RCC_CFGR_MCO1PRE_DIV3 (5 << RCC_CFGR_MCO1PRE_SHIFT) /* 101: division by 3 */
|
||||
# define RCC_CFGR_MCO1PRE_DIV4 (6 << RCC_CFGR_MCO1PRE_SHIFT) /* 110: division by 4 */
|
||||
# define RCC_CFGR_MCO1PRE_DIV5 (7 << RCC_CFGR_MCO1PRE_SHIFT) /* 111: division by 5 */
|
||||
#define RCC_CFGR_MCO2PRE_SHIFT (27) /* Bits 27-29: MCO2 prescaler */
|
||||
#define RCC_CFGR_MCO2PRE_MASK (7 << RCC_CFGR_MCO2PRE_SHIFT)
|
||||
# define RCC_CFGR_MCO2PRE_NONE (0 << RCC_CFGR_MCO2PRE_SHIFT) /* 0xx: no division */
|
||||
# define RCC_CFGR_MCO2PRE_DIV2 (4 << RCC_CFGR_MCO2PRE_SHIFT) /* 100: division by 2 */
|
||||
# define RCC_CFGR_MCO2PRE_DIV3 (5 << RCC_CFGR_MCO2PRE_SHIFT) /* 101: division by 3 */
|
||||
# define RCC_CFGR_MCO2PRE_DIV4 (6 << RCC_CFGR_MCO2PRE_SHIFT) /* 110: division by 4 */
|
||||
# define RCC_CFGR_MCO2PRE_DIV5 (7 << RCC_CFGR_MCO2PRE_SHIFT) /* 111: division by 5 */
|
||||
#define RCC_CFGR_MCO2_SHIFT (30) /* Bits 30-31: Microcontroller clock output 2 */
|
||||
#define RCC_CFGR_MCO2_MASK (3 << RCC_CFGR_MCO2_SHIFT)
|
||||
# define RCC_CFGR_MCO2_SYSCLK (0 << RCC_CFGR_MCO2_SHIFT) /* 00: System clock (SYSCLK) selected */
|
||||
# define RCC_CFGR_MCO2_PLLI2S (1 << RCC_CFGR_MCO2_SHIFT) /* 01: PLLI2S clock selected */
|
||||
# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 10: HSE oscillator clock selected */
|
||||
# define RCC_CFGR_MCO2_PLL (3 << RCC_CFGR_MCO2_SHIFT) /* 11: PLL clock selected */
|
||||
|
||||
/* Clock interrupt register */
|
||||
|
||||
#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */
|
||||
#define RCC_CIR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt flag */
|
||||
#define RCC_CIR_HSIRDYF (1 << 2) /* Bit 2: HSI Ready Interrupt flag */
|
||||
#define RCC_CIR_HSERDYF (1 << 3) /* Bit 3: HSE Ready Interrupt flag */
|
||||
#define RCC_CIR_PLLRDYF (1 << 4) /* Bit 4: PLL Ready Interrupt flag */
|
||||
#define RCC_CIR_PLLI2SRDYF (1 << 5) /* Bit 5: PLLI2S Ready Interrupt flag */
|
||||
#define RCC_CIR_CSSF (1 << 7) /* Bit 7: Clock Security System Interrupt flag */
|
||||
#define RCC_CIR_LSIRDYIE (1 << 8) /* Bit 8: LSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_LSERDYIE (1 << 9) /* Bit 9: LSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSIRDYIE (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSERDYIE (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_PLLRDYIE (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */
|
||||
#define RCC_CIR_PLLI2SRDYIE (1 << 13) /* Bit 13: PLLI2S Ready Interrupt enable */
|
||||
#define RCC_CIR_PLLSAIRDYIE (1 << 14) /* Bit 14: PLLSAI Ready Interrupt enable */
|
||||
#define RCC_CIR_LSIRDYC (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_LSERDYC (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSIRDYC (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSERDYC (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_PLLRDYC (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */
|
||||
#define RCC_CIR_PLLI2SRDYC (1 << 21) /* Bit 21: PLLI2S Ready Interrupt clear */
|
||||
#define RCC_CIR_PLLSAIRDYC (1 << 22) /* Bit 22: PLLSAI Ready Interrupt clear */
|
||||
#define RCC_CIR_CSSC (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */
|
||||
|
||||
/* AHB1 peripheral reset register */
|
||||
|
||||
#define RCC_AHB1RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
|
||||
#define RCC_AHB1RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
|
||||
#define RCC_AHB1RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
|
||||
#define RCC_AHB1RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */
|
||||
#define RCC_AHB1RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */
|
||||
#define RCC_AHB1RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */
|
||||
#define RCC_AHB1RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */
|
||||
#define RCC_AHB1RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */
|
||||
#define RCC_AHB1RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */
|
||||
#define RCC_AHB1RSTR_GPIOJRST (1 << 9) /* Bit 9: IO port J reset */
|
||||
#define RCC_AHB1RSTR_GPIOKRST (1 << 10) /* Bit 10: IO port K reset */
|
||||
#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12 CRC reset */
|
||||
#define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA1 reset */
|
||||
#define RCC_AHB1RSTR_DMA2RST (1 << 22) /* Bit 22: DMA2 reset */
|
||||
#define RCC_AHB1RSTR_DMA2DRST (1 << 23) /* Bit 23: DMA2D reset */
|
||||
#define RCC_AHB1RSTR_ETHMACRST (1 << 25) /* Bit 25: Ethernet MAC reset */
|
||||
#define RCC_AHB1RSTR_OTGHSRST (1 << 29) /* Bit 29: USB OTG HS module reset */
|
||||
|
||||
/* AHB2 peripheral reset register */
|
||||
|
||||
#define RCC_AHB2RSTR_DCMIRST (1 << 0) /* Bit 0: Camera interface reset */
|
||||
#define RCC_AHB2RSTR_CRYPRST (1 << 4) /* Bit 4: Cryptographic module reset */
|
||||
#define RCC_AHB2RSTR_HASHRST (1 << 5) /* Bit 5: Hash module reset */
|
||||
#define RCC_AHB2RSTR_RNGRST (1 << 6) /* Bit 6: Random number generator module reset */
|
||||
#define RCC_AHB2RSTR_OTGFSRST (1 << 7) /* Bit 7: USB OTG FS module reset */
|
||||
|
||||
/* AHB3 peripheral reset register */
|
||||
|
||||
#define RCC_AHB3RSTR_FSMCRST (1 << 0) /* Bit 0: Flexible static memory controller module reset */
|
||||
|
||||
/* APB1 Peripheral reset register */
|
||||
|
||||
#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */
|
||||
#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */
|
||||
#define RCC_APB1RSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */
|
||||
#define RCC_APB1RSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */
|
||||
#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */
|
||||
#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */
|
||||
#define RCC_APB1RSTR_TIM12RST (1 << 6) /* Bit 6: TIM12 reset */
|
||||
#define RCC_APB1RSTR_TIM13RST (1 << 7) /* Bit 7: TIM13 reset */
|
||||
#define RCC_APB1RSTR_TIM14RST (1 << 8) /* Bit 8: TIM14 reset */
|
||||
#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window watchdog reset */
|
||||
#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
|
||||
#define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI 3 reset */
|
||||
#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
|
||||
#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
|
||||
#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: USART 4 reset */
|
||||
#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: USART 5 reset */
|
||||
#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */
|
||||
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
|
||||
#define RCC_APB1RSTR_I2C3RST (1 << 23) /* Bit 23: I2C3 reset */
|
||||
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */
|
||||
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* Bit 26: CAN2 reset */
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
|
||||
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC reset */
|
||||
#define RCC_APB1RSTR_UART7RST (1 << 30) /* Bit 30: USART 7 reset */
|
||||
#define RCC_APB1RSTR_UART8RST (1 << 31) /* Bit 31: USART 8 reset */
|
||||
|
||||
/* APB2 Peripheral reset register */
|
||||
|
||||
#define RCC_APB2RSTR_TIM1RST (1 << 0) /* Bit 0: TIM1 reset */
|
||||
#define RCC_APB2RSTR_TIM8RST (1 << 1) /* Bit 1: TIM8 reset */
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 4) /* Bit 4: USART1 reset */
|
||||
#define RCC_APB2RSTR_USART6RST (1 << 5) /* Bit 5: USART6 reset */
|
||||
#define RCC_APB2RSTR_ADCRST (1 << 8) /* Bit 8: ADC interface reset (common to all ADCs) */
|
||||
#define RCC_APB2RSTR_SDIORST (1 << 11) /* Bit 11: SDIO reset */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */
|
||||
#define RCC_APB2RSTR_SPI4RST (1 << 13) /* Bit 13: SPI4 reset */
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 14) /* Bit 14: System configuration controller reset */
|
||||
#define RCC_APB2RSTR_TIM9RST (1 << 16) /* Bit 16: TIM9 reset */
|
||||
#define RCC_APB2RSTR_TIM10RST (1 << 17) /* Bit 17: TIM10 reset */
|
||||
#define RCC_APB2RSTR_TIM11RST (1 << 18) /* Bit 18: TIM11 reset */
|
||||
#define RCC_APB2RSTR_SPI5RST (1 << 20) /* Bit 20: SPI 5 reset */
|
||||
#define RCC_APB2RSTR_SPI6RST (1 << 21) /* Bit 21: SPI 6 reset */
|
||||
#define RCC_APB2RSTR_SAI1RST (1 << 22) /* Bit 22: SAI 1 reset */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
# define RCC_APB2RSTR_LTDCRST (1 << 26) /* Bit 26: LTDC reset */
|
||||
#endif
|
||||
|
||||
/* AHB1 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB1ENR_GPIOEN(n) (1 << (n))
|
||||
#define RCC_AHB1ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */
|
||||
#define RCC_AHB1ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */
|
||||
#define RCC_AHB1ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */
|
||||
#define RCC_AHB1ENR_GPIODEN (1 << 3) /* Bit 3: IO port D clock enable */
|
||||
#define RCC_AHB1ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E clock enable */
|
||||
#define RCC_AHB1ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */
|
||||
#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */
|
||||
#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */
|
||||
#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
|
||||
#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
|
||||
#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
|
||||
#define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */
|
||||
#define RCC_AHB1ENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */
|
||||
#define RCC_AHB1ENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */
|
||||
#define RCC_AHB1ENR_DMA2DEN (1 << 23) /* Bit 23: DMA2D clock enable */
|
||||
#define RCC_AHB1ENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */
|
||||
#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable */
|
||||
#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) /* Bit 27: Ethernet Reception clock enable */
|
||||
#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable */
|
||||
#define RCC_AHB1ENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */
|
||||
#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */
|
||||
|
||||
/* AHB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB2ENR_DCMIEN (1 << 0) /* Bit 0: Camera interface enable */
|
||||
#define RCC_AHB2ENR_CRYPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable */
|
||||
#define RCC_AHB2ENR_HASHEN (1 << 5) /* Bit 5: Hash modules clock enable */
|
||||
#define RCC_AHB2ENR_RNGEN (1 << 6) /* Bit 6: Random number generator clock enable */
|
||||
#define RCC_AHB2ENR_OTGFSEN (1 << 7) /* Bit 7: USB OTG FS clock enable */
|
||||
|
||||
/* AHB3 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */
|
||||
|
||||
/* APB1 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: TIM2 clock enable */
|
||||
#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: TIM3 clock enable */
|
||||
#define RCC_APB1ENR_TIM4EN (1 << 2) /* Bit 2: TIM4 clock enable */
|
||||
#define RCC_APB1ENR_TIM5EN (1 << 3) /* Bit 3: TIM5 clock enable */
|
||||
#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: TIM6 clock enable */
|
||||
#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: TIM7 clock enable */
|
||||
#define RCC_APB1ENR_TIM12EN (1 << 6) /* Bit 6: TIM12 clock enable */
|
||||
#define RCC_APB1ENR_TIM13EN (1 << 7) /* Bit 7: TIM13 clock enable */
|
||||
#define RCC_APB1ENR_TIM14EN (1 << 8) /* Bit 8: TIM14 clock enable */
|
||||
#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */
|
||||
#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
|
||||
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART3 clock enable */
|
||||
#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART4 clock enable */
|
||||
#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART5 clock enable */
|
||||
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */
|
||||
#define RCC_APB1ENR_I2C3EN (1 << 23) /* Bit 23: I2C3 clock enable */
|
||||
#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN 1 clock enable */
|
||||
#define RCC_APB1ENR_CAN2EN (1 << 26) /* Bit 26: CAN 2 clock enable */
|
||||
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
|
||||
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
|
||||
#define RCC_APB1ENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */
|
||||
#define RCC_APB1ENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */
|
||||
|
||||
/* APB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: TIM1 clock enable */
|
||||
#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: TIM8 clock enable */
|
||||
#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: USART1 clock enable */
|
||||
#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: USART6 clock enable */
|
||||
#define RCC_APB2ENR_ADC1EN (1 << 8) /* Bit 8: ADC1 clock enable */
|
||||
#define RCC_APB2ENR_ADC2EN (1 << 9) /* Bit 9: ADC2 clock enable */
|
||||
#define RCC_APB2ENR_ADC3EN (1 << 10) /* Bit 10: ADC3 clock enable */
|
||||
#define RCC_APB2ENR_SDIOEN (1 << 11) /* Bit 11: SDIO clock enable */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */
|
||||
#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: SPI4 clock enable */
|
||||
#define RCC_APB2ENR_SYSCFGEN (1 << 14) /* Bit 14: System configuration controller clock enable */
|
||||
#define RCC_APB2ENR_TIM9EN (1 << 16) /* Bit 16: TIM9 clock enable */
|
||||
#define RCC_APB2ENR_TIM10EN (1 << 17) /* Bit 17: TIM10 clock enable */
|
||||
#define RCC_APB2ENR_TIM11EN (1 << 18) /* Bit 18: TIM11 clock enable */
|
||||
#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: SPI5 clock enable */
|
||||
#define RCC_APB2ENR_SPI6EN (1 << 21) /* Bit 21: SPI6 clock enable */
|
||||
#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: SAI1 clock enable */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
# define RCC_APB2ENR_LTDCEN (1 << 26) /* Bit 26: LTDC clock enable */
|
||||
#endif
|
||||
|
||||
/* RCC AHB1 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB1LPENR_GPIOLPEN(n) (1 << (n))
|
||||
#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_SRAM3LPEN (1 << 19) /* Bit 19: SRAM 3 interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_CCMDATARAMLPEN (1 << 20) /* Bit 20: CCM data RAM clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_DMA2DLPEN (1 << 23) /* Bit 23: DMA2D clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */
|
||||
|
||||
/* RCC AHB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB2LPENR_DCMILPEN (1 << 0) /* Bit 0: Camera interface enable during Sleep mode */
|
||||
#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable during Sleep mode */
|
||||
#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* Bit 5: Hash modules clock enable during Sleep mode */
|
||||
#define RCC_AHB2LPENR_RNGLPEN (1 << 6) /* Bit 6: Random number generator clock enable during Sleep mode */
|
||||
#define RCC_AHB2LPENR_OTGFLPSEN (1 << 7) /* Bit 7: USB OTG FS clock enable during Sleep mode */
|
||||
|
||||
/* RCC AHB3 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB3LPENR_FSMLPEN (1 << 0) /* Bit 0: Flexible static memory controller module clock
|
||||
* enable during Sleep mode */
|
||||
|
||||
/* RCC APB1 low power modeperipheral clock enable register */
|
||||
|
||||
#define RCC_APB1LPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM3 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM4 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM5 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM6 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM7 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_WWDGLPEN (1 << 11) /* Bit 11: Window watchdog clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI3 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_USART2LPEN (1 << 17) /* Bit 17: USART 2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_USART3LPEN (1 << 18) /* Bit 18: USART3 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_UART4LPEN (1 << 19) /* Bit 19: UART4 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_UART5LPEN (1 << 20) /* Bit 20: UART5 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C1 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_I2C3LPEN (1 << 23) /* Bit 23: I2C3 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_CAN1LPEN (1 << 25) /* Bit 25: CAN 1 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_CAN2LPEN (1 << 26) /* Bit 26: CAN 2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_PWRLPEN (1 << 28) /* Bit 28: Power interface clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_DACLPEN (1 << 29) /* Bit 29: DAC interface clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_UART7LPEN (1 << 30) /* Bit 30: UART7 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_UART8LPEN (1 << 31) /* Bit 31: UART8 clock enable during Sleep mode */
|
||||
|
||||
/* RCC APB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* Bit 0: TIM1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* Bit 1: TIM8 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* Bit 4: USART1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* Bit 5: USART6 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_ADC1LPEN (1 << 8) /* Bit 8: ADC1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_ADC2LPEN (1 << 9) /* Bit 9: ADC2 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_ADC3LPEN (1 << 10) /* Bit 10: ADC3 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SDIOLPEN (1 << 11) /* Bit 11: SDIO clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI4 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) /* Bit 14: System configuration controller clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM9LPEN (1 << 16) /* Bit 16: TIM9 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM10LPEN (1 << 17) /* Bit 17: TIM10 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM11LPEN (1 << 18) /* Bit 18: TIM11 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* Bit 20: SPI5 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SPI6LPEN (1 << 21) /* Bit 21: SPI6 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* Bit 22: SAI1 clock enable during Sleep mode */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
# define RCC_APB2LPENR_LTDCLPEN (1 << 26) /* Bit 26: LTDC clock enable during Sleep mode */
|
||||
#endif
|
||||
|
||||
/* Backup domain control register */
|
||||
|
||||
#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */
|
||||
#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */
|
||||
#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
|
||||
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
|
||||
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */
|
||||
#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */
|
||||
#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */
|
||||
|
||||
/* Control/status register */
|
||||
|
||||
#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */
|
||||
#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */
|
||||
#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */
|
||||
#define RCC_CSR_BORRSTF (1 << 25) /* Bit 25: BOR reset flag */
|
||||
#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */
|
||||
#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */
|
||||
#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */
|
||||
#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */
|
||||
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */
|
||||
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */
|
||||
|
||||
/* Spread spectrum clock generation register */
|
||||
|
||||
#define RCC_SSCGR_MODPER_SHIFT (0) /* Bit 0-12: Modulation period */
|
||||
#define RCC_SSCGR_MODPER_MASK (0x1fff << RCC_SSCGR_MODPER_SHIFT)
|
||||
# define RCC_SSCGR_MODPER(n) ((n) << RCC_SSCGR_MODPER_SHIFT)
|
||||
#define RCC_SSCGR_INCSTEP_SHIFT (13) /* Bit 13-27: Incrementation step */
|
||||
#define RCC_SSCGR_INCSTEP_MASK (0x7fff << RCC_SSCGR_INCSTEP_SHIFT)
|
||||
# define RCC_SSCGR_INCSTEP(n) ((n) << RCC_SSCGR_INCSTEP_SHIFT)
|
||||
#define RCC_SSCGR_SPREADSEL (1 << 30) /* Bit 30: Spread Select */
|
||||
#define RCC_SSCGR_SSCGEN (1 << 31) /* Bit 31: Spread spectrum modulation enable */
|
||||
|
||||
/* PLLI2S configuration register */
|
||||
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT (6) /* Bits 6-14: PLLI2S multiplication factor for VCO */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
|
||||
#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
|
||||
|
||||
/* PLLSAI configuration register */
|
||||
|
||||
#define RCC_PLLSAICFGR_PLLSAIN_SHIFT (6) /* Bits 6-14: PLLSAI divider (N) for VCO */
|
||||
#define RCC_PLLSAICFGR_PLLSAIN_MASK (0x1ff << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
|
||||
#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */
|
||||
#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
|
||||
#define RCC_PLLSAICFGR_PLLSAIR_SHIFT (28) /* Bits 28-30: PLLSAI division factor for LCD clock */
|
||||
#define RCC_PLLSAICFGR_PLLSAIR_MASK (7 << RCC_PLLSAICFGR_PLLSAIR_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIR(n) ((n) << RCC_PLLSAICFGR_PLLSAIR_SHIFT)
|
||||
|
||||
/* Dedicated clocks configuration register */
|
||||
|
||||
#define RCC_DCKCFGR_PLLI2SDIVQ_SHIFT (0) /* Bits 0-4: PLLI2S division factor for I2S clock */
|
||||
#define RCC_DCKCFGR_PLLI2SDIVQ_MASK (0x1F << RCC_DCKCFGR_PLLI2SDIVQ_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLI2SDIVQ(n) ((n) << RCC_DCKCFGR_PLLI2SDIVQ_SHIFT)
|
||||
#define RCC_DCKCFGR_PLLSAIDIVQ_SHIFT (8) /* Bits 8-12: PLLSAI division factor for SAI clock */
|
||||
#define RCC_DCKCFGR_PLLSAIDIVQ_MASK (0x1F << RCC_DCKCFGR_PLLSAIDIVQ_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVQ(n) ((n) << RCC_DCKCFGR_PLLSAIDIVQ_SHIFT)
|
||||
#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT (16) /* Bits 16-17: PLLSAI division factor for LCD_CLK clock */
|
||||
#define RCC_DCKCFGR_PLLSAIDIVR_MASK (0x3 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVR(n) ((n) << RCC_DCKCFGR_PLLSAIDIVR_SHIFT)
|
||||
#define RCC_DCKCFGR_SAI1ASRC_SHIFT (20) /* Bits 20-21: SAI1-A clock source selection */
|
||||
#define RCC_DCKCFGR_SAI1ASRC_MASK (0x3 << RCC_DCKCFGR_SAI1ASRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1ASRC(n) ((n) << RCC_DCKCFGR_SAI1ASRC_SHIFT)
|
||||
#define RCC_DCKCFGR_SAI1BSRC_SHIFT (22) /* Bits 22-23: SAI1-B clock source selection */
|
||||
#define RCC_DCKCFGR_SAI1BSRC_MASK (0x3 << RCC_DCKCFGR_SAI1BSRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1BSRC(n) ((n) << RCC_DCKCFGR_SAI1BSRC_SHIFT)
|
||||
#define RCC_DCKCFGR_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */
|
||||
|
||||
#define RCC_SAICLKSRC_PLLSAI 0
|
||||
#define RCC_SAICLKSRC_PLLI2S 1
|
||||
#define RCC_SAICLKSRC_ALTERNATE 2
|
||||
|
||||
#define RCC_PLLSAIDIVR_DIV2 0
|
||||
#define RCC_PLLSAIDIVR_DIV4 1
|
||||
#define RCC_PLLSAIDIVR_DIV8 2
|
||||
#define RCC_PLLSAIDIVR_DIV16 3
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F427 || CONFIG_STM32_STM32F429 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_RCC_H */
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f42xxx_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
|
||||
#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
|
||||
#define SYSCFG_MEMRMP_MASK (3 << SYSCFG_MEMRMP_SHIFT)
|
||||
# define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 00: Main Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 01: System Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_FSMC (2 << SYSCFG_MEMRMP_SHIFT) /* 10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 11: Embedded SRAM (112kB) mapped at 0x0000 0000 */
|
||||
|
||||
/* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define SYSCFG_PMC_MII_RMII_SEL (1 << 23) /* Bit 23: Ethernet PHY interface selection */
|
||||
#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* Compensation cell control register */
|
||||
|
||||
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
|
||||
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F427 || CONFIG_STM32_STM32F429 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F42XXX_SYSCFG_H */
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f42xxx_vectors.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
|
||||
* supplies ach STM32F40xxx vector in terms of a (lower-case) ISR label and an
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f40xxx_irq.h.
|
||||
* stm32_vectors.S will define the VECTOR macro in different ways in order to generate
|
||||
* the interrupt vectors and handlers in their final form.
|
||||
*/
|
||||
|
||||
/* If the common ARMv7-M vector handling is used, then all it needs is the following
|
||||
* definition that provides the number of supported vectors.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARMV7M_CMNVECTOR
|
||||
|
||||
/* Reserve interrupt table entries for I/O interrupts. */
|
||||
|
||||
# if defined(CONFIG_STM32_STM32F427)
|
||||
# define ARMV7M_PERIPHERAL_INTERRUPTS 87
|
||||
# else /* if defined(CONFIG_STM32_STM32F429) */
|
||||
# define ARMV7M_PERIPHERAL_INTERRUPTS 91
|
||||
# endif
|
||||
|
||||
#else
|
||||
|
||||
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */
|
||||
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */
|
||||
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper and time stamp interrupts */
|
||||
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* Vector 16+3: RTC global interrupt */
|
||||
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */
|
||||
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */
|
||||
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */
|
||||
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */
|
||||
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */
|
||||
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */
|
||||
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */
|
||||
VECTOR(stm32_dma1s0, STM32_IRQ_DMA1S0) /* Vector 16+11: DMA1 Stream 0 global interrupt */
|
||||
VECTOR(stm32_dma1s1, STM32_IRQ_DMA1S1) /* Vector 16+12: DMA1 Stream 1 global interrupt */
|
||||
VECTOR(stm32_dma1s2, STM32_IRQ_DMA1S2) /* Vector 16+13: DMA1 Stream 2 global interrupt */
|
||||
VECTOR(stm32_dma1s3, STM32_IRQ_DMA1S3) /* Vector 16+14: DMA1 Stream 3 global interrupt */
|
||||
VECTOR(stm32_dma1s4, STM32_IRQ_DMA1S4) /* Vector 16+15: DMA1 Stream 4 global interrupt */
|
||||
VECTOR(stm32_dma1s5, STM32_IRQ_DMA1S5) /* Vector 16+16: DMA1 Stream 5 global interrupt */
|
||||
VECTOR(stm32_dma1s6, STM32_IRQ_DMA1S6) /* Vector 16+17: DMA1 Stream 6 global interrupt */
|
||||
VECTOR(stm32_adc, STM32_IRQ_ADC) /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */
|
||||
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* Vector 16+19: CAN1 TX interrupts */
|
||||
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* Vector 16+20: CAN1 RX0 interrupts */
|
||||
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */
|
||||
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */
|
||||
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */
|
||||
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */
|
||||
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */
|
||||
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */
|
||||
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */
|
||||
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */
|
||||
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */
|
||||
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */
|
||||
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */
|
||||
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */
|
||||
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */
|
||||
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */
|
||||
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */
|
||||
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */
|
||||
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */
|
||||
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */
|
||||
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */
|
||||
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */
|
||||
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* Vector 16+41: RTC alarm through EXTI line interrupt */
|
||||
VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP) /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
|
||||
VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */
|
||||
VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* Vector 16+44: TIM8 Update interrupt/TIM13 global interrupt */
|
||||
VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */
|
||||
VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* Vector 16+46: TIM8 Capture Compare interrupt */
|
||||
VECTOR(stm32_dma1s7, STM32_IRQ_DMA1S7) /* Vector 16+47: DMA1 Stream 7 global interrupt */
|
||||
VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */
|
||||
VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* Vector 16+49: SDIO global interrupt */
|
||||
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */
|
||||
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */
|
||||
VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */
|
||||
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */
|
||||
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */
|
||||
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */
|
||||
VECTOR(stm32_dma2s0, STM32_IRQ_DMA2S0) /* Vector 16+56: DMA2 Stream 0 global interrupt */
|
||||
VECTOR(stm32_dma2s1, STM32_IRQ_DMA2S1) /* Vector 16+57: DMA2 Stream 1 global interrupt */
|
||||
VECTOR(stm32_dma2s2, STM32_IRQ_DMA2S2) /* Vector 16+58: DMA2 Stream 2 global interrupt */
|
||||
VECTOR(stm32_dma2s3, STM32_IRQ_DMA2S3) /* Vector 16+59: DMA2 Stream 3 global interrupt */
|
||||
VECTOR(stm32_dma2s4, STM32_IRQ_DMA2S4) /* Vector 16+60: DMA2 Stream 4 global interrupt */
|
||||
VECTOR(stm32_eth, STM32_IRQ_ETH) /* Vector 16+61: Ethernet global interrupt */
|
||||
VECTOR(stm32_ethwkup, STM32_IRQ_ETHWKUP) /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
|
||||
VECTOR(stm32_can2tx, STM32_IRQ_CAN2TX) /* Vector 16+63: CAN2 TX interrupts */
|
||||
VECTOR(stm32_can2rx0, STM32_IRQ_CAN2RX0) /* Vector 16+64: CAN2 RX0 interrupts */
|
||||
VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 interrupt */
|
||||
VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE interrupt */
|
||||
VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */
|
||||
VECTOR(stm32_dma2s5, STM32_IRQ_DMA2S5) /* Vector 16+68: DMA2 Stream 5 global interrupt */
|
||||
VECTOR(stm32_dma2s6, STM32_IRQ_DMA2S6) /* Vector 16+69: DMA2 Stream 6 global interrupt */
|
||||
VECTOR(stm32_dma2s7, STM32_IRQ_DMA2S7) /* Vector 16+70: DMA2 Stream 7 global interrupt */
|
||||
VECTOR(stm32_usart6, STM32_IRQ_USART6) /* Vector 16+71: USART6 global interrupt */
|
||||
VECTOR(stm32_i2c3ev, STM32_IRQ_I2C3EV) /* Vector 16+72: I2C3 event interrupt */
|
||||
VECTOR(stm32_i2c3er, STM32_IRQ_I2C3ER) /* Vector 16+73: I2C3 error interrupt */
|
||||
VECTOR(stm32_otghsep1out, STM32_IRQ_OTGHSEP1OUT) /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
VECTOR(stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN) /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */
|
||||
VECTOR(stm32_otghswkup, STM32_IRQ_OTGHSWKUP) /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
VECTOR(stm32_otghs, STM32_IRQ_OTGHS) /* Vector 16+77: USB On The Go HS global interrupt */
|
||||
VECTOR(stm32_dcmi, STM32_IRQ_DCMI) /* Vector 16+78: DCMI global interrupt */
|
||||
VECTOR(stm32_cryp, STM32_IRQ_CRYP) /* Vector 16+79: CRYP crypto global interrupt */
|
||||
VECTOR(stm32_hash, STM32_IRQ_HASH) /* Vector 16+80: Hash and Rng global interrupt */
|
||||
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* Vector 16+81: FPU global interrupt */
|
||||
VECTOR(stm32_uart7, STM32_IRQ_UART7) /* Vector 16+82: UART7 interrupt */
|
||||
VECTOR(stm32_uart8, STM32_IRQ_UART8) /* Vector 16+83: UART8 interrupt */
|
||||
VECTOR(stm32_spi4, STM32_IRQ_SPI4) /* Vector 16+84: SPI4 interrupt */
|
||||
VECTOR(stm32_spi5, STM32_IRQ_SPI5) /* Vector 16+85: SPI5 interrupt */
|
||||
VECTOR(stm32_spi6, STM32_IRQ_SPI6) /* Vector 16+86: SPI6 interrupt */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
VECTOR(stm32_sai1, STM32_IRQ_SAI1) /* Vector 16+87: SAI1 interrupt */
|
||||
VECTOR(stm32_ltdcint, STM32_IRQ_LTDCINT) /* Vector 16+88: LTDC interrupt */
|
||||
VECTOR(stm32_ltdcerrint, STM32_IRQ_LTDCERRINT) /* Vector 16+89: LTDC Error interrupt */
|
||||
VECTOR(stm32_dma2d, STM32_IRQ_DMA2D) /* Vector 16+90: DMA2D interrupt */
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_ARMV7M_CMNVECTOR */
|
||||
|
|
@ -1,535 +0,0 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f42xxx_dma.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* 2 DMA controllers */
|
||||
|
||||
#define DMA1 (0)
|
||||
#define DMA2 (1)
|
||||
|
||||
/* 8 DMA streams */
|
||||
|
||||
#define DMA_STREAM0 (0)
|
||||
#define DMA_STREAM1 (1)
|
||||
#define DMA_STREAM2 (2)
|
||||
#define DMA_STREAM3 (3)
|
||||
#define DMA_STREAM4 (4)
|
||||
#define DMA_STREAM5 (5)
|
||||
#define DMA_STREAM6 (6)
|
||||
#define DMA_STREAM7 (7)
|
||||
|
||||
/* 8 DMA channels */
|
||||
|
||||
#define DMA_CHAN0 (0)
|
||||
#define DMA_CHAN1 (1)
|
||||
#define DMA_CHAN2 (2)
|
||||
#define DMA_CHAN3 (3)
|
||||
#define DMA_CHAN4 (4)
|
||||
#define DMA_CHAN5 (5)
|
||||
#define DMA_CHAN6 (6)
|
||||
#define DMA_CHAN7 (7)
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */
|
||||
#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */
|
||||
#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */
|
||||
#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */
|
||||
|
||||
#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n))
|
||||
#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */
|
||||
#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */
|
||||
#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */
|
||||
#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */
|
||||
#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */
|
||||
#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */
|
||||
|
||||
#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */
|
||||
#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */
|
||||
#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */
|
||||
#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */
|
||||
#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */
|
||||
#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */
|
||||
#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */
|
||||
#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */
|
||||
|
||||
#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */
|
||||
#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */
|
||||
#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */
|
||||
#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */
|
||||
#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */
|
||||
#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */
|
||||
#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */
|
||||
#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */
|
||||
|
||||
#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */
|
||||
#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */
|
||||
#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */
|
||||
#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */
|
||||
#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */
|
||||
#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */
|
||||
#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */
|
||||
#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */
|
||||
|
||||
#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */
|
||||
#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */
|
||||
#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */
|
||||
#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */
|
||||
#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */
|
||||
#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */
|
||||
#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */
|
||||
#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */
|
||||
|
||||
#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */
|
||||
#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */
|
||||
#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */
|
||||
#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */
|
||||
#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */
|
||||
#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */
|
||||
#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */
|
||||
#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */
|
||||
|
||||
#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */
|
||||
#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */
|
||||
#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */
|
||||
#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */
|
||||
#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */
|
||||
#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */
|
||||
#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */
|
||||
#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET)
|
||||
#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET)
|
||||
#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET)
|
||||
#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET)
|
||||
#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET)
|
||||
#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET)
|
||||
#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET)
|
||||
#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET)
|
||||
#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET)
|
||||
#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET)
|
||||
#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET)
|
||||
#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET)
|
||||
#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET)
|
||||
#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET)
|
||||
#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET)
|
||||
#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET)
|
||||
#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET)
|
||||
#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET)
|
||||
#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET)
|
||||
#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET)
|
||||
#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET)
|
||||
#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET)
|
||||
#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET)
|
||||
#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET)
|
||||
#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET)
|
||||
#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET)
|
||||
#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET)
|
||||
#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET)
|
||||
#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET)
|
||||
#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET)
|
||||
#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET)
|
||||
#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET)
|
||||
#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET)
|
||||
#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET)
|
||||
#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET)
|
||||
#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET)
|
||||
#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET)
|
||||
#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET)
|
||||
#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET)
|
||||
#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET)
|
||||
#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET)
|
||||
#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET)
|
||||
#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET)
|
||||
#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET)
|
||||
#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET)
|
||||
#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET)
|
||||
#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET)
|
||||
#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET)
|
||||
#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET)
|
||||
#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET)
|
||||
#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET)
|
||||
#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET)
|
||||
#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET)
|
||||
#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET)
|
||||
#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET)
|
||||
#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET)
|
||||
#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET)
|
||||
#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET)
|
||||
#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET)
|
||||
#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET)
|
||||
#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET)
|
||||
#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET)
|
||||
#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET)
|
||||
#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET)
|
||||
#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET)
|
||||
#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET)
|
||||
#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET)
|
||||
#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET)
|
||||
#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET)
|
||||
#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET)
|
||||
#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET)
|
||||
#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET)
|
||||
#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET)
|
||||
#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET)
|
||||
#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET)
|
||||
#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET)
|
||||
#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET)
|
||||
#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET)
|
||||
#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET)
|
||||
#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET)
|
||||
#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET)
|
||||
#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET)
|
||||
#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET)
|
||||
#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET)
|
||||
#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET)
|
||||
#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET)
|
||||
#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET)
|
||||
#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET)
|
||||
#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET)
|
||||
#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET)
|
||||
#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_STREAM_MASK 0x3f
|
||||
#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */
|
||||
#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */
|
||||
#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */
|
||||
#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */
|
||||
#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */
|
||||
|
||||
/* DMA interrupt status register and interrupt flag clear register field defintions */
|
||||
|
||||
#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */
|
||||
#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT)
|
||||
#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */
|
||||
#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT)
|
||||
#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */
|
||||
#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT)
|
||||
#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */
|
||||
#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT)
|
||||
|
||||
#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */
|
||||
#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT)
|
||||
#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */
|
||||
#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT)
|
||||
#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */
|
||||
#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT)
|
||||
#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */
|
||||
#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT)
|
||||
|
||||
/* DMA stream configuration register */
|
||||
|
||||
#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */
|
||||
#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */
|
||||
#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */
|
||||
#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */
|
||||
#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */
|
||||
#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */
|
||||
#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */
|
||||
#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT)
|
||||
# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */
|
||||
# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */
|
||||
# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */
|
||||
#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */
|
||||
#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */
|
||||
#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */
|
||||
#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */
|
||||
#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT)
|
||||
# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */
|
||||
#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT)
|
||||
# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */
|
||||
#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */
|
||||
#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT)
|
||||
# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */
|
||||
# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */
|
||||
# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */
|
||||
# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */
|
||||
#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */
|
||||
#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */
|
||||
#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT)
|
||||
# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */
|
||||
# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */
|
||||
# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */
|
||||
# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */
|
||||
#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */
|
||||
#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT)
|
||||
# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */
|
||||
# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */
|
||||
# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */
|
||||
# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */
|
||||
#define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-27: Channel selection */
|
||||
#define DMA_SCR_CHSEL_MASK (7 << DMA_SCR_CHSEL_SHIFT)
|
||||
# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT)
|
||||
|
||||
#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE)
|
||||
|
||||
/* DMA stream number of data register */
|
||||
|
||||
#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA stream n FIFO control register */
|
||||
|
||||
#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */
|
||||
#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT)
|
||||
# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */
|
||||
# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */
|
||||
# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */
|
||||
# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */
|
||||
#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */
|
||||
#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */
|
||||
#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT)
|
||||
# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */
|
||||
# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */
|
||||
# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */
|
||||
# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */
|
||||
# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */
|
||||
# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */
|
||||
/* Bit 6: Reserved */
|
||||
#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DMA Stream mapping. Each DMA stream has a mapping to several possible
|
||||
* sources/sinks of data. The requests from peripherals assigned to a stream
|
||||
* are simply OR'ed together before entering the DMA block. This means that only
|
||||
* one request on a given stream can be enabled at once.
|
||||
*
|
||||
* Alternative stream selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* The DMA driver, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if
|
||||
* SPI3_RX connects via DMA STREAM0, then following should be application-specific
|
||||
* mapping should be used:
|
||||
*
|
||||
* #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1
|
||||
*/
|
||||
|
||||
#define STM32_DMA_MAP(d,s,c) ((d) << 6 | (s) << 3 | (c))
|
||||
#define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1)
|
||||
#define STM32_DMA_STREAM(m) (((m) >> 3) & 7)
|
||||
#define STM32_DMA_CHANNEL(m) ((m) & 7)
|
||||
|
||||
#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0)
|
||||
#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0)
|
||||
|
||||
#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1)
|
||||
#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1)
|
||||
#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1)
|
||||
|
||||
#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2)
|
||||
#define DMAMAP_I2S2_EXT_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2)
|
||||
#define DMAMAP_I2S2_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN2)
|
||||
#define DMAMAP_I2S3_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN2)
|
||||
|
||||
#define DMAMAP_I2S3_EXT_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_I2S2_EXT_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN3)
|
||||
#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3)
|
||||
|
||||
#define DMAMAP_UART5_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN4)
|
||||
#define DMAMAP_USART3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN4)
|
||||
#define DMAMAP_UART4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN4)
|
||||
#define DMAMAP_USART3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN4)
|
||||
#define DMAMAP_UART4_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN4)
|
||||
#define DMAMAP_USART2_RX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN4)
|
||||
#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4)
|
||||
#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4)
|
||||
|
||||
#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5)
|
||||
|
||||
#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_TRIG_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_TRIG_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6)
|
||||
|
||||
#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7)
|
||||
#define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7)
|
||||
#define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7)
|
||||
|
||||
#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0)
|
||||
#define DMAMAP_TIM8_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_TIM8_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0)
|
||||
#define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0)
|
||||
#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0)
|
||||
#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0)
|
||||
|
||||
#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1)
|
||||
#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1)
|
||||
#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1)
|
||||
#define DMAMAP_DCMI_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN1)
|
||||
|
||||
#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2)
|
||||
#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2)
|
||||
#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2)
|
||||
#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2)
|
||||
#define DMAMAP_HASH_IN STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN2)
|
||||
|
||||
#define DMAMAP_SPI1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3)
|
||||
|
||||
#define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4)
|
||||
#define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4)
|
||||
#define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4)
|
||||
#define DMAMAP_SDIO_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4)
|
||||
#define DMAMAP_SDIO_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4)
|
||||
|
||||
#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5)
|
||||
#define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5)
|
||||
|
||||
#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6)
|
||||
|
||||
#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F446 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_DMA_H */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,848 +0,0 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f44xxx_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions. All members of the STM32F40xxx family share the same
|
||||
* pin multiplexing (although they may differ in the pins physically available).
|
||||
*
|
||||
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if
|
||||
* CAN1_RX connects vis PA11 on some board, then the following definitions should
|
||||
* appear inthe board.h header file for that board:
|
||||
*
|
||||
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
*
|
||||
* The driver will then automatically configre PA11 as the CAN1 RX pin.
|
||||
*/
|
||||
|
||||
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
|
||||
* Additional effort is required to select specific GPIO options such as frequency,
|
||||
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
|
||||
* pins in this file.
|
||||
*/
|
||||
|
||||
/* ADC */
|
||||
|
||||
#define GPIO_ADC1_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
|
||||
|
||||
#define GPIO_ADC2_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_ADC2_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC2_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC2_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC2_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_ADC2_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
|
||||
|
||||
#define GPIO_ADC3_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC3_IN4 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_ADC3_IN15 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN5)
|
||||
|
||||
/* CAN */
|
||||
|
||||
#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_CAN1_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_CAN1_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_CAN1_RX_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
|
||||
#define GPIO_CAN1_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_CAN1_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_CAN1_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_CAN1_TX_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
|
||||
|
||||
#define GPIO_CAN2_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_CAN2_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_CAN2_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_CAN2_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
|
||||
|
||||
/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
|
||||
* (PA4 or PA5) is automatically connected to the analog converter output
|
||||
* (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin
|
||||
* should first be configured to analog (AIN)".
|
||||
*/
|
||||
|
||||
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
|
||||
|
||||
/* Digital Camera Interface (DCMI) */
|
||||
|
||||
#define GPIO_DCMI_D0_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D0_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D0_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D1_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_DCMI_D1_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_DCMI_D1_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN10)
|
||||
#define GPIO_DCMI_D2_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_DCMI_D2_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_DCMI_D2_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN11)
|
||||
#define GPIO_DCMI_D3_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D3_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_DCMI_D3_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN12)
|
||||
#define GPIO_DCMI_D4_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_DCMI_D4_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_DCMI_D4_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN14)
|
||||
#define GPIO_DCMI_D5_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D5_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN4)
|
||||
#define GPIO_DCMI_D6_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_DCMI_D6_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_DCMI_D6_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D7_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_DCMI_D7_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_DCMI_D7_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN7)
|
||||
#define GPIO_DCMI_D8_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_DCMI_D8_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_DCMI_D9_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_DCMI_D9_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN2)
|
||||
#define GPIO_DCMI_D10_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_DCMI_D10_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_DCMI_D11_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_DCMI_D11_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN15)
|
||||
#define GPIO_DCMI_D12 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_DCMI_D13_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_DCMI_D13_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_DCMI_HSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DCMI_HSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_DCMI_PIXCK (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_DCMI_VSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_DCMI_VSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN5)
|
||||
|
||||
/* Clocks outputs */
|
||||
|
||||
#define GPIO_MCO1 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_MCO2 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
|
||||
|
||||
/* Flexible Static Memory Controller (FSMC) */
|
||||
|
||||
#define GPIO_FSMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_FSMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_FSMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_FSMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_FSMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_FSMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5)
|
||||
#define GPIO_FSMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12)
|
||||
#define GPIO_FSMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13)
|
||||
#define GPIO_FSMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_FSMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_FSMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0)
|
||||
#define GPIO_FSMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1)
|
||||
#define GPIO_FSMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2)
|
||||
#define GPIO_FSMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3)
|
||||
#define GPIO_FSMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_FSMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_FSMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_FSMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_FSMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_FSMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_FSMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_FSMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_FSMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_FSMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_FSMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_FSMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_FSMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_FSMC_CD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_FSMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_FSMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_FSMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_FSMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_FSMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_FSMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_FSMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_FSMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_FSMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_FSMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_FSMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_FSMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_FSMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_FSMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_FSMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_FSMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_FSMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_FSMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
|
||||
#define GPIO_FSMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_FSMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_FSMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_FSMC_NCE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FSMC_NCE4_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_FSMC_NCE4_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_FSMC_NE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FSMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_FSMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_FSMC_NIORD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_FSMC_NIOWR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_FSMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_FSMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_FSMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
|
||||
#define GPIO_FSMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_FSMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_FSMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_FSMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_FSMC_SDCKE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_FSMC_SDNE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_FSMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_FSMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_FSMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_FSMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_FSMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_FSMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN5)
|
||||
#define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_I2C2_SDA_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
|
||||
|
||||
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
|
||||
|
||||
/* I2S */
|
||||
|
||||
#define GPIO_I2S1_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_I2S1_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_I2S1_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_I2S1_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_I2S1_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_I2S1_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2S1_MCK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_I2S1_MCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN4)
|
||||
|
||||
|
||||
#define GPIO_I2S2_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2S2_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_I2S2_CK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_I2S2_CK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_I2S2_CK_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_I2S2_CK_6 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_I2S2_MCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_I2S2_MCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_I2S2_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_I2S2_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_I2S2_SD_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_I2S2_SD_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_I2S2_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2S2_WS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2S2_WS_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_I2S2_WS_6 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2S2_WS_7 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_I2S2_WS_8 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN1)
|
||||
|
||||
#define GPIO_I2S2EXT_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_I2S2EXT_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_I2S2EXT_SD_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTI|GPIO_PIN2)
|
||||
|
||||
#define GPIO_I2S3_CK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_I2S3_CK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN7)
|
||||
//todo:2, too many!
|
||||
#define GPIO_I2S3_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_I2S3_SD_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_I2S3_SD_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_I2S3_SD_5 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_I2S3_SD_6 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_I2S3_SD_7 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_I2S3_SD_8 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_I2S3_SD_9 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_I2S3_SD_10 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_I2S3_WS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_I2S3_WS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
#define GPIO_I2S3EXT_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN11)
|
||||
|
||||
#define GPIO_I2S_CKIN (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN9)
|
||||
|
||||
/* JTAG */
|
||||
|
||||
#define GPIO_JTCK_SWCLK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_JTDO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_JTMS_SWDIO (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
|
||||
#define GPIO_JTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
|
||||
|
||||
/* OTG FS/HS (VBUS PA9 is not an alternate configuration) */
|
||||
|
||||
#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTGFS_SCL (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_OTGFS_SDA (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
|
||||
#define GPIO_OTGHSFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_OTGHSFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_OTGHSFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
|
||||
|
||||
#define GPIO_OTGHS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_OTGHS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_OTGHS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTGHS_INTN_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_OTGFS_INTN_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_OTGHS_SCL (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_OTGHS_SDA (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
|
||||
|
||||
#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_OTGHS_ULPI_D4_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_ULPI_D4_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0)
|
||||
|
||||
/* RTC */
|
||||
|
||||
#define GPIO_RTC_50HZ (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN15)
|
||||
|
||||
/* SDIO */
|
||||
|
||||
#define GPIO_SDIO_CK_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SDIO_CK_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_SDIO_D1_1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_SDIO_D1_2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_SDIO_D2_1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_SDIO_D2_2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_SDIO_D3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SDIO_D4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SDIO_D5 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SDIO_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SDIO_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
|
||||
#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN2)
|
||||
#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_SPI2_MOSI_4 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_SPI2_NSS_4 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SPI2_NSS_5 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_SPI2_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_SPI2_SCK_6 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
|
||||
#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_SPI3_MOSI_4 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_SPI3_MOSI_5 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_SPI3_MOSI_6 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_SPI3_MOSI_7 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
|
||||
#define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_SPI4_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_SPI4_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_SPI4_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_SPI4_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_SPI4_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_SPI4_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN7)
|
||||
|
||||
#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_TIM2_CH1IN_4 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_TIM2_CH1OUT_4 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH2IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH2OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH4IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN2)
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||||
#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH4OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
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||||
#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
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||||
#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
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||||
#define GPIO_TIM2_ETR_4 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
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||||
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||||
#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
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||||
#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4)
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||||
#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
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||||
#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
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||||
#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
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||||
#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
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||||
#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
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||||
#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5)
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||||
#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
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||||
#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
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||||
#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
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||||
#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
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||||
#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
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||||
#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
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||||
#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
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||||
#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
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||||
#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
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||||
#define GPIO_TIM3_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN2)
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||||
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||||
#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
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||||
#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
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||||
#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
|
||||
|
||||
#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN10)
|
||||
#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10)
|
||||
#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN11)
|
||||
#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11)
|
||||
#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN12)
|
||||
#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12)
|
||||
#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN10)
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||||
|
||||
#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6)
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||||
#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN4)
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||||
#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5)
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||||
#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7)
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||||
#define GPIO_TIM8_CH1N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13)
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||||
#define GPIO_TIM8_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
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||||
#define GPIO_TIM8_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
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||||
#define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5)
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||||
#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
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||||
#define GPIO_TIM8_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN6)
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||||
#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
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||||
#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6)
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||||
#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0)
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||||
#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14)
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||||
#define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14)
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||||
#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1)
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||||
#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15)
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||||
#define GPIO_TIM8_CH3N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15)
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||||
#define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
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||||
#define GPIO_TIM8_CH3IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN7)
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||||
#define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
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||||
#define GPIO_TIM8_CH3OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7)
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||||
#define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
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||||
#define GPIO_TIM8_CH4IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN2)
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||||
#define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
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||||
#define GPIO_TIM8_CH4OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2)
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||||
#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
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||||
#define GPIO_TIM8_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN3)
|
||||
|
||||
#define GPIO_TIM9_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
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||||
#define GPIO_TIM9_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5)
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||||
#define GPIO_TIM9_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
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||||
#define GPIO_TIM9_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
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||||
#define GPIO_TIM9_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
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||||
#define GPIO_TIM9_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6)
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||||
#define GPIO_TIM9_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
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||||
#define GPIO_TIM9_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
|
||||
|
||||
#define GPIO_TIM10_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM10_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_TIM10_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_TIM10_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
|
||||
|
||||
#define GPIO_TIM11_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM11_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_TIM11_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_TIM11_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
|
||||
|
||||
#define GPIO_TIM12_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_TIM12_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM12_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_TIM12_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_TIM12_CH2IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN9)
|
||||
#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_TIM12_CH2OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
|
||||
|
||||
#define GPIO_TIM13_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM13_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_TIM13_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM13_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8)
|
||||
|
||||
#define GPIO_TIM14_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM14_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_TIM14_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM14_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
|
||||
|
||||
/* Trace */
|
||||
|
||||
#define GPIO_TRACECLK (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_TRACED0_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TRACED0_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TRACED1_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TRACED1_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_TRACED2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TRACED3 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_TRACESWO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
|
||||
|
||||
/* UARTs/USARTs */
|
||||
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
|
||||
|
||||
#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5)
|
||||
|
||||
#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8)
|
||||
|
||||
#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_UART4_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_UART4_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN0)
|
||||
|
||||
#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_UART5_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_UART5_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN9)
|
||||
|
||||
#define GPIO_USART6_CK_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_USART6_CK_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_USART6_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_USART6_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_USART6_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_USART6_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
|
||||
|
||||
|
||||
/* Quad SPI */
|
||||
|
||||
#define GPIO_QUADSPI_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_QUADSPI_BK1_IO0_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_QUADSPI_BK1_IO0_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_QUADSPI_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_QUADSPI_BK1_IO1_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_QUADSPI_BK1_IO1_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_QUADSPI_BK1_IO2_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_QUADSPI_BK1_IO2_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_QUADSPI_BK1_IO3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_QUADSPI_BK1_IO3_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_QUADSPI_BK1_IO3_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_QUADSPI_BK1_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_QUADSPI_BK1_NCS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN6)
|
||||
|
||||
#define GPIO_QUADSPI_BK2_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_QUADSPI_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_QUADSPI_BK2_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_QUADSPI_BK2_IO2_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_QUADSPI_BK2_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_QUADSPI_BK2_IO3_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_QUADSPI_BK2_NCS (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN11)
|
||||
|
||||
/* SPDIFRX */
|
||||
|
||||
#define GPIO_SPDIFRX_IN0_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_SPDIFRX_IN0_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_SPDIFRX_IN0_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_SPDIFRX_IN1_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_SPDIFRX_IN1_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_SPDIFRX_IN1_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_SPDIFRX_IN2_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_SPDIFRX_IN2_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_SPDIFRX_IN3_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_SPDIFRX_IN3_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN5)
|
||||
|
||||
/* Serial Audio Interface */
|
||||
|
||||
#define GPIO_SAI1_FS_A_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_SAI1_FS_A_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_SAI1_FS_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_SAI1_FS_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SAI1_MCLK_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_SAI1_MCLK_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_SAI1_MCLK_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_SAI1_SCK_A_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_SAI1_SCK_A_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_SAI1_SCK_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_SAI1_SCK_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_SAI1_SD_B_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN6)
|
||||
|
||||
#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_SAI2_FS_B_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11)
|
||||
|
||||
/* HDMI-CEC Controller */
|
||||
|
||||
#define GPIO_HDMICEC_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_HDMICEC_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
|
||||
/* FMPI2C */
|
||||
|
||||
#define GPIO_FMPI2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_FMPI2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_FMPI2C1_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_FMPI2C1_SCL_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN14)
|
||||
|
||||
#define GPIO_FMPI2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_FMPI2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_FMPI2C1_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_FMPI2C1_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
|
||||
|
||||
#define GPIO_FMPI2C1_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_FMPI2C1_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13)
|
||||
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F446 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_PINMAP_H */
|
||||
|
|
@ -1,647 +0,0 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f44xxx_rcc.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_RCC_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x0004 /* PLL configuration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_CIR_OFFSET 0x000c /* Clock interrupt register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0010 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x0014 /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0018 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR_OFFSET 0x0020 /* APB1 Peripheral reset register */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0024 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0030 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x0034 /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0038 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR_OFFSET 0x0040 /* APB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0044 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2LPENR_OFFSET 0x0054 /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3LPENR_OFFSET 0x0058 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB2LPENR_OFFSET 0x0064 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0074 /* Control/status register */
|
||||
#define STM32_RCC_SSCGR_OFFSET 0x0080 /* Spread spectrum clock generation register */
|
||||
#define STM32_RCC_PLLI2SCFGR_OFFSET 0x0084 /* PLLI2S configuration register */
|
||||
#define STM32_RCC_PLLSAICFGR_OFFSET 0x0088 /* PLLSAI configuration register */
|
||||
#define STM32_RCC_DCKCFGR_OFFSET 0x008c /* Dedicated clocks configuration register */
|
||||
#define STM32_RCC_CKGATENR_OFFSET 0x0090 /* Clock gating for the specified IPs */
|
||||
#define STM32_RCC_DCKCFGR2_OFFSET 0x0094 /* Dedicated clocks configuration register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET)
|
||||
#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR)
|
||||
#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE+STM32_RCC_AHB3LPENR_OFFSET)
|
||||
#define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET)
|
||||
#define STM32_RCC_APB2LPENR (STM32_RCC_BASE+STM32_RCC_APB2LPENR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_SSCGR (STM32_RCC_BASE+STM32_RCC_SSCGR_OFFSET)
|
||||
#define STM32_RCC_PLLI2SCFGR (STM32_RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET)
|
||||
#define STM32_RCC_PLLSAICFGR (STM32_RCC_BASE+STM32_RCC_PLLSAICFGR_OFFSET)
|
||||
#define STM32_RCC_DCKCFGR (STM32_RCC_BASE+STM32_RCC_DCKCFGR_OFFSET)
|
||||
#define STM32_RCC_CKGATENR (STM32_RCC_BASE+STM32_RCC_CKGATENR_OFFSET)
|
||||
#define STM32_RCC_DCKCFGR2 (STM32_RCC_BASE+STM32_RCC_DCKCFGR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */
|
||||
#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */
|
||||
#define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */
|
||||
#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT)
|
||||
#define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed clock Calibration */
|
||||
#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT)
|
||||
#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */
|
||||
#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */
|
||||
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */
|
||||
#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */
|
||||
#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
|
||||
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
|
||||
#define RCC_CR_PLLI2SON (1 << 26) /* Bit 26: PLLI2S enable */
|
||||
#define RCC_CR_PLLI2SRDY (1 << 27) /* Bit 27: PLLI2S clock ready flag */
|
||||
#define RCC_CR_PLLSAION (1 << 28) /* Bit 28: PLLSAI enable */
|
||||
#define RCC_CR_PLLSAIRDY (1 << 29) /* Bit 29: PLLSAI clock ready flag */
|
||||
|
||||
/* PLL configuration register */
|
||||
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (0) /* Bits 0-5: Main PLL (PLL) and audio PLL (PLLI2S)
|
||||
* input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x3f << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT) /* n = 2..63 */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */
|
||||
#define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */
|
||||
#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT)
|
||||
# define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */
|
||||
# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */
|
||||
# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */
|
||||
# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */
|
||||
#define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S)
|
||||
* entry clock source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (0)
|
||||
# define RCC_PLLCFG_PLLSRC_HSE RCC_PLLCFG_PLLSRC
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (24) /* Bits 24-27: Main PLL (PLL) divider
|
||||
* (USB OTG FS, SDIO and RNG clocks) */
|
||||
#define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
# define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */
|
||||
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (28) /* Bits 28-30: Main PLLR (PLLR) divider
|
||||
* (I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks) */
|
||||
#define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT)
|
||||
# define RCC_PLLCFG_PLLR(n) ((n) << RCC_PLLCFG_PLLR_SHIFT) /* n=1..7 */
|
||||
|
||||
#define RCC_PLLCFG_RESET (0x24003010) /* PLLCFG reset value */
|
||||
|
||||
/* Clock configuration register */
|
||||
|
||||
#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */
|
||||
#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT)
|
||||
# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
|
||||
# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
|
||||
# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
|
||||
#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */
|
||||
#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT)
|
||||
# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
|
||||
#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
|
||||
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
|
||||
#define RCC_CFGR_PPRE1_SHIFT (10) /* Bits 10-12: APB Low speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
|
||||
# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
|
||||
#define RCC_CFGR_PPRE2_SHIFT (13) /* Bits 13-15: APB High speed prescaler (APB2) */
|
||||
#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT)
|
||||
# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
|
||||
#define RCC_CFGR_RTCPRE_SHIFT (16) /* Bits 16-20: APB High speed prescaler (APB2) */
|
||||
#define RCC_CFGR_RTCPRE_MASK (31 << RCC_CFGR_RTCPRE_SHIFT)
|
||||
# define RCC_CFGR_RTCPRE(n) ((n) << RCC_CFGR_RTCPRE_SHIFT) /* HSE/n, n=1..31 */
|
||||
#define RCC_CFGR_MCO1_SHIFT (21) /* Bits 21-22: Microcontroller Clock Output */
|
||||
#define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO1_SHIFT)
|
||||
# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 00: HSI clock selected */
|
||||
# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */
|
||||
# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */
|
||||
# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */
|
||||
#define RCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */
|
||||
#define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */
|
||||
#define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT)
|
||||
# define RCC_CFGR_MCO1PRE_NONE (0 << RCC_CFGR_MCO1PRE_SHIFT) /* 0xx: no division */
|
||||
# define RCC_CFGR_MCO1PRE_DIV2 (4 << RCC_CFGR_MCO1PRE_SHIFT) /* 100: division by 2 */
|
||||
# define RCC_CFGR_MCO1PRE_DIV3 (5 << RCC_CFGR_MCO1PRE_SHIFT) /* 101: division by 3 */
|
||||
# define RCC_CFGR_MCO1PRE_DIV4 (6 << RCC_CFGR_MCO1PRE_SHIFT) /* 110: division by 4 */
|
||||
# define RCC_CFGR_MCO1PRE_DIV5 (7 << RCC_CFGR_MCO1PRE_SHIFT) /* 111: division by 5 */
|
||||
#define RCC_CFGR_MCO2PRE_SHIFT (27) /* Bits 27-29: MCO2 prescaler */
|
||||
#define RCC_CFGR_MCO2PRE_MASK (7 << RCC_CFGR_MCO2PRE_SHIFT)
|
||||
# define RCC_CFGR_MCO2PRE_NONE (0 << RCC_CFGR_MCO2PRE_SHIFT) /* 0xx: no division */
|
||||
# define RCC_CFGR_MCO2PRE_DIV2 (4 << RCC_CFGR_MCO2PRE_SHIFT) /* 100: division by 2 */
|
||||
# define RCC_CFGR_MCO2PRE_DIV3 (5 << RCC_CFGR_MCO2PRE_SHIFT) /* 101: division by 3 */
|
||||
# define RCC_CFGR_MCO2PRE_DIV4 (6 << RCC_CFGR_MCO2PRE_SHIFT) /* 110: division by 4 */
|
||||
# define RCC_CFGR_MCO2PRE_DIV5 (7 << RCC_CFGR_MCO2PRE_SHIFT) /* 111: division by 5 */
|
||||
#define RCC_CFGR_MCO2_SHIFT (30) /* Bits 30-31: Microcontroller clock output 2 */
|
||||
#define RCC_CFGR_MCO2_MASK (3 << RCC_CFGR_MCO2_SHIFT)
|
||||
# define RCC_CFGR_MCO2_SYSCLK (0 << RCC_CFGR_MCO2_SHIFT) /* 00: System clock (SYSCLK) selected */
|
||||
# define RCC_CFGR_MCO2_PLLI2S (1 << RCC_CFGR_MCO2_SHIFT) /* 01: PLLI2S clock selected */
|
||||
# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 10: HSE oscillator clock selected */
|
||||
# define RCC_CFGR_MCO2_PLL (3 << RCC_CFGR_MCO2_SHIFT) /* 11: PLL clock selected */
|
||||
|
||||
/* Clock interrupt register */
|
||||
|
||||
#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */
|
||||
#define RCC_CIR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt flag */
|
||||
#define RCC_CIR_HSIRDYF (1 << 2) /* Bit 2: HSI Ready Interrupt flag */
|
||||
#define RCC_CIR_HSERDYF (1 << 3) /* Bit 3: HSE Ready Interrupt flag */
|
||||
#define RCC_CIR_PLLRDYF (1 << 4) /* Bit 4: PLL Ready Interrupt flag */
|
||||
#define RCC_CIR_PLLI2SRDYF (1 << 5) /* Bit 5: PLLI2S Ready Interrupt flag */
|
||||
#define RCC_CIR_CSSF (1 << 7) /* Bit 7: Clock Security System Interrupt flag */
|
||||
#define RCC_CIR_LSIRDYIE (1 << 8) /* Bit 8: LSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_LSERDYIE (1 << 9) /* Bit 9: LSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSIRDYIE (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSERDYIE (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_PLLRDYIE (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */
|
||||
#define RCC_CIR_PLLI2SRDYIE (1 << 13) /* Bit 13: PLLI2S Ready Interrupt enable */
|
||||
#define RCC_CIR_PLLSAIRDYIE (1 << 14) /* Bit 14: PLLSAI Ready Interrupt enable */
|
||||
#define RCC_CIR_LSIRDYC (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_LSERDYC (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSIRDYC (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSERDYC (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_PLLRDYC (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */
|
||||
#define RCC_CIR_PLLI2SRDYC (1 << 21) /* Bit 21: PLLI2S Ready Interrupt clear */
|
||||
#define RCC_CIR_PLLSAIRDYC (1 << 22) /* Bit 22: PLLSAI Ready Interrupt clear */
|
||||
#define RCC_CIR_CSSC (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */
|
||||
|
||||
/* AHB1 peripheral reset register */
|
||||
|
||||
#define RCC_AHB1RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
|
||||
#define RCC_AHB1RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
|
||||
#define RCC_AHB1RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
|
||||
#define RCC_AHB1RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */
|
||||
#define RCC_AHB1RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */
|
||||
#define RCC_AHB1RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */
|
||||
#define RCC_AHB1RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */
|
||||
#define RCC_AHB1RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */
|
||||
#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12 CRC reset */
|
||||
#define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA1 reset */
|
||||
#define RCC_AHB1RSTR_DMA2RST (1 << 22) /* Bit 22: DMA2 reset */
|
||||
#define RCC_AHB1RSTR_OTGHSRST (1 << 29) /* Bit 29: USB OTG HS module reset */
|
||||
|
||||
/* AHB2 peripheral reset register */
|
||||
|
||||
#define RCC_AHB2RSTR_DCMIRST (1 << 0) /* Bit 0: Camera interface reset */
|
||||
#define RCC_AHB2RSTR_CRYPRST (1 << 4) /* Bit 4: Cryptographic module reset */
|
||||
#define RCC_AHB2RSTR_HASHRST (1 << 5) /* Bit 5: Hash module reset */
|
||||
#define RCC_AHB2RSTR_RNGRST (1 << 6) /* Bit 6: Random number generator module reset */
|
||||
#define RCC_AHB2RSTR_OTGFSRST (1 << 7) /* Bit 7: USB OTG FS module reset */
|
||||
|
||||
/* AHB3 peripheral reset register */
|
||||
|
||||
#define RCC_AHB3RSTR_FSMCRST (1 << 0) /* Bit 0: Flexible static memory controller module reset */
|
||||
|
||||
/* APB1 Peripheral reset register */
|
||||
|
||||
#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */
|
||||
#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */
|
||||
#define RCC_APB1RSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */
|
||||
#define RCC_APB1RSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */
|
||||
#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */
|
||||
#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */
|
||||
#define RCC_APB1RSTR_TIM12RST (1 << 6) /* Bit 6: TIM12 reset */
|
||||
#define RCC_APB1RSTR_TIM13RST (1 << 7) /* Bit 7: TIM13 reset */
|
||||
#define RCC_APB1RSTR_TIM14RST (1 << 8) /* Bit 8: TIM14 reset */
|
||||
#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window watchdog reset */
|
||||
#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
|
||||
#define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI 3 reset */
|
||||
#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
|
||||
#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
|
||||
#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: USART 4 reset */
|
||||
#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: USART 5 reset */
|
||||
#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */
|
||||
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
|
||||
#define RCC_APB1RSTR_I2C3RST (1 << 23) /* Bit 23: I2C3 reset */
|
||||
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */
|
||||
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* Bit 26: CAN2 reset */
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
|
||||
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC reset */
|
||||
|
||||
/* APB2 Peripheral reset register */
|
||||
|
||||
#define RCC_APB2RSTR_TIM1RST (1 << 0) /* Bit 0: TIM1 reset */
|
||||
#define RCC_APB2RSTR_TIM8RST (1 << 1) /* Bit 1: TIM8 reset */
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 4) /* Bit 4: USART1 reset */
|
||||
#define RCC_APB2RSTR_USART6RST (1 << 5) /* Bit 5: USART6 reset */
|
||||
#define RCC_APB2RSTR_ADCRST (1 << 8) /* Bit 8: ADC interface reset (common to all ADCs) */
|
||||
#define RCC_APB2RSTR_SDIORST (1 << 11) /* Bit 11: SDIO reset */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */
|
||||
#define RCC_APB2RSTR_SPI4RST (1 << 13) /* Bit 13: SPI4 reset */
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 14) /* Bit 14: System configuration controller reset */
|
||||
#define RCC_APB2RSTR_TIM9RST (1 << 16) /* Bit 16: TIM9 reset */
|
||||
#define RCC_APB2RSTR_TIM10RST (1 << 17) /* Bit 17: TIM10 reset */
|
||||
#define RCC_APB2RSTR_TIM11RST (1 << 18) /* Bit 18: TIM11 reset */
|
||||
#define RCC_APB2RSTR_SAI1RST (1 << 22) /* Bit 22: SAI 1 reset */
|
||||
#define RCC_APB2RSTR_SAI2RST (1 << 23) /* Bit 23: SAI 2 reset */
|
||||
|
||||
/* AHB1 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB1ENR_GPIOEN(n) (1 << (n))
|
||||
#define RCC_AHB1ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */
|
||||
#define RCC_AHB1ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */
|
||||
#define RCC_AHB1ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */
|
||||
#define RCC_AHB1ENR_GPIODEN (1 << 3) /* Bit 3: IO port D clock enable */
|
||||
#define RCC_AHB1ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E clock enable */
|
||||
#define RCC_AHB1ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */
|
||||
#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */
|
||||
#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */
|
||||
#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
|
||||
#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
|
||||
#define RCC_AHB1ENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */
|
||||
#define RCC_AHB1ENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */
|
||||
#define RCC_AHB1ENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */
|
||||
#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */
|
||||
|
||||
/* AHB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB2ENR_DCMIEN (1 << 0) /* Bit 0: Camera interface enable */
|
||||
#define RCC_AHB2ENR_OTGFSEN (1 << 7) /* Bit 7: USB OTG FS clock enable */
|
||||
|
||||
/* AHB3 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHB3ENR_QSPIEN (1 << 1) /* Bit 1: QUADSPI memory controller module clock enable */
|
||||
#define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */
|
||||
|
||||
/* APB1 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: TIM2 clock enable */
|
||||
#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: TIM3 clock enable */
|
||||
#define RCC_APB1ENR_TIM4EN (1 << 2) /* Bit 2: TIM4 clock enable */
|
||||
#define RCC_APB1ENR_TIM5EN (1 << 3) /* Bit 3: TIM5 clock enable */
|
||||
#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: TIM6 clock enable */
|
||||
#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: TIM7 clock enable */
|
||||
#define RCC_APB1ENR_TIM12EN (1 << 6) /* Bit 6: TIM12 clock enable */
|
||||
#define RCC_APB1ENR_TIM13EN (1 << 7) /* Bit 7: TIM13 clock enable */
|
||||
#define RCC_APB1ENR_TIM14EN (1 << 8) /* Bit 8: TIM14 clock enable */
|
||||
#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */
|
||||
#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */
|
||||
#define RCC_APB1ENR_SPDIFRX (1 << 16) /* Bit 16: SPDIF-Rx clock enable */
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
|
||||
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART3 clock enable */
|
||||
#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART4 clock enable */
|
||||
#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART5 clock enable */
|
||||
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */
|
||||
#define RCC_APB1ENR_I2C3EN (1 << 23) /* Bit 23: I2C3 clock enable */
|
||||
#define RCC_APB1ENR_FMPI2C1EN (1 << 24) /* Bit 24: FMPI2C1 clock enable */
|
||||
#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN 1 clock enable */
|
||||
#define RCC_APB1ENR_CAN2EN (1 << 26) /* Bit 26: CAN 2 clock enable */
|
||||
#define RCC_APB1ENR_CECEN (1 << 27) /* Bit 27: CEC clock enable */
|
||||
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
|
||||
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
|
||||
|
||||
/* APB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: TIM1 clock enable */
|
||||
#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: TIM8 clock enable */
|
||||
#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: USART1 clock enable */
|
||||
#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: USART6 clock enable */
|
||||
#define RCC_APB2ENR_ADC1EN (1 << 8) /* Bit 8: ADC1 clock enable */
|
||||
#define RCC_APB2ENR_ADC2EN (1 << 9) /* Bit 9: ADC2 clock enable */
|
||||
#define RCC_APB2ENR_ADC3EN (1 << 10) /* Bit 10: ADC3 clock enable */
|
||||
#define RCC_APB2ENR_SDIOEN (1 << 11) /* Bit 11: SDIO clock enable */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */
|
||||
#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: SPI4 clock enable */
|
||||
#define RCC_APB2ENR_SYSCFGEN (1 << 14) /* Bit 14: System configuration controller clock enable */
|
||||
#define RCC_APB2ENR_TIM9EN (1 << 16) /* Bit 16: TIM9 clock enable */
|
||||
#define RCC_APB2ENR_TIM10EN (1 << 17) /* Bit 17: TIM10 clock enable */
|
||||
#define RCC_APB2ENR_TIM11EN (1 << 18) /* Bit 18: TIM11 clock enable */
|
||||
#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: SAI1 clock enable */
|
||||
#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: SAI2 clock enable */
|
||||
|
||||
/* RCC AHB1 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB1LPENR_GPIOLPEN(n) (1 << (n))
|
||||
#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */
|
||||
#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */
|
||||
|
||||
/* RCC AHB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB2LPENR_DCMILPEN (1 << 0) /* Bit 0: Camera interface enable during Sleep mode */
|
||||
#define RCC_AHB2LPENR_OTGFLPSEN (1 << 7) /* Bit 7: USB OTG FS clock enable during Sleep mode */
|
||||
|
||||
/* RCC AHB3 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB3LPENR_QSPILPEN (1 << 1) /* Bit 1: QUADSPI memory controller module clock enable
|
||||
* during Sleep mode */
|
||||
#define RCC_AHB3LPENR_FSMLPEN (1 << 0) /* Bit 0: Flexible static memory controller module clock
|
||||
* enable during Sleep mode */
|
||||
|
||||
/* RCC APB1 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB1LPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM3 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM4 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM5 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM6 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM7 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_WWDGLPEN (1 << 11) /* Bit 11: Window watchdog clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI3 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_SPDIFRXLPEN (1 << 16) /* Bit 16: SPDIF-Rx clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_USART2LPEN (1 << 17) /* Bit 17: USART 2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_USART3LPEN (1 << 18) /* Bit 18: USART3 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_UART4LPEN (1 << 19) /* Bit 19: UART4 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_UART5LPEN (1 << 20) /* Bit 20: UART5 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C1 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_I2C3LPEN (1 << 23) /* Bit 23: I2C3 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_FMPI2C1LPEN (1 << 24) /* Bit 24: FMPI2C1 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_CAN1LPEN (1 << 25) /* Bit 25: CAN 1 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_CAN2LPEN (1 << 26) /* Bit 26: CAN 2 clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_CECLPEN (1 << 27) /* Bit 27: CEC clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_PWRLPEN (1 << 28) /* Bit 28: Power interface clock enable during Sleep mode */
|
||||
#define RCC_APB1LPENR_DACLPEN (1 << 29) /* Bit 29: DAC interface clock enable during Sleep mode */
|
||||
|
||||
/* RCC APB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* Bit 0: TIM1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* Bit 1: TIM8 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* Bit 4: USART1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* Bit 5: USART6 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_ADC1LPEN (1 << 8) /* Bit 8: ADC1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_ADC2LPEN (1 << 9) /* Bit 9: ADC2 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_ADC3LPEN (1 << 10) /* Bit 10: ADC3 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SDIOLPEN (1 << 11) /* Bit 11: SDIO clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI4 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) /* Bit 14: System configuration controller clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM9LPEN (1 << 16) /* Bit 16: TIM9 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM10LPEN (1 << 17) /* Bit 17: TIM10 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_TIM11LPEN (1 << 18) /* Bit 18: TIM11 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* Bit 22: SAI1 clock enable during Sleep mode */
|
||||
#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* Bit 23: SAI2 clock enable during Sleep mode */
|
||||
|
||||
/* Backup domain control register */
|
||||
|
||||
#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */
|
||||
#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */
|
||||
#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */
|
||||
|
||||
#define RCC_BDCR_LSEMOD_SHIFT (3) /* Bit 3: External low-speed oscillator mode */
|
||||
#define RCC_BDCR_LSEMOD_MASK (1 << RCC_BDCR_LSEMOD_SHIFT) /* Bit 3: External low-speed oscillator mode */
|
||||
# define RCC_BDCR_LSEMOD_LOWPWR (0 << RCC_BDCR_LSEMOD_SHIFT) /* LSE oscillator "low power" mode selection */
|
||||
# define RCC_BDCR_LSEMOD_HIDRIVE (1 << RCC_BDCR_LSEMOD_SHIFT) /* LSE oscillator "high drive" mode selection */
|
||||
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
|
||||
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
|
||||
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */
|
||||
#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */
|
||||
#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */
|
||||
|
||||
/* Control/status register */
|
||||
|
||||
#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */
|
||||
#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */
|
||||
#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */
|
||||
#define RCC_CSR_BORRSTF (1 << 25) /* Bit 25: BOR reset flag */
|
||||
#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */
|
||||
#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */
|
||||
#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */
|
||||
#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */
|
||||
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */
|
||||
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */
|
||||
|
||||
/* Spread spectrum clock generation register */
|
||||
|
||||
#define RCC_SSCGR_MODPER_SHIFT (0) /* Bit 0-12: Modulation period */
|
||||
#define RCC_SSCGR_MODPER_MASK (0x1fff << RCC_SSCGR_MODPER_SHIFT)
|
||||
# define RCC_SSCGR_MODPER(n) ((n) << RCC_SSCGR_MODPER_SHIFT)
|
||||
#define RCC_SSCGR_INCSTEP_SHIFT (13) /* Bit 13-27: Incrementation step */
|
||||
#define RCC_SSCGR_INCSTEP_MASK (0x7fff << RCC_SSCGR_INCSTEP_SHIFT)
|
||||
# define RCC_SSCGR_INCSTEP(n) ((n) << RCC_SSCGR_INCSTEP_SHIFT)
|
||||
#define RCC_SSCGR_SPREADSEL (1 << 30) /* Bit 30: Spread Select */
|
||||
#define RCC_SSCGR_SSCGEN (1 << 31) /* Bit 31: Spread spectrum modulation enable */
|
||||
|
||||
/* PLLI2S configuration register */
|
||||
|
||||
#define RCC_PLLI2SCFGR_PLLI2SM_SHIFT (0) /* Bits 0-5: Division factor M for audio PLL
|
||||
(PLLI2S) input clock */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SM_MASK (0x3f << RCC_PLLI2SCFGR_PLLI2SM_SHIFT)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SM(n) ((n) << RCC_PLLI2SCFGR_PLLI2SM_SHIFT)
|
||||
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT (6) /* Bits 6-14: PLLI2S N multiplication factor for VCO */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SN(n) ((n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
|
||||
#define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIF-Rx clock */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SP_MASK (0x3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
|
||||
/* Set PLLI2S P to 2,4,6,8 */
|
||||
# define RCC_PLLI2SCFGR_PLLI2SP(n) (((((n)-2)/2) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) & RCC_PLLI2SCFGR_PLLI2SP_MASK)
|
||||
|
||||
#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAI1 clock*/
|
||||
#define RCC_PLLI2SCFGR_PLLI2SQ_MASK (0xf << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SQ(n) ((n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
|
||||
|
||||
#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */
|
||||
#define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
|
||||
# define RCC_PLLI2SCFGR_PLLI2SR(n) ((n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
|
||||
|
||||
/* PLLSAI configuration register */
|
||||
|
||||
#define RCC_PLLSAICFGR_PLLSAIM_SHIFT (0) /* Bits 0-5: Division factor M for audio PLLSAI
|
||||
input clock */
|
||||
#define RCC_PLLSAICFGR_PLLSAIM_MASK (0x3f << RCC_PLLSAICFGR_PLLSAIM_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIM(n) ((n) << RCC_PLLSAICFGR_PLLSAIM_SHIFT)
|
||||
|
||||
#define RCC_PLLSAICFGR_PLLSAIN_SHIFT (6) /* Bits 6-14: PLLSAI divider (N) for VCO */
|
||||
#define RCC_PLLSAICFGR_PLLSAIN_MASK (0x1ff << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT)
|
||||
|
||||
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48 MHz clock */
|
||||
#define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
|
||||
/* Set PLLSAI P to 2,4,6,8 */
|
||||
# define RCC_PLLSAICFGR_PLLSAIP(n) (((((n)-2)/2) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) & RCC_PLLSAICFGR_PLLSAIP_MASK)
|
||||
|
||||
#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */
|
||||
#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
|
||||
# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
|
||||
|
||||
|
||||
/* Dedicated clocks configuration register */
|
||||
|
||||
#define RCC_DCKCFGR_PLLI2SDIVQ_SHIFT (0) /* Bits 0-4: PLLI2S division 1..32 factor for I2S clock */
|
||||
#define RCC_DCKCFGR_PLLI2SDIVQ_MASK (0x1F << RCC_DCKCFGR_PLLI2SDIVQ_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLI2SDIVQ(n) (((n)-1) << RCC_DCKCFGR_PLLI2SDIVQ_SHIFT)
|
||||
#define RCC_DCKCFGR_PLLSAIDIVQ_SHIFT (8) /* Bits 8-12: PLLSAI division 1..32 factor for SAI clock */
|
||||
#define RCC_DCKCFGR_PLLSAIDIVQ_MASK (0x1F << RCC_DCKCFGR_PLLSAIDIVQ_SHIFT)
|
||||
# define RCC_DCKCFGR_PLLSAIDIVQ(n) (((n)-1) << RCC_DCKCFGR_PLLSAIDIVQ_SHIFT)
|
||||
#define RCC_DCKCFGR_SAI1SRC_SHIFT (20) /* Bits 20-21: SAI1 clock source selection */
|
||||
#define RCC_DCKCFGR_SAI1SRC_MASK (0x3 << RCC_DCKCFGR_SAI1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI1SRC(n) ((n) << RCC_DCKCFGR_SAI1SRC_SHIFT)
|
||||
#define RCC_DCKCFGR_SAI2SRC_SHIFT (22) /* Bits 22-23: SAI2 clock source selection */
|
||||
#define RCC_DCKCFGR_SAI2SRC_MASK (0x3 << RCC_DCKCFGR_SAI2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_SAI2SRC(n) ((n) << RCC_DCKCFGR_SAI2SRC_SHIFT)
|
||||
#define RCC_DCKCFGR_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */
|
||||
#define RCC_DCKCFGR_I2S1SRC_SHIFT (25) /* Bits 25-26: I2S APB1 clock source selection */
|
||||
#define RCC_DCKCFGR_I2S1SRC_MASK (0x3 << RCC_DCKCFGR_I2S1SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S1SRC(n) ((n) << RCC_DCKCFGR_I2S1SRC_SHIFT)
|
||||
#define RCC_DCKCFGR_I2S2SRC_SHIFT (28) /* Bits 28-29: I2S APB2 clock source selection */
|
||||
#define RCC_DCKCFGR_I2S2SRC_MASK (0x3 << RCC_DCKCFGR_I2S2SRC_SHIFT)
|
||||
# define RCC_DCKCFGR_I2S2SRC(n) ((n) << RCC_DCKCFGR_I2S2SRC_SHIFT)
|
||||
|
||||
#define RCC_SAI2CLKSRC_PLLSAI 0
|
||||
#define RCC_SAI2CLKSRC_PLLI2S 1
|
||||
#define RCC_SAI2CLKSRC_PLLR 2
|
||||
#define RCC_SAI2CLKSRC_HSX 3
|
||||
|
||||
#define RCC_SAI1CLKSRC_PLLSAI 0
|
||||
#define RCC_SAI1CLKSRC_PLLI2S 1
|
||||
#define RCC_SAI1CLKSRC_PLLR 2
|
||||
#define RCC_SAI2CLKSRC_I2S_CLKIN 3
|
||||
|
||||
#define RCC_I2SSRC_PLLI2S_R 0
|
||||
#define RCC_I2SSRC_I2S_CKIN 1
|
||||
#define RCC_I2SSRC_PLL_R 2
|
||||
#define RCC_I2SSRC_HSX 3
|
||||
|
||||
|
||||
/* RCC clocks gated enable register */
|
||||
|
||||
#define RCC_CKGATENR_AHB2APB1_CKEN (1 << 0) /* Bit 0: AHB to APB1 Bridge clock enable */
|
||||
#define RCC_CKGATENR_AHB2APB2_CKEN (1 << 1) /* Bit 1: AHB to APB2 Bridge clock enable */
|
||||
#define RCC_CKGATENR_CM4DBG_CKEN (1 << 2) /* Bit 2: Cortex M4 ETM clock enable */
|
||||
#define RCC_CKGATENR_SPARE_CKEN (1 << 3) /* Bit 3: Spare clock enable */
|
||||
#define RCC_CKGATENR_SRAM_CKEN (1 << 4) /* Bit 4: SRQAM controller clock enable */
|
||||
#define RCC_CKGATENR_FLITF_CKEN (1 << 5) /* Bit 5: Flash Interface clock enable */
|
||||
#define RCC_CKGATENR_RCC_CKEN (1 << 6) /* Bit 6: RCC clock enable */
|
||||
|
||||
/* Dedicated clocks configuration register 2 */
|
||||
|
||||
#define RCC_DCKCFGR2_FMPI2C1SEL_SHIFT (22) /* Bits 22-23: I2C4 clock source selection */
|
||||
#define RCC_DCKCFGR2_FMPI2C1SEL_MASK (3 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_FMPI2C1SEL_APB (0 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 4 clock */
|
||||
# define RCC_DCKCFGR2_FMPI2C1SEL_SYSCLK (1 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) /* System clock is selected as I2C 4 clock */
|
||||
# define RCC_DCKCFGR2_FMPI2C1SEL_HSI (2 << RCC_DCKCFGR2_FMPI2C1SEL_SHIFT) /* HSI clock is selected as I2C 4 clock */
|
||||
#define RCC_DCKCFGR2_CECSEL_SHIFT (26) /* Bit 26: HDMI-CEC clock source selection */
|
||||
#define RCC_DCKCFGR2_CECSEL_MASK (1 << RCC_DCKCFGR2_CECSEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_CECSEL_LSE (0 << RCC_DCKCFGR2_CECSEL_SHIFT) /* LSE clock is selected as HDMI-CEC clock */
|
||||
# define RCC_DCKCFGR2_CECSEL_HSI (1 << RCC_DCKCFGR2_CECSEL_SHIFT) /* HSI clock is selected as HDMI-CEC clock */
|
||||
#define RCC_DCKCFGR2_CK48MSEL_SHIFT (27) /* Bit 27: 48MHz clock source selection */
|
||||
#define RCC_DCKCFGR2_CK48MSEL_MASK (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_CK48MSEL_PLL (0 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48MHz clock from PLL is selected */
|
||||
# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48MHz clock from PLLSAI is selected */
|
||||
#define RCC_DCKCFGR2_SDIOCSEL_SHIFT (28) /* Bit 28: SDIO clock source selection */
|
||||
#define RCC_DCKCFGR2_SDIOCSEL_MASK (1 << RCC_DCKCFGR2_SDIOCSEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_SDIOCSEL_48MHZ (0 << RCC_DCKCFGR2_SDIOCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */
|
||||
# define RCC_DCKCFGR2_SDIOCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDIOCSEL_SHIFT) /* System clock is selected as SDMMC clock */
|
||||
|
||||
#define RCC_DCKCFGR2_SPDIFRXEL_SHIFT (29) /* Bit 29: SPDIF-Rx clock selection */
|
||||
#define RCC_DCKCFGR2_SPDIFRXEL_MASK (1 << RCC_DCKCFGR2_SPDIFRXEL_SHIFT)
|
||||
# define RCC_DCKCFGR2_SPDIFRXEL_48MHZ (0 << RCC_DCKCFGR2_SPDIFRXEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */
|
||||
# define RCC_DCKCFGR2_SPDIFRXEL_SYSCLK (1 << RCC_DCKCFGR2_SPDIFRXEL_SHIFT) /* System clock is selected as SDMMC clock */
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F446 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_RCC_H */
|
||||
|
|
@ -1,166 +0,0 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f44xxx_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
|
||||
#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */
|
||||
#define STM32_SYSCFG_CFGR_OFFSET 0x002c /* SYSCFG configuration register */
|
||||
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR_OFFSET)
|
||||
|
||||
/* Register Bit field Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
|
||||
#define SYSCFG_MEMRMP_MASK (3 << SYSCFG_MEMRMP_SHIFT)
|
||||
# define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 00: Main Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 01: System Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_FSMC (2 << SYSCFG_MEMRMP_SHIFT) /* 10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 11: Embedded SRAM (112kB) mapped at 0x0000 0000 */
|
||||
|
||||
#define SYSCFG_SWPFMC_SHIFT (0) /* Bits 10:11 SWP_FMC: FMC memory mapping swap */
|
||||
#define SYSCFG_SWPFMC_MASK (3 << SYSCFG_SWPFMC_SHIFT)
|
||||
# define SYSCFG_SWPFMC_NOSWAP (0 << SYSCFG_SWPFMC_SHIFT) /* 00: No FMC memory mapping swap */
|
||||
# define SYSCFG_SWPFMC_SWAP (1 << SYSCFG_SWPFMC_SHIFT) /* 01: SDRAM banks and NAND Bank 2/PCCARD mapping are swapped */
|
||||
|
||||
/* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* Compensation cell control register */
|
||||
|
||||
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
|
||||
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
|
||||
|
||||
/* SYSCFG configuration register */
|
||||
|
||||
#define SYSCFG_CFGR_FMPI2C1_SCL (1 << 0) /* Bit 0: Forces FM+ drive capability on SCL */
|
||||
#define SYSCFG_CFGR_FMPI2C1_SDA (1 << 1) /* Bit 8: Forces FM+ drive capability on SDA */
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F446 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F44XXX_SYSCFG_H */
|
||||
|
|
@ -1,159 +0,0 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f44xxx_vectors.h
|
||||
*
|
||||
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
|
||||
* supplies ach STM32F40xxx vector in terms of a (lower-case) ISR label and an
|
||||
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f40xxx_irq.h.
|
||||
* stm32_vectors.S will define the VECTOR macro in different ways in order to generate
|
||||
* the interrupt vectors and handlers in their final form.
|
||||
*/
|
||||
|
||||
/* If the common ARMv7-M vector handling is used, then all it needs is the following
|
||||
* definition that provides the number of supported vectors.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARMV7M_CMNVECTOR
|
||||
|
||||
/* Reserve interrupt table entries for I/O interrupts. */
|
||||
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS 97
|
||||
|
||||
#else
|
||||
|
||||
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */
|
||||
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */
|
||||
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper and time stamp interrupts */
|
||||
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* Vector 16+3: RTC global interrupt */
|
||||
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */
|
||||
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */
|
||||
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */
|
||||
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */
|
||||
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */
|
||||
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */
|
||||
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */
|
||||
VECTOR(stm32_dma1s0, STM32_IRQ_DMA1S0) /* Vector 16+11: DMA1 Stream 0 global interrupt */
|
||||
VECTOR(stm32_dma1s1, STM32_IRQ_DMA1S1) /* Vector 16+12: DMA1 Stream 1 global interrupt */
|
||||
VECTOR(stm32_dma1s2, STM32_IRQ_DMA1S2) /* Vector 16+13: DMA1 Stream 2 global interrupt */
|
||||
VECTOR(stm32_dma1s3, STM32_IRQ_DMA1S3) /* Vector 16+14: DMA1 Stream 3 global interrupt */
|
||||
VECTOR(stm32_dma1s4, STM32_IRQ_DMA1S4) /* Vector 16+15: DMA1 Stream 4 global interrupt */
|
||||
VECTOR(stm32_dma1s5, STM32_IRQ_DMA1S5) /* Vector 16+16: DMA1 Stream 5 global interrupt */
|
||||
VECTOR(stm32_dma1s6, STM32_IRQ_DMA1S6) /* Vector 16+17: DMA1 Stream 6 global interrupt */
|
||||
VECTOR(stm32_adc, STM32_IRQ_ADC) /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */
|
||||
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* Vector 16+19: CAN1 TX interrupts */
|
||||
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* Vector 16+20: CAN1 RX0 interrupts */
|
||||
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */
|
||||
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */
|
||||
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */
|
||||
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */
|
||||
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */
|
||||
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */
|
||||
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */
|
||||
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */
|
||||
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */
|
||||
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */
|
||||
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */
|
||||
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */
|
||||
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */
|
||||
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */
|
||||
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */
|
||||
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */
|
||||
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */
|
||||
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */
|
||||
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */
|
||||
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */
|
||||
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* Vector 16+41: RTC alarm through EXTI line interrupt */
|
||||
VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP) /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
|
||||
VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */
|
||||
VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* Vector 16+44: TIM8 Update interrupt/TIM13 global interrupt */
|
||||
VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */
|
||||
VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* Vector 16+46: TIM8 Capture Compare interrupt */
|
||||
VECTOR(stm32_dma1s7, STM32_IRQ_DMA1S7) /* Vector 16+47: DMA1 Stream 7 global interrupt */
|
||||
VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */
|
||||
VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* Vector 16+49: SDIO global interrupt */
|
||||
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */
|
||||
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */
|
||||
VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */
|
||||
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */
|
||||
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */
|
||||
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */
|
||||
VECTOR(stm32_dma2s0, STM32_IRQ_DMA2S0) /* Vector 16+56: DMA2 Stream 0 global interrupt */
|
||||
VECTOR(stm32_dma2s1, STM32_IRQ_DMA2S1) /* Vector 16+57: DMA2 Stream 1 global interrupt */
|
||||
VECTOR(stm32_dma2s2, STM32_IRQ_DMA2S2) /* Vector 16+58: DMA2 Stream 2 global interrupt */
|
||||
VECTOR(stm32_dma2s3, STM32_IRQ_DMA2S3) /* Vector 16+59: DMA2 Stream 3 global interrupt */
|
||||
VECTOR(stm32_dma2s4, STM32_IRQ_DMA2S4) /* Vector 16+60: DMA2 Stream 4 global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES01) /* Vector 16+61: 1st Reserved (Ethernet global) interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES02) /* Vector 16+62: 2nd Reserved (Ethernet Wakeup through EXTI line) interrupt */
|
||||
VECTOR(stm32_can2tx, STM32_IRQ_CAN2TX) /* Vector 16+63: CAN2 TX interrupts */
|
||||
VECTOR(stm32_can2rx0, STM32_IRQ_CAN2RX0) /* Vector 16+64: CAN2 RX0 interrupts */
|
||||
VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 interrupt */
|
||||
VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE interrupt */
|
||||
VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */
|
||||
VECTOR(stm32_dma2s5, STM32_IRQ_DMA2S5) /* Vector 16+68: DMA2 Stream 5 global interrupt */
|
||||
VECTOR(stm32_dma2s6, STM32_IRQ_DMA2S6) /* Vector 16+69: DMA2 Stream 6 global interrupt */
|
||||
VECTOR(stm32_dma2s7, STM32_IRQ_DMA2S7) /* Vector 16+70: DMA2 Stream 7 global interrupt */
|
||||
VECTOR(stm32_usart6, STM32_IRQ_USART6) /* Vector 16+71: USART6 global interrupt */
|
||||
VECTOR(stm32_i2c3ev, STM32_IRQ_I2C3EV) /* Vector 16+72: I2C3 event interrupt */
|
||||
VECTOR(stm32_i2c3er, STM32_IRQ_I2C3ER) /* Vector 16+73: I2C3 error interrupt */
|
||||
VECTOR(stm32_otghsep1out, STM32_IRQ_OTGHSEP1OUT) /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
VECTOR(stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN) /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */
|
||||
VECTOR(stm32_otghswkup, STM32_IRQ_OTGHSWKUP) /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
VECTOR(stm32_otghs, STM32_IRQ_OTGHS) /* Vector 16+77: USB On The Go HS global interrupt */
|
||||
VECTOR(stm32_dcmi, STM32_IRQ_DCMI) /* Vector 16+78: DCMI global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES03) /* Vector 16+79: 3rd Reserved (CRYP crypto global) interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES04) /* Vector 16+80: 4th Reserved (Hash and Rng global) interrupt */
|
||||
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* Vector 16+81: FPU global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES05) /* Vector 16+82: 5th Reserved (UART7)interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES06) /* Vector 16+83: 6th Reserved (UART8) interrupt */
|
||||
VECTOR(stm32_spi4, STM32_IRQ_SPI4) /* Vector 16+84: SPI4 interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES07) /* Vector 16+85: 7th Reserved (SPI5) interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES08) /* Vector 16+86: 8th Reserved (SPI6) interrupt */
|
||||
VECTOR(stm32_sai1, STM32_IRQ_SAI1) /* Vector 16+87: SAI1 interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES09) /* Vector 16+88: 9th Reserved (LTDCINT interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES10) /* Vector 16+89: 10th Reserved (LTDCERRINT) interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_RES11) /* Vector 16+90: 11th Reserved (DMA2D) interrupt */
|
||||
/* todo:Implemnt 91-96 */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_SAI2) /* Vector 16+91: SAI2 Global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_QUADSPI) /* Vector 16+92: QuadSPI Global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_HDMICEC) /* Vector 16+93: HDMI-CEC Global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_SPDIFRX) /* Vector 16+94: SPDIF-Rx Global interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_FMPI2C1) /* Vector 16+95: FMPI2C1 event interrupt */
|
||||
VECTOR(stm32_reserved, STM32_IRQ_FMPI2C1ERR) /* Vector 16+96: FMPI2C1 Error event interrupt */
|
||||
|
||||
#endif /* CONFIG_ARMV7M_CMNVECTOR */
|
||||
|
|
@ -1,8 +1,10 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
|
||||
*
|
||||
* Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -385,17 +387,30 @@
|
|||
|
||||
#define OTGFS_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */
|
||||
#define OTGFS_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */
|
||||
/* Bits 2-7 Reserved, must be kept at reset value */
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define OTGFS_GOTGCTL_VBVALOEN (1 << 2) /* Bit 2: VBUS valid override enable */
|
||||
# define OTGFS_GOTGCTL_VBVALOVAL (1 << 3) /* Bit 3: VBUS valid override value */
|
||||
# define OTGFS_GOTGCTL_AVALOEN (1 << 4) /* Bit 4: A-peripheral session valid override enable */
|
||||
# define OTGFS_GOTGCTL_AVALOVAL (1 << 5) /* Bit 5: A-peripheral session valid override value */
|
||||
# define OTGFS_GOTGCTL_BVALOEN (1 << 6) /* Bit 6: B-peripheral session valid override enable */
|
||||
# define OTGFS_GOTGCTL_BVALOVAL (1 << 7) /* Bit 7: B-peripheral session valid override value */
|
||||
#endif
|
||||
#define OTGFS_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */
|
||||
#define OTGFS_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */
|
||||
#define OTGFS_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */
|
||||
#define OTGFS_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */
|
||||
/* Bits 12-15: Reserved, must be kept at reset value */
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define OTGFS_GOTGCTL_EHEN (1 << 12) /* Bit 12: Embedded host enable */
|
||||
#endif
|
||||
/* Bits 13-15: Reserved, must be kept at reset value */
|
||||
#define OTGFS_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */
|
||||
#define OTGFS_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */
|
||||
#define OTGFS_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */
|
||||
#define OTGFS_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */
|
||||
/* Bits 20-31: Reserved, must be kept at reset value */
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define OTGFS_GOTGCTL_OTGVER (1 << 20) /* Bit 20: OTG version */
|
||||
#endif
|
||||
/* Bits 21-31: Reserved, must be kept at reset value */
|
||||
/* Interrupt register */
|
||||
/* Bits 1:0 Reserved, must be kept at reset value */
|
||||
#define OTGFS_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */
|
||||
|
|
@ -406,7 +421,10 @@
|
|||
#define OTGFS_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */
|
||||
#define OTGFS_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */
|
||||
#define OTGFS_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */
|
||||
/* Bits 20-31: Reserved, must be kept at reset value */
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define OTGFS_GOTGINT_IDCHNG (1 << 20) /* Bit 20: Change in ID pin input value */
|
||||
#endif
|
||||
/* Bits 21-31: Reserved, must be kept at reset value */
|
||||
|
||||
/* AHB configuration register */
|
||||
|
||||
|
|
@ -476,11 +494,16 @@
|
|||
#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
|
||||
#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
|
||||
#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
|
||||
/* Bits 22-23: Reserved, must be kept at reset value */
|
||||
/* Bit 22: Reserved, must be kept at reset value */
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define OTGFS_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
|
||||
#endif
|
||||
#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
|
||||
#define OTGFS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */
|
||||
#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */
|
||||
/* Bit 27 Reserved, must be kept at reset value */
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define OTGFS_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */
|
||||
#endif
|
||||
#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */
|
||||
#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */
|
||||
#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */
|
||||
|
|
@ -571,14 +594,18 @@
|
|||
# define OTGFS_HNPTXSTS_EPNUM_MASK (15 << OTGFS_HNPTXSTS_EPNUM_SHIFT)
|
||||
/* Bit 31 Reserved, must be kept at reset value */
|
||||
/* General core configuration register */
|
||||
/* Bits 15:0 Reserved, must be kept at reset value */
|
||||
/* Bits 0-15: Reserved, must be kept at reset value */
|
||||
#define OTGFS_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */
|
||||
/* Bit 17 Reserved, must be kept at reset value */
|
||||
#define OTGFS_GCCFG_VBUSASEN (1 << 18) /* Bit 18: Enable the VBUS sensing A device */
|
||||
#define OTGFS_GCCFG_VBUSBSEN (1 << 19) /* Bit 19: Enable the VBUS sensing B device */
|
||||
#define OTGFS_GCCFG_SOFOUTEN (1 << 20) /* Bit 20: SOF output enable */
|
||||
#define OTGFS_GCCFG_NOVBUSSENS (1 << 21) /* Bit 21: VBUS sensing disable option */
|
||||
/* Bits 31:22 Reserved, must be kept at reset value */
|
||||
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
# define OTGFS_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */
|
||||
#else
|
||||
# define OTGFS_GCCFG_VBUSASEN (1 << 18) /* Bit 18: Enable the VBUS sensing A device */
|
||||
# define OTGFS_GCCFG_VBUSBSEN (1 << 19) /* Bit 19: Enable the VBUS sensing B device */
|
||||
# define OTGFS_GCCFG_SOFOUTEN (1 << 20) /* Bit 20: SOF output enable */
|
||||
# define OTGFS_GCCFG_NOVBUSSENS (1 << 21) /* Bit 21: VBUS sensing disable option */
|
||||
#endif
|
||||
/* Bits 22-31: Reserved, must be kept at reset value */
|
||||
/* Core ID register (32-bit product ID) */
|
||||
|
||||
/* Host periodic transmit FIFO size register */
|
||||
|
|
|
|||
|
|
@ -52,10 +52,6 @@
|
|||
# include "chip/stm32f10xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "chip/stm32f20xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_dma.h"
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -46,11 +46,7 @@
|
|||
|
||||
#include "stm32.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_otgfs.h"
|
||||
#else
|
||||
# include "chip/stm32fxxxxx_otgfs.h"
|
||||
#endif
|
||||
#include "chip/stm32fxxxxx_otgfs.h"
|
||||
|
||||
#if defined(CONFIG_STM32_OTGFS)
|
||||
|
||||
|
|
|
|||
|
|
@ -86,10 +86,6 @@
|
|||
# include "stm32f30xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "stm32f37xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "stm32f42xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "stm32f44xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "stm32f40xxx_rcc.c"
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -55,10 +55,6 @@
|
|||
# include "chip/stm32f30xxx_rcc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f37xxx_rcc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_rcc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_rcc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_rcc.h"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -51,10 +51,6 @@
|
|||
# include "chip/stm32f30xxx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f37xxx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_syscfg.h"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -179,10 +179,6 @@ _vectors:
|
|||
# include "chip/stm32f30xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f37xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_vectors.h"
|
||||
#else
|
||||
|
|
@ -228,10 +224,6 @@ handlers:
|
|||
# include "chip/stm32f30xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f37xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_vectors.h"
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -2,8 +2,10 @@
|
|||
* arch/arm/src/stm32/stm32f40xxx_rcc.c
|
||||
*
|
||||
* Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -134,37 +136,37 @@ static inline void rcc_enableahb1(void)
|
|||
|
||||
/* Enable GPIOA, GPIOB, .... GPIOI */
|
||||
|
||||
#if STM32_NGPIO > 0
|
||||
#if STM32_NGPIO_PORTS > 0
|
||||
regval |= (RCC_AHB1ENR_GPIOAEN
|
||||
#if STM32_NGPIO > 16
|
||||
#if STM32_NGPIO_PORTS > 1
|
||||
| RCC_AHB1ENR_GPIOBEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 32
|
||||
#if STM32_NGPIO_PORTS > 2
|
||||
| RCC_AHB1ENR_GPIOCEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 48
|
||||
#if STM32_NGPIO_PORTS > 3
|
||||
| RCC_AHB1ENR_GPIODEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 64
|
||||
#if STM32_NGPIO_PORTS > 4
|
||||
| RCC_AHB1ENR_GPIOEEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 80
|
||||
#if STM32_NGPIO_PORTS > 5
|
||||
| RCC_AHB1ENR_GPIOFEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 96
|
||||
#if STM32_NGPIO_PORTS > 6
|
||||
| RCC_AHB1ENR_GPIOGEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 112
|
||||
#if STM32_NGPIO_PORTS > 7
|
||||
| RCC_AHB1ENR_GPIOHEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 128
|
||||
#if STM32_NGPIO_PORTS > 8
|
||||
| RCC_AHB1ENR_GPIOIEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 144
|
||||
|RCC_AHB1ENR_GPIOJEN
|
||||
#if STM32_NGPIO_PORTS > 9
|
||||
| RCC_AHB1ENR_GPIOJEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 160
|
||||
|RCC_AHB1ENR_GPIOKEN
|
||||
#if STM32_NGPIO_PORTS > 10
|
||||
| RCC_AHB1ENR_GPIOKEN
|
||||
#endif
|
||||
);
|
||||
#endif
|
||||
|
|
@ -675,26 +677,32 @@ static void stm32_stdclockconfig(void)
|
|||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
|
||||
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
|
||||
regval &= ~PWR_CR_VOS_MASK;
|
||||
regval |= PWR_CR_VOS_SCALE_1;
|
||||
#else
|
||||
regval |= PWR_CR_VOS;
|
||||
#endif
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_HPRE_MASK;
|
||||
regval |= STM32_RCC_CFGR_HPRE;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK2 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE2_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE2;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK1 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE1_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
|
@ -702,7 +710,7 @@ static void stm32_stdclockconfig(void)
|
|||
#ifdef CONFIG_RTC_HSECLOCK
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_RTCPRE_MASK;
|
||||
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
|
@ -710,18 +718,22 @@ static void stm32_stdclockconfig(void)
|
|||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP
|
||||
| STM32_PLLCFG_PLLQ
|
||||
#ifdef STM32_BOARD_USEHSI
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
|
||||
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
|
||||
| RCC_PLLCFG_PLLSRC_HSI
|
||||
#else /* if STM32_BOARD_USEHSE */
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
|
||||
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
|
||||
| RCC_PLLCFG_PLLSRC_HSE
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
| STM32_PLLCFG_PLLR
|
||||
#endif
|
||||
);
|
||||
putreg32(regval, STM32_RCC_PLLCFG);
|
||||
|
||||
/* Enable the main PLL */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
|
|
@ -731,13 +743,31 @@ static void stm32_stdclockconfig(void)
|
|||
{
|
||||
}
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446)
|
||||
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODSWEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
|
||||
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN
|
||||
#ifdef CONFIG_STM32_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
| FLASH_ACR_PRFTEN
|
||||
#endif
|
||||
);
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
|
|
@ -753,26 +783,54 @@ static void stm32_stdclockconfig(void)
|
|||
{
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STM32_LTDC
|
||||
#if defined(CONFIG_STM32_LTDC) || \
|
||||
(defined(CONFIG_STM32_STM32F446) && defined(CONFIG_STM32_SAIPLL))
|
||||
/* Configure PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLSAICFGR);
|
||||
regval = getreg32(STM32_RCC_PLLSAICFGR);
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
regval &= ~(RCC_PLLSAICFGR_PLLSAIM_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIN_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIP_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIQ_MASK);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIM
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIP
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
|
||||
#else
|
||||
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIR_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIQ_MASK);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
|
||||
#endif
|
||||
putreg32(regval, STM32_RCC_PLLSAICFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR);
|
||||
regval = getreg32(STM32_RCC_DCKCFGR);
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
regval &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MASK
|
||||
| RCC_DCKCFGR_PLLSAIDIVQ_MASK
|
||||
| RCC_DCKCFGR_SAI1SRC_MASK
|
||||
| RCC_DCKCFGR_SAI2SRC_MASK
|
||||
| RCC_DCKCFGR_I2S1SRC_MASK
|
||||
| RCC_DCKCFGR_I2S2SRC_MASK);
|
||||
regval |= (STM32_RCC_DCKCFGR_PLLI2SDIVQ
|
||||
| STM32_RCC_DCKCFGR_PLLSAIDIVQ
|
||||
| STM32_RCC_DCKCFGR_SAI1SRC
|
||||
| STM32_RCC_DCKCFGR_SAI2SRC
|
||||
| STM32_RCC_DCKCFGR_TIMPRE
|
||||
| STM32_RCC_DCKCFGR_I2S1SRC
|
||||
| STM32_RCC_DCKCFGR_I2S2SRC);
|
||||
#else
|
||||
regval &= ~RCC_DCKCFGR_PLLSAIDIVR_MASK;
|
||||
regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
|
||||
#endif
|
||||
putreg32(regval, STM32_RCC_DCKCFGR);
|
||||
|
||||
/* Enable PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLSAION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
|
|
@ -783,6 +841,48 @@ static void stm32_stdclockconfig(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446) && defined(CONFIG_STM32_I2SPLL)
|
||||
/* Configure PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLI2SCFGR);
|
||||
regval &= ~(RCC_PLLI2SCFGR_PLLI2SM_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SN_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SP_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SQ_MASK);
|
||||
regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SM
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SN
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SP
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SQ
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
|
||||
putreg32(regval, STM32_RCC_PLLI2SCFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR2);
|
||||
regval &= ~(RCC_DCKCFGR2_FMPI2C1SEL_MASK
|
||||
| RCC_DCKCFGR2_CECSEL_MASK
|
||||
| RCC_DCKCFGR2_CK48MSEL_MASK
|
||||
| RCC_DCKCFGR2_SDIOSEL_MASK
|
||||
| RCC_DCKCFGR2_SPDIFRXSEL_MASK);
|
||||
regval |= (STM32_RCC_DCKCFGR2_FMPI2C1SEL
|
||||
| STM32_RCC_DCKCFGR2_CECSEL
|
||||
| STM32_RCC_DCKCFGR2_CK48MSEL
|
||||
| STM32_RCC_DCKCFGR2_SDIOSEL
|
||||
| STM32_RCC_DCKCFGR2_SPDIFRXSEL);
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR2);
|
||||
|
||||
/* Enable PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLI2SON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLI2S is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,826 +0,0 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32f42xxx_rcc.c
|
||||
*
|
||||
* Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "stm32_pwr.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Allow up to 100 milliseconds for the high speed clock to become ready.
|
||||
* that is a very long delay, but if the clock does not become ready we are
|
||||
* hosed anyway. Normally this is very fast, but I have seen at least one
|
||||
* board that required this long, long timeout for the HSE to be ready.
|
||||
*/
|
||||
|
||||
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
|
||||
|
||||
/* Same for HSI */
|
||||
|
||||
#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
|
||||
|
||||
/* HSE divisor to yield ~1MHz RTC clock */
|
||||
|
||||
#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_reset
|
||||
*
|
||||
* Description:
|
||||
* Reset the RCC clock configuration to the default reset state
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_reset(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable the Internal High Speed clock (HSI) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Reset CFGR register */
|
||||
|
||||
putreg32(0x00000000, STM32_RCC_CFGR);
|
||||
|
||||
/* Reset HSION, HSEON, CSSON and PLLON bits */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Reset PLLCFGR register to reset default */
|
||||
|
||||
putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG);
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~RCC_CR_HSEBYP;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0x00000000, STM32_RCC_CIR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb1
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB1 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb1(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the AHB1ENR register to enabled the
|
||||
* selected AHB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB1ENR);
|
||||
|
||||
/* Enable GPIOA, GPIOB, .... GPIOI */
|
||||
|
||||
#if STM32_NGPIO > 0
|
||||
regval |= (RCC_AHB1ENR_GPIOAEN
|
||||
#if STM32_NGPIO > 16
|
||||
| RCC_AHB1ENR_GPIOBEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 32
|
||||
| RCC_AHB1ENR_GPIOCEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 48
|
||||
| RCC_AHB1ENR_GPIODEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 64
|
||||
| RCC_AHB1ENR_GPIOEEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 80
|
||||
| RCC_AHB1ENR_GPIOFEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 96
|
||||
| RCC_AHB1ENR_GPIOGEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 112
|
||||
| RCC_AHB1ENR_GPIOHEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 128
|
||||
| RCC_AHB1ENR_GPIOIEN
|
||||
#endif
|
||||
);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CRC
|
||||
/* CRC clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_CRCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_BKPSRAM
|
||||
/* Backup SRAM clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_BKPSRAMEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CCMDATARAM
|
||||
/* CCM data RAM clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_CCMDATARAMEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_DMA1
|
||||
/* DMA 1 clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_DMA1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_DMA2
|
||||
/* DMA 2 clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_DMA2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_ETHMAC
|
||||
/* Ethernet MAC clocking */
|
||||
|
||||
regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN);
|
||||
|
||||
#ifdef CONFIG_STM32_ETH_PTP
|
||||
/* Precision Time Protocol (PTP) */
|
||||
|
||||
regval |= RCC_AHB1ENR_ETHMACPTPEN;
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_OTGHS
|
||||
/* USB OTG HS */
|
||||
|
||||
regval |= RCC_AHB1ENR_OTGHSEN;
|
||||
|
||||
#endif /* CONFIG_STM32_OTGHS */
|
||||
|
||||
#ifdef CONFIG_STM32_DMA2D
|
||||
/* DMA2D clock */
|
||||
|
||||
regval |= RCC_AHB1ENR_DMA2DEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb2
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB2 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb2(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the AHB2ENR register to enabled the
|
||||
* selected AHB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB2ENR);
|
||||
|
||||
#ifdef CONFIG_STM32_DCMI
|
||||
/* Camera interface enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_DCMIEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CRYP
|
||||
/* Cryptographic modules clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_CRYPEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_HASH
|
||||
/* Hash modules clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_HASHEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_RNG
|
||||
/* Random number generator clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_RNGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_OTGFS
|
||||
/* USB OTG FS clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_OTGFSEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb3
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB3 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb3(void)
|
||||
{
|
||||
#ifdef CONFIG_STM32_FSMC
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the AHB3ENR register to enabled the
|
||||
* selected AHB3 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB3ENR);
|
||||
|
||||
/* Flexible static memory controller module clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_FSMCEN;
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb1
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB1 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb1(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB1ENR register to enabled the
|
||||
* selected APB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
|
||||
#ifdef CONFIG_STM32_TIM2
|
||||
/* TIM2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM3
|
||||
/* TIM3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM4
|
||||
/* TIM4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM5
|
||||
/* TIM5 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM6
|
||||
/* TIM6 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM6EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM7
|
||||
/* TIM7 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM7EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM12
|
||||
/* TIM12 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM12EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM13
|
||||
/* TIM13 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM13EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM14
|
||||
/* TIM14 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM14EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_WWDG
|
||||
/* Window watchdog clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_WWDGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI2
|
||||
/* SPI2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_SPI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI3
|
||||
/* SPI3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_SPI3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_USART2
|
||||
/* USART 2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_USART2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_USART3
|
||||
/* USART3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_USART3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_UART4
|
||||
/* UART4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_UART5
|
||||
/* UART5 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_I2C1
|
||||
/* I2C1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_I2C2
|
||||
/* I2C2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_I2C3
|
||||
/* I2C3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CAN1
|
||||
/* CAN 1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_CAN1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CAN2
|
||||
/* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */
|
||||
|
||||
regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN);
|
||||
#endif
|
||||
|
||||
/* Power interface clock enable. The PWR block is always enabled so that
|
||||
* we can set the internal voltage regulator for maximum performance.
|
||||
*/
|
||||
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
|
||||
#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
|
||||
/* DAC interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_DACEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_UART7
|
||||
/* UART7 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART7EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_UART8
|
||||
/* UART8 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART8EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb2
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB2 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb2(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB2ENR register to enabled the
|
||||
* selected APB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB2ENR);
|
||||
|
||||
#ifdef CONFIG_STM32_TIM1
|
||||
/* TIM1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM8
|
||||
/* TIM8 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM8EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_USART1
|
||||
/* USART1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_USART1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_USART6
|
||||
/* USART6 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_USART6EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_ADC1
|
||||
/* ADC1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_ADC2
|
||||
/* ADC2 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_ADC3
|
||||
/* ADC3 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SDIO
|
||||
/* SDIO clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SDIOEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI1
|
||||
/* SPI1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI4
|
||||
/* SPI4 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SYSCFG
|
||||
/* System configuration controller clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM9
|
||||
/* TIM9 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM9EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM10
|
||||
/* TIM10 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM10EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM11
|
||||
/* TIM11 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM11EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI5
|
||||
/* SPI5 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI6
|
||||
/* SPI6 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI6EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_LTDC
|
||||
/* LTDC clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_LTDCEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_stdclockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to change to new clock based on settings in board.h
|
||||
*
|
||||
* NOTE: This logic would need to be extended if you need to select low-
|
||||
* power clocking modes!
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
|
||||
static void stm32_stdclockconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
volatile int32_t timeout;
|
||||
|
||||
#ifdef STM32_BOARD_USEHSI
|
||||
/* Enable Internal High-Speed Clock (HSI) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSION; /* Enable HSI */
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSI is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSIRDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#else /* if STM32_BOARD_USEHSE */
|
||||
/* Enable External High-Speed Clock (HSE) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSEON; /* Enable HSE */
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSE is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSERDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Check for a timeout. If this timeout occurs, then we are hosed. We
|
||||
* have no real back-up plan, although the following logic makes it look
|
||||
* as though we do.
|
||||
*/
|
||||
|
||||
if (timeout > 0)
|
||||
{
|
||||
/* Select regulator voltage output Scale 1 mode to support system
|
||||
* frequencies up to 168 MHz.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval &= ~PWR_CR_VOS_MASK;
|
||||
regval |= PWR_CR_VOS_SCALE_1;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_HPRE_MASK;
|
||||
regval |= STM32_RCC_CFGR_HPRE;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK2 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE2_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE2;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK1 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE1_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
#ifdef CONFIG_RTC_HSECLOCK
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_RTCPRE_MASK;
|
||||
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
#endif
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
#ifdef STM32_BOARD_USEHSI
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
|
||||
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
|
||||
#else /* if STM32_BOARD_USEHSE */
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
|
||||
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
|
||||
#endif
|
||||
putreg32(regval, STM32_RCC_PLLCFG);
|
||||
|
||||
/* Enable the main PLL */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F429)
|
||||
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODSWEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
|
||||
|
||||
#ifdef CONFIG_STM32_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
#endif
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_SW_MASK;
|
||||
regval |= RCC_CFGR_SW_PLL;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STM32_LTDC
|
||||
/* Configure PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLSAICFGR);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
|
||||
putreg32(regval, STM32_RCC_PLLSAICFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR);
|
||||
regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
|
||||
putreg32(regval, STM32_RCC_DCKCFGR);
|
||||
|
||||
/* Enable PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLSAION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLSAI is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
stm32_rcc_enablelsi();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTC_LSECLOCK)
|
||||
/* Low speed external clock source LSE
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if the MCO1 pin selects LSE as source.
|
||||
*/
|
||||
|
||||
stm32_rcc_enablelse();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableperiphals
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableperipherals(void)
|
||||
{
|
||||
rcc_enableahb1();
|
||||
rcc_enableahb2();
|
||||
rcc_enableahb3();
|
||||
rcc_enableapb1();
|
||||
rcc_enableapb2();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
@ -1,819 +0,0 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32f44xxx_rcc.c
|
||||
*
|
||||
* Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "stm32_pwr.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Allow up to 100 milliseconds for the high speed clock to become ready.
|
||||
* that is a very long delay, but if the clock does not become ready we are
|
||||
* hosed anyway. Normally this is very fast, but I have seen at least one
|
||||
* board that required this long, long timeout for the HSE to be ready.
|
||||
*/
|
||||
|
||||
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
|
||||
|
||||
/* Same for HSI */
|
||||
|
||||
#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
|
||||
|
||||
/* HSE divisor to yield ~1MHz RTC clock */
|
||||
|
||||
#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_reset
|
||||
*
|
||||
* Description:
|
||||
* Reset the RCC clock configuration to the default reset state
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_reset(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable the Internal High Speed clock (HSI) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Reset CFGR register */
|
||||
|
||||
putreg32(0x00000000, STM32_RCC_CFGR);
|
||||
|
||||
/* Reset HSION, HSEON, CSSON and PLLON bits */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Reset PLLCFGR register to reset default */
|
||||
|
||||
putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG);
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~RCC_CR_HSEBYP;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0x00000000, STM32_RCC_CIR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb1
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB1 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb1(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the AHB1ENR register to enabled the
|
||||
* selected AHB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB1ENR);
|
||||
|
||||
/* Enable GPIOA, GPIOB, .... GPIOI */
|
||||
|
||||
#if STM32_NGPIO > 0
|
||||
regval |= (RCC_AHB1ENR_GPIOAEN
|
||||
#if STM32_NGPIO > 16
|
||||
| RCC_AHB1ENR_GPIOBEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 32
|
||||
| RCC_AHB1ENR_GPIOCEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 48
|
||||
| RCC_AHB1ENR_GPIODEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 64
|
||||
| RCC_AHB1ENR_GPIOEEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 80
|
||||
| RCC_AHB1ENR_GPIOFEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 96
|
||||
| RCC_AHB1ENR_GPIOGEN
|
||||
#endif
|
||||
#if STM32_NGPIO > 112
|
||||
| RCC_AHB1ENR_GPIOHEN
|
||||
#endif
|
||||
);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CRC
|
||||
/* CRC clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_CRCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_BKPSRAM
|
||||
/* Backup SRAM clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_BKPSRAMEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_DMA1
|
||||
/* DMA 1 clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_DMA1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_DMA2
|
||||
/* DMA 2 clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_DMA2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_OTGHS
|
||||
/* USB OTG HS */
|
||||
|
||||
regval |= RCC_AHB1ENR_OTGHSEN;
|
||||
|
||||
#endif /* CONFIG_STM32_OTGHS */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb2
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB2 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb2(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the AHB2ENR register to enabled the
|
||||
* selected AHB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB2ENR);
|
||||
|
||||
#ifdef CONFIG_STM32_DCMI
|
||||
/* Camera interface enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_DCMIEN;
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32_RNG
|
||||
/* Random number generator clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_RNGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_OTGFS
|
||||
/* USB OTG FS clock enable */
|
||||
|
||||
regval |= RCC_AHB2ENR_OTGFSEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb3
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB3 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb3(void)
|
||||
{
|
||||
#ifdef CONFIG_STM32_FSMC
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the AHB3ENR register to enabled the
|
||||
* selected AHB3 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB3ENR);
|
||||
|
||||
/* Flexible static memory controller module clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_FSMCEN;
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb1
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB1 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb1(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB1ENR register to enabled the
|
||||
* selected APB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
|
||||
#ifdef CONFIG_STM32_TIM2
|
||||
/* TIM2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM3
|
||||
/* TIM3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM4
|
||||
/* TIM4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM5
|
||||
/* TIM5 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM6
|
||||
/* TIM6 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM6EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM7
|
||||
/* TIM7 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM7EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM12
|
||||
/* TIM12 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM12EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM13
|
||||
/* TIM13 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM13EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM14
|
||||
/* TIM14 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM14EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_WWDG
|
||||
/* Window watchdog clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_WWDGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI2
|
||||
/* SPI2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_SPI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI3
|
||||
/* SPI3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_SPI3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_USART2
|
||||
/* USART 2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_USART2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_USART3
|
||||
/* USART3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_USART3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_UART4
|
||||
/* UART4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_UART5
|
||||
/* UART5 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_I2C1
|
||||
/* I2C1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_I2C2
|
||||
/* I2C2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_I2C3
|
||||
/* I2C3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CAN1
|
||||
/* CAN 1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_CAN1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CAN2
|
||||
/* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */
|
||||
|
||||
regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN);
|
||||
#endif
|
||||
|
||||
/* Power interface clock enable. The PWR block is always enabled so that
|
||||
* we can set the internal voltage regulator for maximum performance.
|
||||
*/
|
||||
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
|
||||
#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
|
||||
/* DAC interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_DACEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb2
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB2 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb2(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB2ENR register to enabled the
|
||||
* selected APB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB2ENR);
|
||||
|
||||
#ifdef CONFIG_STM32_TIM1
|
||||
/* TIM1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM8
|
||||
/* TIM8 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM8EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_USART1
|
||||
/* USART1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_USART1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_USART6
|
||||
/* USART6 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_USART6EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_ADC1
|
||||
/* ADC1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_ADC2
|
||||
/* ADC2 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_ADC3
|
||||
/* ADC3 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SDIO
|
||||
/* SDIO clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SDIOEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI1
|
||||
/* SPI1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI4
|
||||
/* SPI4 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SYSCFG
|
||||
/* System configuration controller clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM9
|
||||
/* TIM9 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM9EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM10
|
||||
/* TIM10 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM10EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM11
|
||||
/* TIM11 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM11EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_stdclockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to change to new clock based on settings in board.h
|
||||
*
|
||||
* NOTE: This logic would need to be extended if you need to select low-
|
||||
* power clocking modes!
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
|
||||
static void stm32_stdclockconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
volatile int32_t timeout;
|
||||
|
||||
#ifdef STM32_BOARD_USEHSI
|
||||
/* Enable Internal High-Speed Clock (HSI) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSION; /* Enable HSI */
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSI is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSIRDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#else /* if STM32_BOARD_USEHSE */
|
||||
/* Enable External High-Speed Clock (HSE) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSEON; /* Enable HSE */
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSE is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSERDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Check for a timeout. If this timeout occurs, then we are hosed. We
|
||||
* have no real back-up plan, although the following logic makes it look
|
||||
* as though we do.
|
||||
*/
|
||||
|
||||
if (timeout > 0)
|
||||
{
|
||||
/* Select regulator voltage output Scale 1 mode to support system
|
||||
* frequencies up to 180 MHz with Over Drive.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval &= ~PWR_CR_VOS_MASK;
|
||||
regval |= PWR_CR_VOS_SCALE_1;
|
||||
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_HPRE_MASK;
|
||||
regval |= STM32_RCC_CFGR_HPRE;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK2 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE2_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE2;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK1 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE1_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
#ifdef CONFIG_RTC_HSECLOCK
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_RTCPRE_MASK;
|
||||
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
#endif
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
#ifdef STM32_BOARD_USEHSI
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
|
||||
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR);
|
||||
#else /* if STM32_BOARD_USEHSE */
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
|
||||
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR);
|
||||
#endif
|
||||
putreg32(regval, STM32_RCC_PLLCFG);
|
||||
|
||||
/* Enable the main PLL */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODSWEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
|
||||
|
||||
#ifdef CONFIG_STM32_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
#endif
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_SW_MASK;
|
||||
regval |= RCC_CFGR_SW_PLL;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
#if defined(CONFIG_STM32_SAIPLL)
|
||||
|
||||
/* Configure PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLSAICFGR);
|
||||
regval &= ~(RCC_PLLSAICFGR_PLLSAIM_MASK |
|
||||
RCC_PLLSAICFGR_PLLSAIN_MASK |
|
||||
RCC_PLLSAICFGR_PLLSAIP_MASK |
|
||||
RCC_PLLSAICFGR_PLLSAIQ_MASK);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIM
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIP
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
|
||||
putreg32(regval, STM32_RCC_PLLSAICFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR);
|
||||
regval &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MASK |
|
||||
RCC_DCKCFGR_PLLSAIDIVQ_MASK |
|
||||
RCC_DCKCFGR_SAI1SRC_MASK |
|
||||
RCC_DCKCFGR_SAI2SRC_MASK |
|
||||
RCC_DCKCFGR_I2S1SRC_MASK |
|
||||
RCC_DCKCFGR_I2S2SRC_MASK);
|
||||
|
||||
regval |= (STM32_RCC_DCKCFGR_PLLI2SDIVQ
|
||||
| STM32_RCC_DCKCFGR_PLLSAIDIVQ
|
||||
| STM32_RCC_DCKCFGR_SAI1SRC
|
||||
| STM32_RCC_DCKCFGR_SAI2SRC
|
||||
| STM32_RCC_DCKCFGR_TIMPRE
|
||||
| STM32_RCC_DCKCFGR_I2S1SRC
|
||||
| STM32_RCC_DCKCFGR_I2S2SRC);
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR);
|
||||
|
||||
/* Enable PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLSAION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLSAI is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_I2SPLL)
|
||||
|
||||
/* Configure PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLI2SCFGR);
|
||||
regval &= ~(RCC_PLLI2SCFGR_PLLI2SM_MASK |
|
||||
RCC_PLLI2SCFGR_PLLI2SN_MASK |
|
||||
RCC_PLLI2SCFGR_PLLI2SP_MASK |
|
||||
RCC_PLLI2SCFGR_PLLI2SQ_MASK);
|
||||
regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SM
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SN
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SP
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SQ
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
|
||||
putreg32(regval, STM32_RCC_PLLI2SCFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR2);
|
||||
regval &= ~(RCC_DCKCFGR2_FMPI2C1SEL_MASK |
|
||||
RCC_DCKCFGR2_CECSEL_MASK |
|
||||
RCC_DCKCFGR2_CK48MSEL_MASK |
|
||||
RCC_DCKCFGR2_SDIOCSEL_MASK |
|
||||
RCC_DCKCFGR2_SPDIFRXEL_MASK);
|
||||
regval |= (STM32_RCC_DCKCFGR2_FMPI2C1SEL
|
||||
| STM32_RCC_DCKCFGR2_CECSEL
|
||||
| STM32_RCC_DCKCFGR2_CK48MSEL
|
||||
| STM32_RCC_DCKCFGR2_SDIOCSEL
|
||||
| STM32_RCC_DCKCFGR2_SPDIFRXEL);
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR2);
|
||||
|
||||
/* Enable PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLI2SON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLI2S is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
stm32_rcc_enablelsi();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTC_LSECLOCK)
|
||||
/* Low speed external clock source LSE
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if the MCO1 pin selects LSE as source.
|
||||
*/
|
||||
|
||||
stm32_rcc_enablelse();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableperiphals
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableperipherals(void)
|
||||
{
|
||||
rcc_enableahb1();
|
||||
rcc_enableahb2();
|
||||
rcc_enableahb3();
|
||||
rcc_enableapb1();
|
||||
rcc_enableapb2();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
Loading…
Add table
Reference in a new issue