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Squashed commit of the following:

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Fixed coding standard error in several files.  Use of while( is incorrect; a space is required between while and (.  Also ran tools/nxstyle and fix thoses complaints as well in most files.

    Changes to comply with coding standard.  Mostly focused on files with missing space after keyword in if(, switch(, and for(.  Offending files also got changes to comply with tools nxstyle.  If there were logs of nxstyle complaints, the file also got a taste of tools/indent.sh.  Still need to fix occurrences of while( with missing space.  There are a lot of them.
This commit is contained in:
Gregory Nutt 2019-02-27 08:41:08 -06:00
parent c664ed01ec
commit dc8c814ca3
68 changed files with 2687 additions and 2179 deletions
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4
arch/arm/src/am335x/am335x_wdog.c
View file

@ -59,12 +59,12 @@
void am335x_wdog_disable_all(void)
{
putreg32(WDT_WSPR_STOP_FEED_A, AM335X_WDT_WSPR);
while((getreg32(AM335X_WDT_WWPS) & WDT_WWPS_W_PEND_WSPR) != 0)
while ((getreg32(AM335X_WDT_WWPS) & WDT_WWPS_W_PEND_WSPR) != 0)
{
}
putreg32(WDT_WSPR_STOP_FEED_B, AM335X_WDT_WSPR);
while((getreg32(AM335X_WDT_WWPS) & WDT_WWPS_W_PEND_WSPR) != 0)
while ((getreg32(AM335X_WDT_WWPS) & WDT_WWPS_W_PEND_WSPR) != 0)
{
}
}

94
arch/arm/src/kinetis/kinetis_i2c.c
View file

@ -184,7 +184,7 @@ static const struct i2c_ops_s kinetis_i2c_ops =
{
.transfer = kinetis_i2c_transfer
#ifdef CONFIG_I2C_RESET
,.reset = kinetis_i2c_reset
, .reset = kinetis_i2c_reset
#endif
};
@ -306,13 +306,13 @@ static void kinetis_i2c_putreg(struct kinetis_i2cdev_s *priv, uint8_t value,
putreg8(value, priv->config->base + offset);
}
/************************************************************************************
/****************************************************************************
* Name: kinetis_i2c_sem_init
*
* Description:
* Initialize semaphores
*
************************************************************************************/
****************************************************************************/
static inline void kinetis_i2c_sem_init(FAR struct kinetis_i2cdev_s *priv)
{
@ -326,13 +326,13 @@ static inline void kinetis_i2c_sem_init(FAR struct kinetis_i2cdev_s *priv)
nxsem_setprotocol(&priv->wait, SEM_PRIO_NONE);
}
/************************************************************************************
/****************************************************************************
* Name: kinetis_i2c_sem_destroy
*
* Description:
* Destroy semaphores.
*
************************************************************************************/
****************************************************************************/
static inline void kinetis_i2c_sem_destroy(FAR struct kinetis_i2cdev_s *priv)
{
@ -340,13 +340,13 @@ static inline void kinetis_i2c_sem_destroy(FAR struct kinetis_i2cdev_s *priv)
nxsem_destroy(&priv->wait);
}
/************************************************************************************
/****************************************************************************
* Name: kinetis_i2c_sem_wait
*
* Description:
* Take the exclusive access, waiting as necessary
*
************************************************************************************/
****************************************************************************/
static inline void kinetis_i2c_sem_wait(FAR struct kinetis_i2cdev_s *priv)
{
@ -367,52 +367,52 @@ static inline void kinetis_i2c_sem_wait(FAR struct kinetis_i2cdev_s *priv)
while (ret == -EINTR);
}
/************************************************************************************
/****************************************************************************
* Name: kinetis_i2c_sem_post
*
* Description:
* Release the mutual exclusion semaphore
*
************************************************************************************/
****************************************************************************/
static inline void kinetis_i2c_sem_post(struct kinetis_i2cdev_s *priv)
{
nxsem_post(&priv->mutex);
}
/************************************************************************************
/****************************************************************************
* Name: kinetis_i2c_wait
*
* Description:
* Wait on the signaling semaphore
*
************************************************************************************/
****************************************************************************/
static inline void kinetis_i2c_wait(struct kinetis_i2cdev_s *priv)
{
(void)nxsem_wait(&priv->wait);
}
/************************************************************************************
/****************************************************************************
* Name: kinetis_i2c_endwait
*
* Description:
* Release the signaling semaphore
*
************************************************************************************/
****************************************************************************/
static inline void kinetis_i2c_endwait(struct kinetis_i2cdev_s *priv)
{
nxsem_post(&priv->wait);
}
/************************************************************************************
/****************************************************************************
* Name: kinetis_i2c_init
*
* Description:
* Setup the I2C hardware, ready for operation with defaults
*
************************************************************************************/
****************************************************************************/
static int kinetis_i2c_init(FAR struct kinetis_i2cdev_s *priv)
{
@ -467,13 +467,13 @@ static int kinetis_i2c_init(FAR struct kinetis_i2cdev_s *priv)
return OK;
}
/************************************************************************************
/****************************************************************************
* Name: kinetis_i2c_deinit
*
* Description:
* Shutdown the I2C hardware
*
************************************************************************************/
****************************************************************************/
static int kinetis_i2c_deinit(FAR struct kinetis_i2cdev_s *priv)
{
@ -733,7 +733,7 @@ static void kinetis_i2c_setfrequency(struct kinetis_i2cdev_s *priv,
kinetis_i2c_putreg(priv, I2C_F_DIV64, KINETIS_I2C_F_OFFSET); /* 375 kHz */
}
else
{161
{
kinetis_i2c_putreg(priv, I2C_F_DIV24, KINETIS_I2C_F_OFFSET); /* 1 MHz */
}
@ -813,7 +813,8 @@ static int kinetis_i2c_start(struct kinetis_i2cdev_s *priv)
/* We are already the bus master, so send a repeated start */
kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST |
I2C_C1_RSTA | I2C_C1_TX, KINETIS_I2C_C1_OFFSET);
I2C_C1_RSTA | I2C_C1_TX,
KINETIS_I2C_C1_OFFSET);
}
else
{
@ -833,7 +834,8 @@ static int kinetis_i2c_start(struct kinetis_i2cdev_s *priv)
/* Become the bus master in transmit mode (send start) */
kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST |
I2C_C1_TX, KINETIS_I2C_C1_OFFSET);
I2C_C1_TX,
KINETIS_I2C_C1_OFFSET);
}
if (I2C_M_READ & msg->flags) /* DEBUG: should happen always */
@ -844,7 +846,8 @@ static int kinetis_i2c_start(struct kinetis_i2cdev_s *priv)
start = clock_systimer();
while ((kinetis_i2c_getreg(priv, KINETIS_I2C_S_OFFSET) & I2C_S_BUSY) == 0)
while ((kinetis_i2c_getreg(priv, KINETIS_I2C_S_OFFSET) & I2C_S_BUSY)
== 0)
{
if (clock_systimer() - start > I2C_TIMEOUT)
{
@ -1098,7 +1101,8 @@ static int kinetis_i2c_interrupt(int irq, void *context, void *arg)
/* Do not ACK any more */
kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
I2C_C1_MST | I2C_C1_TXAK, KINETIS_I2C_C1_OFFSET);
I2C_C1_MST | I2C_C1_TXAK,
KINETIS_I2C_C1_OFFSET);
}
msg->buffer[priv->rdcnt] =
@ -1168,7 +1172,7 @@ static int kinetis_i2c_transfer(struct i2c_master_s *dev,
if (priv->nmsg > 1)
{
struct i2c_msg_s* nextmsg = (priv->msgs + 1);
struct i2c_msg_s *nextmsg = (priv->msgs + 1);
/* If there is a following message with "norestart" flag of
* the same type as the current one, we can avoid the restart
@ -1177,7 +1181,8 @@ static int kinetis_i2c_transfer(struct i2c_master_s *dev,
if ((nextmsg->flags & I2C_M_NOSTART) &&
nextmsg->addr == priv->msgs->addr &&
nextmsg->frequency == priv->msgs->frequency &&
(nextmsg->flags & I2C_M_READ) == (priv->msgs->flags & I2C_M_READ))
(nextmsg->flags & I2C_M_READ) ==
(priv->msgs->flags & I2C_M_READ))
{
/* "no restart" can be performed */
@ -1222,7 +1227,7 @@ timeout:
return (priv->state != STATE_OK) ? -EIO : 0;
}
/************************************************************************************
/****************************************************************************
* Name: kinetis_i2c_reset
*
* Description:
@ -1234,7 +1239,7 @@ timeout:
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int kinetis_i2c_reset(struct i2c_master_s *dev)
@ -1372,31 +1377,36 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port)
i2cinfo("port=%d\n", port);
switch(port)
switch (port)
{
#ifdef CONFIG_KINETIS_I2C0
case 0:
priv = &g_i2c0_dev;
break;
case 0:
priv = &g_i2c0_dev;
break;
#endif
#ifdef CONFIG_KINETIS_I2C1
case 1:
priv = &g_i2c1_dev;
break;
case 1:
priv = &g_i2c1_dev;
break;
#endif
#ifdef CONFIG_KINETIS_I2C2
case 2:
priv = &g_i2c2_dev;
break;
case 2:
priv = &g_i2c2_dev;
break;
#endif
#ifdef CONFIG_KINETIS_I2C3
case 3:
priv = &g_i2c3_dev;
break;
case 3:
priv = &g_i2c3_dev;
break;
#endif
default:
i2cerr("ERROR: Kinetis I2C Only suppors ports 0 and %d\n", KINETIS_NI2C-1);
return NULL;
default:
i2cerr("ERROR: Kinetis I2C Only suppors ports 0 and %d\n",
KINETIS_NI2C - 1);
return NULL;
}
flags = enter_critical_section();

35
arch/arm/src/kinetis/kinetis_lpserial.c
View file

@ -72,6 +72,7 @@
****************************************************************************/
/* Some sanity checks *******************************************************/
/* Is there at least one LPUART enabled and configured as a RS-232 device? */
#ifndef HAVE_LPUART_DEVICE
@ -202,7 +203,6 @@
#define LPUART_STAT_ERRORS (LPUART_STAT_OR | LPUART_STAT_FE | \
LPUART_STAT_PF | LPUART_STAT_NF)
/* The LPUART does not have an common set of aligned bits for the interrupt
* enable and the status. So map the ctrl to the stat bits
*/
@ -253,8 +253,8 @@ static int kinetis_receive(struct uart_dev_s *dev, uint32_t *status);
static void kinetis_rxint(struct uart_dev_s *dev, bool enable);
static bool kinetis_rxavailable(struct uart_dev_s *dev);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool kinetis_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
bool upper);
static bool kinetis_rxflowcontrol(struct uart_dev_s *dev,
unsigned int nbuffered, bool upper);
#endif
static void kinetis_send(struct uart_dev_s *dev, int ch);
static void kinetis_txint(struct uart_dev_s *dev, bool enable);
@ -751,7 +751,8 @@ static int kinetis_interrupt(int irq, void *context, void *arg)
/* Reset any Errors */
kinetis_serialout(priv, KINETIS_LPUART_STAT_OFFSET, stat & LPUART_STAT_ERRORS);
kinetis_serialout(priv, KINETIS_LPUART_STAT_OFFSET,
stat & LPUART_STAT_ERRORS);
return OK;
}
@ -786,7 +787,8 @@ static int kinetis_interrupt(int irq, void *context, void *arg)
stat = kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET);
ctrl = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET);
stat &= LPUART_CTRL2STAT(ctrl);
} while(stat != 0);
}
while (stat != 0);
return OK;
}
@ -1047,9 +1049,9 @@ static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg)
* Name: kinetis_receive
*
* Description:
* Called (usually) from the interrupt level to receive one
* character from the LPUART. Error bits associated with the
* receipt are provided in the return 'status'.
* Called (usually) from the interrupt level to receive one character from
* the LPUART. Error bits associated with the receipt are provided in the
* return 'status'.
*
****************************************************************************/
@ -1140,10 +1142,10 @@ static bool kinetis_rxavailable(struct uart_dev_s *dev)
{
struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv;
/* Return true if the receive data register is full (RDRF).
*/
/* Return true if the receive data register is full (RDRF). */
return (kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET) & LPUART_STAT_RDRF) != 0;
return (kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET) &
LPUART_STAT_RDRF) != 0;
}
/****************************************************************************
@ -1206,8 +1208,8 @@ static bool kinetis_rxflowcontrol(struct uart_dev_s *dev,
else
{
/* We might leave Rx interrupt disabled if full recv buffer was
* read empty. Enable Rx interrupt to make sure that more input is
* received.
* read empty. Enable Rx interrupt to make sure that more input
* is received.
*/
kinetis_rxint(dev, true);
@ -1287,7 +1289,8 @@ static bool kinetis_txready(struct uart_dev_s *dev)
/* Return true if the transmit data register is "empty." */
return (kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) != 0;
return (kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) != 0;
}
/****************************************************************************
@ -1301,8 +1304,8 @@ static bool kinetis_txready(struct uart_dev_s *dev)
* Performs the low level LPUART initialization early in debug so that the
* serial console will be available during bootup. This must be called
* before up_serialinit. NOTE: This function depends on GPIO pin
* configuration performed in kinetis_lowsetup() and main clock initialization
* performed in up_clkinitialize().
* configuration performed in kinetis_lowsetup() and main clock
* initialization performed in up_clkinitialize().
*
****************************************************************************/

204
arch/arm/src/lc823450/lc823450_usbdev.c
View file

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lc823450/lc823450_usbdev.c
*
* Copyright 2014,2015,2016,2017 Sony Video & Sound Products Inc.
* Copyright 2014, 2015, 2016, 2017 Sony Video & Sound Products Inc.
* Author: Masatoshi Tateishi <Masatoshi.Tateishi@jp.sony.com>
* Author: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
*
@ -100,7 +100,7 @@
#if 0
# define DPRINTF(fmt, args...) uinfo(fmt, ##args)
#else
# define DPRINTF(fmt, args...) do {} while(0)
# define DPRINTF(fmt, args...) do {} while (0)
#endif
#ifndef container_of
@ -155,9 +155,9 @@ struct lc823450_usbdev_s
#endif /* CONFIG_USBDEV_CHARGER */
};
/*******************************************************************************
/****************************************************************************
* Private Functions
*******************************************************************************/
****************************************************************************/
static void lc823450_epack(int epnum, bool ack);
static int epbuf_write(int epnum, void *buf, size_t len);
@ -173,11 +173,13 @@ static void lc823450_epfreereq(struct usbdev_ep_s *ep,
static void *lc823450_epallocbuffer(struct usbdev_ep_s *ep, uint16_t bytes);
static void lc823450_epfreebuffer(struct usbdev_ep_s *ep, void *buf);
#endif /* CONFIG_USBDEV_DMA */
static int lc823450_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req);
static int lc823450_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req);
static int lc823450_epsubmit(struct usbdev_ep_s *ep,
struct usbdev_req_s *req);
static int lc823450_epcancel(struct usbdev_ep_s *ep,
struct usbdev_req_s *req);
static int lc823450_epstall(struct usbdev_ep_s *ep, bool resume);
static struct usbdev_ep_s *lc823450_allocep(struct usbdev_s *dev, uint8_t eplog,
bool in, uint8_t eptype);
static struct usbdev_ep_s *lc823450_allocep(struct usbdev_s *dev,
uint8_t eplog, bool in, uint8_t eptype);
static void lc823450_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep);
static int lc823450_getframe(struct usbdev_s *dev);
static int lc823450_wakeup(struct usbdev_s *dev);
@ -192,22 +194,27 @@ static void usb_reset_work_func(void *arg);
#endif
/****************************************************************************
* Private Data
* Public Function Prototypes
****************************************************************************/
static struct lc823450_usbdev_s g_usbdev;
static DMA_HANDLE hdma;
sem_t dma_wait;
struct lc823450_dma_llist dma_list[16];
#ifdef CONFIG_DVFS
#define DVFS_BOOST_TIMEOUT (200) /* 200ms */
extern int lc823450_dvfs_boost(int timeout);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
static struct lc823450_usbdev_s g_usbdev;
static DMA_HANDLE hdma;
static sem_t dma_wait;
static struct lc823450_dma_llist dma_list[16];
#ifdef CONFIG_PM
static void usbdev_pmnotify(struct pm_callback_s *cb, enum pm_state_e pmstate);
static void usbdev_pmnotify(struct pm_callback_s *cb,
enum pm_state_e pmstate);
static struct pm_callback_s pm_cb =
{
.notify = usbdev_pmnotify,
@ -251,13 +258,13 @@ static struct work_s usb_suspend_work;
* Private Functions
****************************************************************************/
/******************************************************************************
/****************************************************************************
* Name: lc823450_epack
*
* Description:
* ACK or NAK and endpoint
*
******************************************************************************/
****************************************************************************/
static void lc823450_epack(int epnum, bool ack)
{
@ -277,13 +284,13 @@ static void lc823450_epack(int epnum, bool ack)
epcmd_write(epnum, (privep->epcmd));
}
/******************************************************************************
/****************************************************************************
* Name: epbuf_read
*
* Description:
* read from RX Endpoint Buffer
*
******************************************************************************/
****************************************************************************/
int epbuf_read(int epnum, void *buf, size_t len)
{
@ -307,18 +314,20 @@ int epbuf_read(int epnum, void *buf, size_t len)
return len;
}
/******************************************************************************
/****************************************************************************
* Name: epbuf_write
*
* Description:
* Write to TX Endpoint Buffer
*
******************************************************************************/
****************************************************************************/
static int epbuf_write(int epnum, void *buf, size_t len)
{
struct lc823450_ep_s *privep;
int bufidx, txn, total;
int bufidx;
int txn;
int total;
int tout = 0;
total = len;
@ -338,11 +347,11 @@ cont:
}
else
{
while (!(getreg32(USB_EPCTRL(epnum)) & USB_EPCTRL_EMPTY) &&
!privep->disable && tout++ < 1000000)
{
up_udelay(1);
}
while (!(getreg32(USB_EPCTRL(epnum)) & USB_EPCTRL_EMPTY) &&
!privep->disable && tout++ < 1000000)
{
up_udelay(1);
}
}
txn = MIN(len, privep->ep.maxpacket);
@ -354,6 +363,7 @@ cont:
lc823450_epack(epnum, true);
epcmd_write(epnum, USB_EPCMD_NACK_CLR);
len -= txn;
buf += txn;
if (len > 0)
@ -364,13 +374,13 @@ cont:
return total;
}
/******************************************************************************
/****************************************************************************
* Name: epcmd_write
*
* Description:
* Write to EP command register
*
******************************************************************************/
****************************************************************************/
static void epcmd_write(int epnum, uint32_t val)
{
@ -379,7 +389,7 @@ static void epcmd_write(int epnum, uint32_t val)
putreg32(val, USB_EPCMD(epnum));
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_epconfigure
*
* Description:
@ -392,7 +402,7 @@ static void epcmd_write(int epnum, uint32_t val)
* needs to take special action when all of the endpoints have been
* configured.
*
******************************************************************************/
****************************************************************************/
static int lc823450_epconfigure(struct usbdev_ep_s *ep,
const struct usb_epdesc_s *desc,
@ -474,13 +484,13 @@ static int lc823450_epconfigure(struct usbdev_ep_s *ep,
return 0;
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_epdisable
*
* Description:
* The endpoint will no longer be used
*
******************************************************************************/
****************************************************************************/
static int lc823450_epclearreq(struct usbdev_ep_s *ep)
{
@ -508,13 +518,13 @@ static int lc823450_epclearreq(struct usbdev_ep_s *ep)
return 0;
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_epdisable
*
* Description:
* The endpoint will no longer be used
*
******************************************************************************/
****************************************************************************/
static int lc823450_epdisable(struct usbdev_ep_s *ep)
{
@ -545,13 +555,13 @@ static int lc823450_epdisable(struct usbdev_ep_s *ep)
return lc823450_epclearreq(ep);
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_epallocreq
*
* Description:
* Allocate an I/O request
*
******************************************************************************/
****************************************************************************/
static struct usbdev_req_s *lc823450_epallocreq(struct usbdev_ep_s *ep)
{
@ -567,7 +577,9 @@ static struct usbdev_req_s *lc823450_epallocreq(struct usbdev_ep_s *ep)
usbtrace(TRACE_EPALLOCREQ, ((struct lc823450_ep_s *)ep)->epphy);
privreq = (struct lc823450_req_s *)kmm_malloc(sizeof(struct lc823450_req_s));
privreq = (struct lc823450_req_s *)
kmm_malloc(sizeof(struct lc823450_req_s));
if (!privreq)
{
usbtrace(TRACE_DEVERROR(LC823450_TRACEERR_ALLOCFAIL), 0);
@ -578,15 +590,16 @@ static struct usbdev_req_s *lc823450_epallocreq(struct usbdev_ep_s *ep)
return &privreq->req;
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_epfreereq
*
* Description:
* Free an I/O request
*
******************************************************************************/
****************************************************************************/
static void lc823450_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
static void lc823450_epfreereq(struct usbdev_ep_s *ep,
struct usbdev_req_s *req)
{
struct lc823450_req_s *privreq = (struct lc823450_req_s *)req;
@ -603,13 +616,13 @@ static void lc823450_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
}
#ifdef CONFIG_USBDEV_DMA
/******************************************************************************
/****************************************************************************
* Name: lc823450_epallocbuffer
*
* Description:
* Allocate an I/O buffer
*
******************************************************************************/
****************************************************************************/
static void *lc823450_epallocbuffer(struct usbdev_ep_s *ep, uint16_t bytes)
{
@ -624,13 +637,13 @@ static void *lc823450_epallocbuffer(struct usbdev_ep_s *ep, uint16_t bytes)
#endif
#ifdef CONFIG_USBDEV_DMA
/******************************************************************************
/****************************************************************************
* Name: lc823450_epfreebuffer
*
* Description:
* Free an I/O buffer
*
******************************************************************************/
****************************************************************************/
static void lc823450_epfreebuffer(struct usbdev_ep_s *ep, void *buf)
{
@ -644,13 +657,13 @@ static void lc823450_epfreebuffer(struct usbdev_ep_s *ep, void *buf)
}
#endif
/******************************************************************************
/****************************************************************************
* Name: lc823450_epsubmit
*
* Description:
* Submit an I/O request to the endpoint
*
******************************************************************************/
****************************************************************************/
static int lc823450_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
{
@ -704,13 +717,13 @@ static int lc823450_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
return 0;
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_epcancel
*
* Description:
* Cancel an I/O request previously sent to an endpoint
*
******************************************************************************/
****************************************************************************/
static int lc823450_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
{
@ -718,7 +731,7 @@ static int lc823450_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
struct lc823450_ep_s *privep = (struct lc823450_ep_s *)ep;
irqstate_t flags;
/* remove request from req_queue */
/* Remove request from req_queue */
flags = spin_lock_irqsave();
sq_remafter(&privreq->q_ent, &privep->req_q);
@ -726,13 +739,13 @@ static int lc823450_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
return 0;
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_epstall
*
* Description:
* Stall or resume and endpoint
*
******************************************************************************/
****************************************************************************/
static int lc823450_epstall(struct usbdev_ep_s *ep, bool resume)
{
@ -772,24 +785,25 @@ void up_epignore_clear_stall(struct usbdev_ep_s *ep, bool ignore)
}
#endif /* CONFIG_USBMSC_IGNORE_CLEAR_STALL */
/******************************************************************************
/****************************************************************************
* Name: lc823450_allocep
*
* Description:
* Allocate an endpoint matching the parameters.
*
* Input Parameters:
* eplog - 7-bit logical endpoint number (direction bit ignored). Zero means
* that any endpoint matching the other requirements will suffice. The
* assigned endpoint can be found in the eplog field.
* eplog - 7-bit logical endpoint number (direction bit ignored). Zero
* means that any endpoint matching the other requirements will
* suffice. The assigned endpoint can be found in the eplog field.
* in - true: IN (device-to-host) endpoint requested
* eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, USB_EP_ATTR_XFER_BULK,
* USB_EP_ATTR_XFER_INT}
* eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC,
* USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT}
*
******************************************************************************/
static struct usbdev_ep_s *lc823450_allocep(struct usbdev_s *dev, uint8_t eplog,
bool in, uint8_t eptype)
static struct usbdev_ep_s *lc823450_allocep(struct usbdev_s *dev,
uint8_t eplog, bool in,
uint8_t eptype)
{
struct lc823450_usbdev_s *priv = (struct lc823450_usbdev_s *)dev;
struct lc823450_ep_s *privep;
@ -818,13 +832,13 @@ static struct usbdev_ep_s *lc823450_allocep(struct usbdev_s *dev, uint8_t eplog,
return &privep->ep;
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_freeep
*
* Description:
* Free the previously allocated endpoint
*
******************************************************************************/
****************************************************************************/
static void lc823450_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
{
@ -838,13 +852,13 @@ static void lc823450_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
return;
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_getframe
*
* Description:
* Returns the current frame number
*
******************************************************************************/
****************************************************************************/
static int lc823450_getframe(struct usbdev_s *dev)
{
@ -853,13 +867,13 @@ static int lc823450_getframe(struct usbdev_s *dev)
return (int)(getreg32(USB_TSTAMP));
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_wakeup
*
* Description:
* Tries to wake up the host connected to this device
*
******************************************************************************/
****************************************************************************/
static int lc823450_wakeup(struct usbdev_s *dev)
{
@ -869,26 +883,26 @@ static int lc823450_wakeup(struct usbdev_s *dev)
return OK;
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_selfpowered
*
* Description:
* Sets/clears the device selfpowered feature
*
******************************************************************************/
****************************************************************************/
static int lc823450_selfpowered(struct usbdev_s *dev, bool selfpowered)
{
return OK;
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_usbpullup
*
* Description:
* Software-controlled connect to/disconnect from USB host
*
******************************************************************************/
****************************************************************************/
int lc823450_usbpullup(struct usbdev_s *dev, bool enable)
{
@ -904,13 +918,13 @@ int lc823450_usbpullup(struct usbdev_s *dev, bool enable)
}
#ifdef CONFIG_WAKELOCK
/******************************************************************************
/****************************************************************************
* Name: subintr_usbdev
*
* Description:
* USB dev interrupt sub handler
*
******************************************************************************/
****************************************************************************/
static void usb_suspend_work_func(void *arg)
{
@ -944,9 +958,9 @@ static void usb_suspend_work_func(void *arg)
#endif
#if defined(CONFIG_BATTERY) && defined(CONFIG_USBDEV_CHARGER)
/******************************************************************************
/****************************************************************************
* Name: usb_reset_work_func
******************************************************************************/
****************************************************************************/
static void usb_reset_work_func(void *arg)
{
@ -973,9 +987,9 @@ static void usb_reset_work_func(void *arg)
}
#endif
/******************************************************************************
/****************************************************************************
* Name: subintr_usbdev
******************************************************************************/
****************************************************************************/
static void subintr_usbdev(void)
{
@ -1068,19 +1082,20 @@ static void subintr_usbdev(void)
}
}
/******************************************************************************
/****************************************************************************
* Name: subintr_ep0
*
* Description:
* Endpoint0 interrupt sub handler
*
******************************************************************************/
****************************************************************************/
static void subintr_ep0(void)
{
uint32_t epctrl;
struct lc823450_usbdev_s *priv = &g_usbdev;
int len, handled = 0;
int len;
int handled = 0;
char resp[2];
uint8_t epnum;
@ -1170,7 +1185,8 @@ static void subintr_ep0(void)
}
else
{
putreg32(1 << ctrl.index[1] | USB_TESTC_FORCE_HS, USB_TESTC);
putreg32(1 << ctrl.index[1] | USB_TESTC_FORCE_HS,
USB_TESTC);
}
handled = 1;
@ -1242,13 +1258,13 @@ static void subintr_ep0(void)
}
}
/******************************************************************************
/****************************************************************************
* Name: subintr_epin
*
* Description:
* Endpoint interrupt sub handler
*
******************************************************************************/
****************************************************************************/
static void subintr_epin(uint8_t epnum, struct lc823450_ep_s *privep)
{
@ -1286,13 +1302,13 @@ static void subintr_epin(uint8_t epnum, struct lc823450_ep_s *privep)
}
}
/******************************************************************************
/****************************************************************************
* Name: subintr_epout
*
* Description:
* Endpoint interrupt sub handler
*
******************************************************************************/
****************************************************************************/
static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep)
{
@ -1337,13 +1353,13 @@ static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep)
}
}
/******************************************************************************
/****************************************************************************
* Name: subintr_ep
*
* Description:
* Endpoint interrupt sub handler
*
******************************************************************************/
****************************************************************************/
static void subintr_ep(uint8_t epnum)
{
@ -1365,13 +1381,13 @@ static void subintr_ep(uint8_t epnum)
}
}
/******************************************************************************
/****************************************************************************
* Name: lc823450_usbinterrupt
*
* Description:
* USB interrupt handler
*
******************************************************************************/
****************************************************************************/
static int lc823450_usbinterrupt(int irq, void *context, FAR void *arg)
{
@ -1412,8 +1428,10 @@ static int lc823450_usbinterrupt(int irq, void *context, FAR void *arg)
/****************************************************************************
* Name: up_usbinitialize
*
* Description:
* Initialize the USB driver
*
* Input Parameters:
* None
*
@ -1463,7 +1481,8 @@ void up_usbinitialize(void)
int usbdev_register(struct usbdevclass_driver_s *driver)
{
int ret = -1, i;
int ret = -1;
int i;
#ifdef CONFIG_DVFS
lc823450_dvfs_boost(DVFS_BOOST_TIMEOUT * 20);
@ -1508,7 +1527,6 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
modifyreg32(USB_CONF, 0, USB_CONF_SOFT_RESET);
while (getreg32(USB_CONF) & USB_CONF_SOFT_RESET);
putreg32(0, USB_CONF);
/* RAM area init */
@ -1627,7 +1645,8 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
/* At present, there is only a single USB device support. Hence it is
* pre-allocated as g_otgfsdev. However, in most code, the private data
* structure will be referenced using the 'priv' pointer (rather than the
* global data) in order to simplify any future support for multiple devices.
* global data) in order to simplify any future support for multiple
* devices.
*/
struct lc823450_usbdev_s *priv = &g_usbdev;
@ -1699,6 +1718,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
}
/* FOR USBMSC optimization */
#ifdef CONFIG_USBMSC_OPT
/****************************************************************************
* Name: usbdev_msc_read_enter

25
arch/arm/src/lpc43xx/lpc43_adc.c
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/lpc43xx/lpc43_adc.c
*
* Copyright(C) 2012, 2016 Gregory Nutt. All rights reserved.
@ -42,7 +42,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Included Files
@ -164,7 +164,8 @@ static struct up_dev_s g_adcpriv =
.mask_int = CONFIG_LPC43_ADC0_MASK,
.irq = LPC43M4_IRQ_ADC0,
.timer = CONFIG_LPC43_ADC0_USE_TIMER,
.m_ch = (CONFIG_LPC43_ADC0_MASK & (CONFIG_LPC43_ADC0_MASK - 1)) ? true : false
.m_ch = (CONFIG_LPC43_ADC0_MASK & (CONFIG_LPC43_ADC0_MASK - 1)) ?
true : false
};
static struct adc_dev_s g_adcdev =
@ -181,8 +182,8 @@ static struct adc_dev_s g_adcdev =
* Name: adc_bind
*
* Description:
* Bind the upper-half driver callbacks to the lower-half implementation. This
* must be called early in order to receive ADC event notifications.
* Bind the upper-half driver callbacks to the lower-half implementation.
* This must be called early in order to receive ADC event notifications.
*
****************************************************************************/
@ -227,7 +228,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_APB3_ADC0_CFG);
/* Calc config value*/
/* Calc config value */
regval = ADC_CR_PDN;
regval |= priv->mask;
@ -248,7 +249,8 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* Enable synch timer 2 match 0 to adc */
putreg32(GIMA_EDGE | GIMA_SYNCH | GIMA_ADC1_SELECT_T2MAT0, LPC43_GIMA_ADCSTART1);
putreg32(GIMA_EDGE | GIMA_SYNCH | GIMA_ADC1_SELECT_T2MAT0,
LPC43_GIMA_ADCSTART1);
/* Power on */
@ -264,12 +266,13 @@ static void adc_reset(FAR struct adc_dev_s *dev)
putreg32(LPC43_CCLK/priv->freq/2-1, LPC43_TIMER2_BASE+LPC43_TMR_PR_OFFSET); /* set clock, divide by 2 - bug in chip */
putreg32(1, LPC43_TMR2_MR0); /* set match on 1*/
putreg32(1, LPC43_TMR2_MR0); /* set match on 1 */
}
else
{
uint32_t clkdiv = BOARD_ABP3_FREQUENCY/priv->freq +(BOARD_ABP3_FREQUENCY%priv->freq != 0) - 1;
regval |= clkdiv<<ADC_CR_CLKDIV_SHIFT;
uint32_t clkdiv = BOARD_ABP3_FREQUENCY / priv->freq +
(BOARD_ABP3_FREQUENCY % priv->freq != 0) - 1;
regval |= clkdiv << ADC_CR_CLKDIV_SHIFT;
}
}
@ -480,7 +483,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg)
/* Read data, clear interrupt by this */
for(i = 0; i < 8; i++)
for (i = 0; i < 8; i++)
{
if (priv->mask & (1 << i))
{

2
arch/arm/src/lpc43xx/lpc43_can.c
View file

@ -725,7 +725,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
uint32_t dlc;
uint8_t txobj;
if(msg == NULL)
if (msg == NULL)
{
return ERROR;
}

2
arch/arm/src/lpc43xx/lpc43_ssp.c
View file

@ -589,7 +589,7 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
data = ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
if (rxbuffer)
{
if(priv->nbits > 8)
if (priv->nbits > 8)
{
*rx.p16++ = (uint16_t)data;
}

30
arch/arm/src/samd2l2/sam_ac.c
View file

@ -129,14 +129,16 @@ int sam_ac_initialize(uint8_t gclkgen)
int sam_ac_config(uint8_t channel, uint32_t compctrl)
{
switch(channel)
switch (channel)
{
case 0:
putreg32(compctrl, SAM_AC_COMPCTRL0);
break;
case 1:
putreg32(compctrl, SAM_AC_COMPCTRL1);
break;
default:
return -ENODEV;
}
@ -149,24 +151,36 @@ int sam_ac_config(uint8_t channel, uint32_t compctrl)
int sam_ac_enable(uint8_t channel, bool enable)
{
uint32_t regval;
switch(channel)
switch (channel)
{
case 0:
regval = getreg32(SAM_AC_COMPCTRL0);
if(enable == true)
regval |= AC_COMPCTRL_ENABLE;
if (enable == true)
{
regval |= AC_COMPCTRL_ENABLE;
}
else
regval &= ~AC_COMPCTRL_ENABLE;
{
regval &= ~AC_COMPCTRL_ENABLE;
}
putreg32(regval, SAM_AC_COMPCTRL0);
break;
case 1:
regval = getreg32(SAM_AC_COMPCTRL1);
if(enable == true)
regval |= AC_COMPCTRL_ENABLE;
if (enable == true)
{
regval |= AC_COMPCTRL_ENABLE;
}
else
regval &= ~AC_COMPCTRL_ENABLE;
{
regval &= ~AC_COMPCTRL_ENABLE;
}
putreg32(regval, SAM_AC_COMPCTRL1);
break;
default:
return -ENODEV;
}

5
arch/arm/src/samd2l2/sam_eic.c
View file

@ -81,7 +81,7 @@ static int sam_eic_isr(int irq, FAR void *context, FAR void *arg)
/* Dispatch the IRQ to the SAM_IRQ_EXTINTn handlers */
for(bit=0;bit<SAM_IRQ_NEXTINTS;bit++)
for (bit = 0; bit < SAM_IRQ_NEXTINTS; bit++)
{
if (intflag >> bit & 0x1)
{
@ -142,7 +142,8 @@ int sam_eic_initialize(uint8_t gclkgen)
sam_eic_enableperiph();
regval = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN(gclkgen) | GCLK_CLKCTRL_CLKEN;
regval = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN(gclkgen) |
GCLK_CLKCTRL_CLKEN;
putreg16(regval, SAM_GCLK_CLKCTRL);
putreg8(EIC_CTRLA_ENABLE, SAM_EIC_CTRLA);

2
arch/arm/src/stm32/stm32_can.c
View file

@ -1866,7 +1866,7 @@ static int stm32can_cellinit(FAR struct stm32_can_s *priv)
stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
ret = stm32can_enterinitmode(priv);
if(ret != 0)
if (ret != 0)
{
return ret;
}

16
arch/arm/src/stm32/stm32_capture.c
View file

@ -61,6 +61,7 @@
/************************************************************************************
* Private Types
************************************************************************************/
/* Configuration ********************************************************************/
#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || defined(GPIO_TIM3_CH1IN) || \
@ -97,8 +98,8 @@
# define USE_EXT_CLOCK 1
#endif
/* This module then only compiles if there are enabled timers that are not intended for
* some other purpose.
/* This module then only compiles if there are enabled timers that are not intended
* for some other purpose.
*/
#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM2_CAP) || \
@ -183,7 +184,7 @@ static inline void stm32_putreg32(FAR const struct stm32_cap_priv_s *priv,
static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
int channel)
{
switch(priv->base)
switch (priv->base)
{
#ifdef CONFIG_STM32_TIM1_CAP
case STM32_TIM1_BASE:
@ -628,7 +629,7 @@ static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv,
************************************************************************************/
static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t clk,
uint32_t prescaler,uint32_t max)
uint32_t prescaler, uint32_t max)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint16_t regval = 0;
@ -655,8 +656,7 @@ static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t c
prescaler = 0xffff;
}
switch(clk)
switch (clk)
{
case STM32_CAP_CLK_INT:
regval = GTIM_SMCR_DISAB;
@ -702,7 +702,8 @@ static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t c
return prescaler;
}
static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, void *arg)
static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler,
void *arg)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
int irq;
@ -750,7 +751,6 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, voi
return OK;
}
static void stm32_cap_enableint(FAR struct stm32_cap_dev_s *dev,
stm32_cap_flags_t src, bool on)
{

158
arch/arm/src/stm32/stm32_hrtim.c
View file

@ -340,9 +340,9 @@
struct stm32_hrtim_timout_s
{
uint32_t set; /* Set events*/
uint32_t rst; /* Reset events*/
uint8_t pol:1; /* Output polarisation */
uint32_t set; /* Set events*/
uint32_t rst; /* Reset events*/
uint8_t pol:1; /* Output polarisation */
};
/* HRTIM Slave Timer Chopper Configuration */
@ -379,10 +379,10 @@ struct stm32_hrtim_deadtime_s
struct stm32_hrtim_tim_burst_s
{
uint8_t ch1_en:1; /* Enable burst mode operation for CH1 */
uint8_t ch1_state:1; /* CH1 IDLE state */
uint8_t ch2_en:1; /* Enable burst mode operation for CH2 */
uint8_t ch2_state:1; /* CH2 IDLE state */
uint8_t ch1_en:1; /* Enable burst mode operation for CH1 */
uint8_t ch1_state:1; /* CH1 IDLE state */
uint8_t ch2_en:1; /* Enable burst mode operation for CH2 */
uint8_t ch2_state:1; /* CH2 IDLE state */
uint8_t res:4;
};
@ -407,13 +407,13 @@ struct stm32_hrtim_pwm_s
};
#endif
/* HRTIM TIMER Capture sturcutre */
/* HRTIM TIMER Capture structure */
#ifdef CONFIG_STM32_HRTIM_CAPTURE
struct stm32_hrtim_capture_s
{
uint32_t cap1; /* Capture 1 configuration */
uint32_t cap2; /* Capture 2 configuration */
uint32_t cap1; /* Capture 1 configuration */
uint32_t cap2; /* Capture 2 configuration */
};
#endif
@ -421,16 +421,16 @@ struct stm32_hrtim_capture_s
struct stm32_hrtim_timcmn_s
{
uint32_t base; /* The base adress of the timer */
uint64_t fclk; /* The frequency of the peripheral clock
* that drives the timer module.
*/
uint8_t prescaler:3; /* Prescaler */
uint8_t mode; /* Timer mode */
uint8_t dac:2; /* DAC triggering */
uint32_t base; /* The base adress of the timer */
uint64_t fclk; /* The frequency of the peripheral clock
* that drives the timer module.
*/
uint8_t prescaler:3; /* Prescaler */
uint8_t mode; /* Timer mode */
uint8_t dac:2; /* DAC triggering */
uint8_t reserved:3;
#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
uint16_t irq; /* interrupts configuration */
uint16_t irq; /* interrupts configuration */
#endif
#ifdef CONFIG_STM32_HRTIM_DMA
uint16_t dma;
@ -452,7 +452,7 @@ struct stm32_hrtim_tim_s
struct stm32_hrtim_master_priv_s
{
uint32_t reserved; /* reserved for future use */
uint32_t reserved; /* reserved for future use */
};
/* Slave Timer (A-E) private data structure */
@ -672,8 +672,8 @@ static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *priv,
uint8_t timer);
#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_FAULTS)
static FAR struct stm32_hrtim_slave_priv_s *hrtim_slave_get(FAR struct stm32_hrtim_s *priv,
uint8_t timer);
static FAR struct stm32_hrtim_slave_priv_s
hrtim_slave_get(FAR struct stm32_hrtim_s *priv, uint8_t timer);
#endif
static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s *priv, uint8_t timer);
@ -818,7 +818,7 @@ static struct stm32_hrtim_tim_s g_master =
/* If MASTER is disabled, we need only MASTER base */
#ifdef CONFIG_STM32_HRTIM_MASTER
.fclk = HRTIM_CLOCK/(1<<HRTIM_MASTER_PRESCALER),
.fclk = HRTIM_CLOCK / (1 << HRTIM_MASTER_PRESCALER),
.prescaler = HRTIM_MASTER_PRESCALER,
.mode = HRTIM_MASTER_MODE,
# ifdef CONFIG_STM32_HRTIM_MASTER_DAC
@ -921,7 +921,7 @@ static struct stm32_hrtim_tim_s g_tima =
.tim =
{
.base = STM32_HRTIM1_TIMERA_BASE,
.fclk = HRTIM_CLOCK/(1<<HRTIM_TIMA_PRESCALER),
.fclk = HRTIM_CLOCK / (1 << HRTIM_TIMA_PRESCALER),
.prescaler = HRTIM_TIMA_PRESCALER,
.mode = HRTIM_TIMA_MODE,
#ifdef CONFIG_STM32_HRTIM_TIMA_DAC
@ -1023,7 +1023,7 @@ static struct stm32_hrtim_tim_s g_timb =
.tim =
{
.base = STM32_HRTIM1_TIMERB_BASE,
.fclk = HRTIM_CLOCK/(1<<HRTIM_TIMB_PRESCALER),
.fclk = HRTIM_CLOCK / (1 << HRTIM_TIMB_PRESCALER),
.prescaler = HRTIM_TIMB_PRESCALER,
.mode = HRTIM_TIMB_MODE,
#ifdef CONFIG_STM32_HRTIM_TIMB_DAC
@ -1125,7 +1125,7 @@ static struct stm32_hrtim_tim_s g_timc =
.tim =
{
.base = STM32_HRTIM1_TIMERC_BASE,
.fclk = HRTIM_CLOCK/(1<<HRTIM_TIMC_PRESCALER),
.fclk = HRTIM_CLOCK / (1 << HRTIM_TIMC_PRESCALER),
.prescaler = HRTIM_TIMC_PRESCALER,
.mode = HRTIM_TIMC_MODE,
#ifdef CONFIG_STM32_HRTIM_TIMC_DAC
@ -1227,7 +1227,7 @@ static struct stm32_hrtim_tim_s g_timd =
.tim =
{
.base = STM32_HRTIM1_TIMERD_BASE,
.fclk = HRTIM_CLOCK/(1<<HRTIM_TIMD_PRESCALER),
.fclk = HRTIM_CLOCK / (1 << HRTIM_TIMD_PRESCALER),
.prescaler = HRTIM_TIMD_PRESCALER,
.mode = HRTIM_TIMD_MODE,
#ifdef CONFIG_STM32_HRTIM_TIMD_DAC
@ -1329,7 +1329,7 @@ static struct stm32_hrtim_tim_s g_time =
.tim =
{
.base = STM32_HRTIM1_TIMERE_BASE,
.fclk = HRTIM_CLOCK/(1<<HRTIM_TIME_PRESCALER),
.fclk = HRTIM_CLOCK / (1 << HRTIM_TIME_PRESCALER),
.prescaler = HRTIM_TIME_PRESCALER,
.mode = HRTIM_TIME_MODE,
#ifdef CONFIG_STM32_HRTIM_TIME_DAC
@ -1871,8 +1871,8 @@ static FAR struct stm32_hrtim_tim_s *
static FAR struct stm32_hrtim_slave_priv_s *
hrtim_slave_get(FAR struct stm32_hrtim_s *priv, uint8_t timer)
{
FAR struct stm32_hrtim_tim_s* tim;
FAR struct stm32_hrtim_slave_priv_s* slave;
FAR struct stm32_hrtim_tim_s *tim;
FAR struct stm32_hrtim_slave_priv_s *slave;
/* Sanity checking */
@ -1893,7 +1893,7 @@ static FAR struct stm32_hrtim_slave_priv_s *
/* Get Slave Timer data */
slave = (struct stm32_hrtim_slave_priv_s*)tim->priv;
slave = (struct stm32_hrtim_slave_priv_s *)tim->priv;
errout:
return slave;
@ -1915,9 +1915,9 @@ errout:
*
****************************************************************************/
static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s* priv, uint8_t timer)
static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s *priv, uint8_t timer)
{
FAR struct stm32_hrtim_tim_s* tim;
FAR struct stm32_hrtim_tim_s *tim;
uint32_t base = 0;
tim = hrtim_tim_get(priv, timer);
@ -2209,7 +2209,8 @@ static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv)
hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET, regval);
while(!(hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET) & HRTIM_ISR_DLLRDY));
while ((hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET) &
HRTIM_ISR_DLLRDY) == 0);
return OK;
}
@ -2404,10 +2405,10 @@ errout:
static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv)
{
#ifdef CONFIG_STM32_HRTIM_EVENTS
FAR struct stm32_hrtim_eev_s* eev = priv->eev;
FAR struct stm32_hrtim_eev_s *eev = priv->eev;
#endif
#ifdef CONFIG_STM32_HRTIM_FAULTS
FAR struct stm32_hrtim_faults_s* flt = priv->flt;
FAR struct stm32_hrtim_faults_s *flt = priv->flt;
#endif
/* Configure Timer A Outputs */
@ -2661,34 +2662,34 @@ errout:
static int hrtim_capture_config(FAR struct stm32_hrtim_s *priv)
{
FAR struct stm32_hrtim_slave_priv_s* slave;
FAR struct stm32_hrtim_slave_priv_s *slave;
#ifdef CONFIG_STM32_HRTIM_TIMA_CAP
slave = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->tima->priv;
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMA, HRTIM_CAPTURE1, slave->cap.cap1);
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMA, HRTIM_CAPTURE2, slave->cap.cap2);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB_CAP
slave = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->timb->priv;
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMB, HRTIM_CAPTURE1, slave->cap.cap1);
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMB, HRTIM_CAPTURE2, slave->cap.cap2);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC_CAP
slave = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->timc->priv;
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMC, HRTIM_CAPTURE1, slave->cap.cap1);
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMC, HRTIM_CAPTURE2, slave->cap.cap2);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD_CAP
slave = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->timd->priv;
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMD, HRTIM_CAPTURE1, slave->cap.cap1);
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMD, HRTIM_CAPTURE2, slave->cap.cap2);
#endif
#ifdef CONFIG_STM32_HRTIM_TIME_CAP
slave = (struct stm32_hrtim_slave_priv_s*)priv->time->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->time->priv;
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIME, HRTIM_CAPTURE1, slave->cap.cap1);
hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIME, HRTIM_CAPTURE2, slave->cap.cap2);
#endif
@ -2837,7 +2838,7 @@ static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv)
#if defined(CONFIG_STM32_HRTIM_PWM)
static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t timer)
{
FAR struct stm32_hrtim_slave_priv_s* slave;
FAR struct stm32_hrtim_slave_priv_s *slave;
uint32_t regval = 0;
int ret = OK;
@ -2935,7 +2936,8 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t time
{
/* Enable push-pull mode */
hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, 0, HRTIM_TIMCR_PSHPLL);
hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, 0,
HRTIM_TIMCR_PSHPLL);
}
#endif
@ -3065,7 +3067,7 @@ static uint8_t output_tim_index_get(uint16_t output)
{
uint8_t timer = 0;
switch(output)
switch (output)
{
#ifdef CONFIG_STM32_HRTIM_TIMA
case HRTIM_OUT_TIMA_CH1:
@ -3190,7 +3192,7 @@ static int hrtim_output_set_set(FAR struct hrtim_dev_s *dev, uint16_t output,
uint32_t set)
{
FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
FAR struct stm32_hrtim_slave_priv_s* slave;
FAR struct stm32_hrtim_slave_priv_s *slave;
uint8_t timer = 0;
int ret = OK;
@ -3244,7 +3246,7 @@ static int hrtim_output_rst_set(FAR struct hrtim_dev_s *dev, uint16_t output,
uint32_t rst)
{
FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
FAR struct stm32_hrtim_slave_priv_s* slave;
FAR struct stm32_hrtim_slave_priv_s *slave;
uint8_t timer = 0;
int ret = OK;
@ -3390,42 +3392,42 @@ static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv)
/* Configure DAC synchronization for Master Timer */
#ifdef CONFIG_STM32_HRTIM_MASTER_DAC
tim = (struct stm32_hrtim_timcmn_s*)priv->master;
tim = (struct stm32_hrtim_timcmn_s *)priv->master;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, tim->dac);
#endif
/* Configure DAC synchronization for Timer A */
#ifdef CONFIG_STM32_HRTIM_TIMA_DAC
tim = (struct stm32_hrtim_timcmn_s*)priv->tima;
tim = (struct stm32_hrtim_timcmn_s *)priv->tima;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, tim->dac);
#endif
/* Configure DAC synchronization for Timer B */
#ifdef CONFIG_STM32_HRTIM_TIMB_DAC
tim = (struct stm32_hrtim_timcmn_s*)priv->timb;
tim = (struct stm32_hrtim_timcmn_s *)priv->timb;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMB, tim->dac);
#endif
/* Configure DAC synchronization for Timer C */
#ifdef CONFIG_STM32_HRTIM_TIMC_DAC
tim = (struct stm32_hrtim_timcmn_s*)priv->timc;
tim = (struct stm32_hrtim_timcmn_s *)priv->timc;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMC, tim->dac);
#endif
/* Configure DAC synchronization for Timer D */
#ifdef CONFIG_STM32_HRTIM_TIMD_DAC
tim = (struct stm32_hrtim_timcmn_s*)priv->timd;
tim = (struct stm32_hrtim_timcmn_s *)priv->timd;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMD, tim->dac);
#endif
/* Configure DAC synchronization for Timer E */
#ifdef CONFIG_STM32_HRTIM_TIME_DAC
tim = (struct stm32_hrtim_timcmn_s*)priv->time;
tim = (struct stm32_hrtim_timcmn_s *)priv->time;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIME, tim->dac);
#endif
@ -3632,7 +3634,7 @@ errout:
static int hrtim_tim_deadtime_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer)
{
FAR struct stm32_hrtim_slave_priv_s* slave;
FAR struct stm32_hrtim_slave_priv_s *slave;
uint32_t regval = 0;
int ret = OK;
@ -3831,7 +3833,7 @@ errout:
static int hrtim_tim_chopper_cfg(FAR struct stm32_hrtim_s *priv,
uint8_t timer)
{
FAR struct stm32_hrtim_slave_priv_s* slave;
FAR struct stm32_hrtim_slave_priv_s *slave;
int ret = OK;
uint32_t regval = 0;
@ -3979,7 +3981,7 @@ static uint16_t hrtim_burst_cmp_get(FAR struct hrtim_dev_s *dev)
{
FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
return (uint16_t)hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET);;
return (uint16_t)hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET);
}
/****************************************************************************
@ -4225,11 +4227,13 @@ static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index)
/* Configure polarity */
regval |= (((flt->pol & HRTIM_FAULT_POL_HIGH) ? HRTIM_FLTINR1_FLT1P : 0) << (index-1)*8);
regval |= (((flt->pol & HRTIM_FAULT_POL_HIGH) ?
HRTIM_FLTINR1_FLT1P : 0) << (index-1)*8);
/* Config source */
regval |= (((flt->src & HRTIM_FAULT_SRC_PIN) ? HRTIM_FLTINR1_FLT1SRC : 0) << (index-1)*8);
regval |= (((flt->src & HRTIM_FAULT_SRC_PIN) ?
HRTIM_FLTINR1_FLT1SRC : 0) << (index-1)*8);
/* Config filter */
@ -4376,7 +4380,7 @@ static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv)
static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index)
{
struct stm32_hrtim_eev_cfg_s* eev;
struct stm32_hrtim_eev_cfg_s *eev;
int ret = OK;
uint32_t regval = 0;
@ -4478,7 +4482,8 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index)
/* Configure polarity */
regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? HRTIM_EECR1_EE1POL : 0) << (index-1)*6);
regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ?
HRTIM_EECR1_EE1POL : 0) << (index-1)*6);
/* Configure sensitivity */
@ -4486,7 +4491,8 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index)
/* Configure mode */
regval |= (((eev->mode & HRTIM_EEV_MODE_FAST) ? HRTIM_EECR1_EE1FAST : 0) << (index-1)*6);
regval |= (((eev->mode & HRTIM_EEV_MODE_FAST) ?
HRTIM_EECR1_EE1FAST : 0) << (index-1)*6);
/* Write register */
@ -4507,7 +4513,8 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index)
/* Configure polarity */
regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? HRTIM_EECR2_EE6POL : 0) << (index-6)*6);
regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ?
HRTIM_EECR2_EE6POL : 0) << (index-6)*6);
/* Configure sensitivity */
@ -4605,7 +4612,6 @@ static int hrtim_events_config(FAR struct stm32_hrtim_s *priv)
}
#endif /* CONFIG_STM32_HRTIM_FAULTS */
#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
/****************************************************************************
@ -4841,7 +4847,7 @@ static void hrtim_mode_config(FAR struct stm32_hrtim_s *priv)
static uint8_t hrtim_cmpcap_mask_get(FAR struct stm32_hrtim_s *priv,
uint8_t timer)
{
FAR struct stm32_hrtim_tim_s* tim;
FAR struct stm32_hrtim_tim_s *tim;
uint8_t mask = 0;
/* Get Timer data strucutre */
@ -4855,7 +4861,7 @@ static uint8_t hrtim_cmpcap_mask_get(FAR struct stm32_hrtim_s *priv,
/* Not significant bits depens on timer prescaler */
switch(tim->tim.prescaler)
switch (tim->tim.prescaler)
{
case HRTIM_PRESCALER_1:
{
@ -5342,7 +5348,7 @@ static int hrtim_tim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
/* TimerX reset events differ for individual timers */
switch(timer)
switch (timer)
{
#ifdef CONFIG_STM32_HRTIM_TIMA
case HRTIM_TIMER_TIMA:
@ -5462,27 +5468,27 @@ static int hrtim_reset_config(FAR struct stm32_hrtim_s *priv)
FAR struct stm32_hrtim_slave_priv_s *slave;
#ifdef CONFIG_STM32_HRTIM_TIMA
slave = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->tima->priv;
hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMA, slave->reset);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB
slave = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->timb->priv;
hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMB, slave->reset);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC
slave = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->timc->priv;
hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMC, slave->reset);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD
slave = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->timd->priv;
hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMD, slave->reset);
#endif
#ifdef CONFIG_STM32_HRTIM_TIME
slave = (struct stm32_hrtim_slave_priv_s*)priv->time->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->time->priv;
hrtim_tim_reset_set(priv, HRTIM_TIMER_TIME, slave->reset);
#endif
@ -5536,27 +5542,27 @@ static int hrtim_update_config(FAR struct stm32_hrtim_s *priv)
FAR struct stm32_hrtim_slave_priv_s *slave;
#ifdef CONFIG_STM32_HRTIM_TIMA
slave = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->tima->priv;
hrtim_tim_update_set(priv, HRTIM_TIMER_TIMA, slave->update);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB
slave = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->timb->priv;
hrtim_tim_update_set(priv, HRTIM_TIMER_TIMB, slave->update);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC
slave = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->timc->priv;
hrtim_tim_update_set(priv, HRTIM_TIMER_TIMC, slave->update);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD
slave = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->timd->priv;
hrtim_tim_update_set(priv, HRTIM_TIMER_TIMD, slave->update);
#endif
#ifdef CONFIG_STM32_HRTIM_TIME
slave = (struct stm32_hrtim_slave_priv_s*)priv->time->priv;
slave = (struct stm32_hrtim_slave_priv_s *)priv->time->priv;
hrtim_tim_update_set(priv, HRTIM_TIMER_TIME, slave->update);
#endif
@ -5846,7 +5852,7 @@ errout:
*
****************************************************************************/
FAR struct hrtim_dev_s* stm32_hrtiminitialize(void)
FAR struct hrtim_dev_s *stm32_hrtiminitialize(void)
{
FAR struct hrtim_dev_s *dev;
FAR struct stm32_hrtim_s *hrtim;

2
arch/arm/src/stm32/stm32_hrtim.h
View file

@ -1126,7 +1126,7 @@ extern "C"
*
****************************************************************************/
FAR struct hrtim_dev_s* stm32_hrtiminitialize(void);
FAR struct hrtim_dev_s *stm32_hrtiminitialize(void);
/****************************************************************************
* Name: hrtim_register

2
arch/arm/src/stm32/stm32_i2s.c
View file

@ -1954,7 +1954,7 @@ errout_with_exclsem:
static int roundf(float num)
{
if(((int)(num + 0.5f)) > num)
if (((int)(num + 0.5f)) > num)
{
return num + 1;
}

295
arch/arm/src/stm32/stm32_otgfsdev.c
View file

@ -67,6 +67,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***************************************************************/
#ifndef CONFIG_USBDEV_EP0_MAXSIZE
@ -196,6 +197,7 @@
#endif
/* Debug ***********************************************************************/
/* Trace error codes */
#define STM32_TRACEERR_ALLOCFAIL 0x01
@ -535,6 +537,7 @@ static bool stm32_req_addlast(FAR struct stm32_ep_s *privep,
FAR struct stm32_req_s *req);
/* Low level data transfers and request operations *****************************/
/* Special endpoint 0 data transfer logic */
static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv,
@ -619,6 +622,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv);
static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg);
/* Endpoint operations *********************************************************/
/* Global OUT NAK controls */
static void stm32_enablegonak(FAR struct stm32_ep_s *privep);
@ -698,6 +702,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv);
/****************************************************************************
* Private Data
****************************************************************************/
/* Since there is only a single USB interface, all status information can be
* be simply retained in a single global instance.
*/
@ -2723,6 +2728,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
*/
#if 1
/* REVISIT: */
if ((doepint & OTGFS_DOEPINT_EPDISD) != 0)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint);
@ -3163,162 +3169,160 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
/* Disable the Rx status queue level interrupt */
while(0 != (stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL))
while (0 != (stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL))
{
/* Get the status from the top of the FIFO */
/* Get the status from the top of the FIFO */
regval = stm32_getreg(STM32_OTGFS_GRXSTSP);
regval = stm32_getreg(STM32_OTGFS_GRXSTSP);
/* Decode status fields */
/* Decode status fields */
epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT;
epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT;
/* Workaround for bad values read from the STM32_OTGFS_GRXSTSP register
* happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c
* All of which provide out of range indexes for epout[epphy]
*/
/* Workaround for bad values read from the STM32_OTGFS_GRXSTSP register
* happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c
* All of which provide out of range indexes for epout[epphy]
*/
if (epphy < STM32_NENDPOINTS)
{
privep = &priv->epout[epphy];
if (epphy < STM32_NENDPOINTS)
{
privep = &priv->epout[epphy];
/* Handle the RX event according to the packet status field */
/* Handle the RX event according to the packet status field */
switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
{
/* Global OUT NAK. This indicate that the global OUT NAK bit has taken
* effect.
*
* PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
* Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0);
}
break;
/* OUT data packet received.
*
* PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
* EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy);
bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
if (bcnt > 0)
{
stm32_epout_receive(privep, bcnt);
}
}
break;
/* OUT transfer completed. This indicates that an OUT data transfer for
* the specified OUT endpoint has completed. After this entry is popped
* from the receive FIFO, the core asserts a Transfer Completed interrupt
* on the specified OUT endpoint.
*
* PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
* which the data transfer is complete, DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy);
}
break;
/* SETUP transaction completed. This indicates that the Setup stage for
* the specified endpoint has completed and the Data stage has started.
* After this entry is popped from the receive FIFO, the core asserts a
* Setup interrupt on the specified control OUT endpoint (triggers an
* interrupt).
*
* PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
* DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
/* Now that the Setup Phase is complete if it was an OUT enable
* the endpoint
* (Doing this here prevents the loss of the first FIFO word)
*/
if (priv->ep0state == EP0STATE_SETUP_OUT)
{
/* Clear NAKSTS so that we can receive the data */
regval = stm32_getreg(STM32_OTGFS_DOEPCTL0);
regval |= OTGFS_DOEPCTL0_CNAK;
stm32_putreg(regval, STM32_OTGFS_DOEPCTL0);
}
}
break;
/* SETUP data packet received. This indicates that a SETUP packet for the
* specified endpoint is now available for reading from the receive FIFO.
*
* PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
{
uint16_t datlen;
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy);
/* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
* the last one overwrites the previous setup packets and only that
* last SETUP packet will be processed.
*/
stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
USB_SIZEOF_CTRLREQ);
/* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
* then we need to wait for the completion of the data phase to
* process the setup command. If it is an IN SETUP packet, then
* we must processing the command BEFORE we enter the DATA phase.
/* Global OUT NAK. This indicate that the global OUT NAK bit has taken
* effect.
*
* If the data associated with the OUT SETUP packet is zero length,
* then, of course, we don't need to wait.
* PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
* Care.
*/
datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{
/* Wait for the data phase. */
case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0);
}
break;
priv->ep0state = EP0STATE_SETUP_OUT;
}
else
{
/* We can process the setup data as soon as SETUP done word is
* popped of the RxFIFO.
*/
/* OUT data packet received.
*
* PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
* EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
*/
priv->ep0state = EP0STATE_SETUP_READY;
}
case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy);
bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
if (bcnt > 0)
{
stm32_epout_receive(privep, bcnt);
}
}
break;
/* OUT transfer completed. This indicates that an OUT data transfer for
* the specified OUT endpoint has completed. After this entry is popped
* from the receive FIFO, the core asserts a Transfer Completed interrupt
* on the specified OUT endpoint.
*
* PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
* which the data transfer is complete, DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy);
}
break;
/* SETUP transaction completed. This indicates that the Setup stage for
* the specified endpoint has completed and the Data stage has started.
* After this entry is popped from the receive FIFO, the core asserts a
* Setup interrupt on the specified control OUT endpoint (triggers an
* interrupt).
*
* PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
* DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
/* Now that the Setup Phase is complete if it was an OUT enable
* the endpoint
* (Doing this here prevents the loss of the first FIFO word)
*/
if (priv->ep0state == EP0STATE_SETUP_OUT)
{
/* Clear NAKSTS so that we can receive the data */
regval = stm32_getreg(STM32_OTGFS_DOEPCTL0);
regval |= OTGFS_DOEPCTL0_CNAK;
stm32_putreg(regval, STM32_OTGFS_DOEPCTL0);
}
}
break;
/* SETUP data packet received. This indicates that a SETUP packet for the
* specified endpoint is now available for reading from the receive FIFO.
*
* PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
{
uint16_t datlen;
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy);
/* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
* the last one overwrites the previous setup packets and only that
* last SETUP packet will be processed.
*/
stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
USB_SIZEOF_CTRLREQ);
/* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
* then we need to wait for the completion of the data phase to
* process the setup command. If it is an IN SETUP packet, then
* we must processing the command BEFORE we enter the DATA phase.
*
* If the data associated with the OUT SETUP packet is zero length,
* then, of course, we don't need to wait.
*/
datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{
/* Wait for the data phase. */
priv->ep0state = EP0STATE_SETUP_OUT;
}
else
{
/* We can process the setup data as soon as SETUP done word is
* popped of the RxFIFO.
*/
priv->ep0state = EP0STATE_SETUP_READY;
}
}
break;
default:
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS),
(regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT);
}
break;
}
break;
default:
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS),
(regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT);
}
break;
}
}
}
}
}
@ -3587,7 +3591,6 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg)
stm32_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), STM32_OTGFS_GINTSTS);
/* Break out of the loop when there are no further pending (and
* unmasked) interrupts to be processes.
*/
@ -3961,7 +3964,6 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
mpsiz = (maxpacket << OTGFS_DIEPCTL_MPSIZ_SHIFT);
}
/* If the endpoint is already active don't change the endpoint control
* register.
*/
@ -4106,6 +4108,7 @@ static void stm32_epout_disable(FAR struct stm32_ep_s *privep)
while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0);
#else
/* REVISIT: */
up_udelay(10);
#endif
@ -4535,6 +4538,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep)
while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0);
#else
/* REVISIT: */
up_udelay(10);
#endif
@ -5191,6 +5195,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
stm32_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG);
/* Common USB OTG core initialization */
/* Reset after a PHY select and set Host mode. First, wait for AHB master
* IDLE state.
*/
@ -5271,6 +5276,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
up_mdelay(50);
/* Initialize device mode */
/* Restart the PHY Clock */
stm32_putreg(0, STM32_OTGFS_PCGCCTL);
@ -5489,7 +5495,8 @@ void up_usbinitialize(void)
#endif
/* Uninitialize the hardware so that we know that we are starting from a
* known state. */
* known state.
*/
up_usbuninitialize();

44
arch/arm/src/stm32/stm32_pwm.c
View file

@ -71,6 +71,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PWM/Timer Definitions ****************************************************/
/* The following definitions are used to identify the various time types.
@ -364,6 +365,7 @@ struct stm32_pwm_break_s
#endif
/* PWM channel configuration */
struct stm32_pwmchan_s
{
uint8_t channel:4; /* Timer output channel: {1,..4} */
@ -421,12 +423,14 @@ struct stm32_pwmtimer_s
/****************************************************************************
* Static Function Prototypes
****************************************************************************/
/* Register access */
static uint32_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset);
static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint32_t value);
static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset,
uint32_t value);
static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset,
uint32_t clearbits, uint32_t setbits);
uint32_t clearbits, uint32_t setbits);
#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg);
@ -438,13 +442,13 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg);
static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev,
uint32_t frequency);
static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, uint8_t channel,
uint32_t mode);
static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv,
uint8_t channel, uint32_t mode);
static int pwm_timer_configure(FAR struct stm32_pwmtimer_s *priv);
static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
uint8_t channel);
static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev, uint16_t outputs,
bool state);
static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
uint16_t outputs, bool state);
static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev);
static int pwm_soft_break(FAR struct pwm_lowerhalf_s *dev, bool state);
static int pwm_ccr_update(FAR struct pwm_lowerhalf_s *dev, uint8_t index,
@ -459,7 +463,8 @@ static int pwm_timer_enable(FAR struct pwm_lowerhalf_s *dev, bool state);
static int pwm_break_dt_configure(FAR struct stm32_pwmtimer_s *priv);
#endif
#ifdef HAVE_TRGO
static int pwm_sync_configure(FAR struct stm32_pwmtimer_s *priv, uint8_t trgo);
static int pwm_sync_configure(FAR struct stm32_pwmtimer_s *priv,
uint8_t trgo);
#endif
#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS)
static int pwm_deadtime_update(FAR struct pwm_lowerhalf_s *dev, uint8_t dt);
@ -2965,7 +2970,7 @@ static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
* outputs - outputs to set (look at enum stm32_chan_e in stm32_pwm.h)
* state - Enable/disable operation
*
****************************************************************************/
****************************************************************************/
static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
uint16_t outputs, bool state)
@ -3056,7 +3061,6 @@ errout:
#endif
#ifdef HAVE_TRGO
/****************************************************************************
* Name: pwm_sync_configure
*
@ -3071,12 +3075,12 @@ static int pwm_sync_configure(FAR struct stm32_pwmtimer_s *priv, uint8_t trgo)
/* Configure TRGO (4 LSB in trgo) */
cr2 |= (((trgo>>0) & 0x0F) << ATIM_CR2_MMS_SHIFT) & ATIM_CR2_MMS_MASK;
cr2 |= (((trgo >> 0) & 0x0f) << ATIM_CR2_MMS_SHIFT) & ATIM_CR2_MMS_MASK;
#ifdef HAVE_IP_TIMERS_V2
/* Configure TRGO2 (4 MSB in trgo)*/
/* Configure TRGO2 (4 MSB in trgo) */
cr2 |= (((trgo>>4) & 0x0F) << ATIM_CR2_MMS2_SHIFT) & ATIM_CR2_MMS2_MASK;
cr2 |= (((trgo >> 4) & 0x0f) << ATIM_CR2_MMS2_SHIFT) & ATIM_CR2_MMS2_MASK;
#endif
/* Write register */
@ -3152,7 +3156,7 @@ static uint16_t pwm_outputs_from_channels(FAR struct stm32_pwmtimer_s *priv)
uint8_t channel = 0;
uint8_t i = 0;
for(i = 0; i < priv->chan_num; i += 1)
for (i = 0; i < priv->chan_num; i += 1)
{
/* Get channel */
@ -3205,7 +3209,7 @@ static int pwm_break_dt_configure(FAR struct stm32_pwmtimer_s *priv)
*/
pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK,
priv->t_dts<<GTIM_CR1_CKD_SHIFT);
priv->t_dts << GTIM_CR1_CKD_SHIFT);
#ifdef HAVE_PWM_COMPLEMENTARY
/* Initialize deadtime */
@ -3257,7 +3261,7 @@ static int pwm_break_dt_configure(FAR struct stm32_pwmtimer_s *priv)
/* Configure lock */
bdtr |= priv->lock<<GTIM_BDTR_LOCK_SHIFT;
bdtr |= priv->lock << GTIM_BDTR_LOCK_SHIFT;
/* Write BDTR register at once */
@ -3328,8 +3332,9 @@ static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev)
goto errout;
}
/* Configure TRGO/TRGO2 */
#ifdef HAVE_TRGO
/* Configure TRGO/TRGO2 */
ret = pwm_sync_configure(priv, priv->trgo);
if (ret < 0)
{
@ -3570,8 +3575,9 @@ static int pwm_configure(FAR struct pwm_lowerhalf_s *dev)
goto errout;
}
/* Configure TRGO/TRGO2 */
#ifdef HAVE_TRGO
/* Configure TRGO/TRGO2 */
ret = pwm_sync_configure(priv, priv->trgo);
if (ret < 0)
{
@ -3882,7 +3888,7 @@ static int pwm_interrupt(FAR struct pwm_lowerhalf_s *dev)
/* Now all of the time critical stuff is done so we can do some debug
* output.
*/
*/
pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n",
regval, priv->prev, priv->curr, priv->count);
@ -4374,7 +4380,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
info->channels[i].duty);
}
#else
ret = pwm_duty_update(dev, priv->channels[0].channel,info->duty);
ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty);
#endif /* CONFIG_PWM_MULTICHAN */
}
else

41
arch/arm/src/stm32/stm32f20xxf40xx_flash.c
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32/stm32f20xx40xx_flash.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
@ -31,19 +31,19 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/* Provides standard flash access functions, to be used by the flash mtd driver.
* The interface is defined in the include/nuttx/progmem.h
/* Provides standard flash access functions, to be used by the flash mtd
* driver. The interface is defined in the include/nuttx/progmem.h
*
* Requirements during write/erase operations on FLASH:
* - HSI must be ON.
* - Low Power Modes are not permitted during write/erase
*/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
@ -67,9 +67,9 @@
# warning "Default Flash Configuration Used - See Override Flash Size Designator"
#endif
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#define FLASH_KEY1 0x45670123
#define FLASH_KEY2 0xcdef89ab
@ -77,15 +77,15 @@
#define FLASH_OPTKEY2 0x4c5d6e7f
#define FLASH_ERASEDVALUE 0xff
/************************************************************************************
/****************************************************************************
* Private Data
************************************************************************************/
****************************************************************************/
static sem_t g_sem = SEM_INITIALIZER(1);
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
static void sem_lock(void)
{
@ -150,9 +150,9 @@ static void data_cache_enable(void)
}
#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
void stm32_flash_unlock(void)
{
@ -168,13 +168,13 @@ void stm32_flash_lock(void)
sem_unlock();
}
/************************************************************************************
/****************************************************************************
* Name: stm32_flash_writeprotect
*
* Description:
* Enable or disable the write protection of a flash sector.
*
************************************************************************************/
****************************************************************************/
int stm32_flash_writeprotect(size_t page, bool enabled)
{
@ -213,11 +213,11 @@ int stm32_flash_writeprotect(size_t page, bool enabled)
if (enabled)
{
val &= ~(1 << (16+page) );
val &= ~(1 << (16 + page));
}
else
{
val |= (1 << (16+page) );
val |= (1 << (16 + page));
}
/* Unlock options */
@ -235,7 +235,10 @@ int stm32_flash_writeprotect(size_t page, bool enabled)
/* Wait for completion */
while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
up_waste();
}
/* Relock options */

16
arch/arm/src/stm32f7/stm32_capture.c
View file

@ -60,6 +60,7 @@
/************************************************************************************
* Private Types
************************************************************************************/
/* Configuration ********************************************************************/
#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || defined(GPIO_TIM3_CH1IN) || \
@ -96,8 +97,8 @@
# define USE_EXT_CLOCK 1
#endif
/* This module then only compiles if there are enabled timers that are not intended for
* some other purpose.
/* This module then only compiles if there are enabled timers that are not intended
* for some other purpose.
*/
#if defined(CONFIG_STM32F7_TIM1_CAP) || defined(CONFIG_STM32F7_TIM2_CAP) || \
@ -182,7 +183,7 @@ static inline void stm32_putreg32(FAR const struct stm32_cap_priv_s *priv,
static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
int channel)
{
switch(priv->base)
switch (priv->base)
{
#ifdef CONFIG_STM32F7_TIM1_CAP
case STM32_TIM1_BASE:
@ -627,7 +628,7 @@ static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv,
************************************************************************************/
static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t clk,
uint32_t prescaler,uint32_t max)
uint32_t prescaler, uint32_t max)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint16_t regval = 0;
@ -654,8 +655,7 @@ static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t c
prescaler = 0xffff;
}
switch(clk)
switch (clk)
{
case STM32_CAP_CLK_INT:
regval = GTIM_SMCR_DISAB;
@ -701,7 +701,8 @@ static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t c
return prescaler;
}
static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, void *arg)
static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler,
void *arg)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
int irq;
@ -749,7 +750,6 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, voi
return OK;
}
static void stm32_cap_enableint(FAR struct stm32_cap_dev_s *dev,
stm32_cap_flags_t src, bool on)
{

46
arch/arm/src/stm32f7/stm32_flash.c
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32f7/stm32_flash.c
*
* Copyright (C) 2018 Wolpike LLC. All rights reserved.
@ -36,19 +36,19 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/* Provides standard flash access functions, to be used by the flash mtd driver.
* The interface is defined in the include/nuttx/progmem.h
/* Provides standard flash access functions, to be used by the flash mtd
* driver. The interface is defined in the include/nuttx/progmem.h
*
* Requirements during write/erase operations on FLASH:
* - HSI must be ON.
* - Low Power Modes are not permitted during write/erase
*/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
@ -62,9 +62,9 @@
#include "up_arch.h"
#include "cache.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#define FLASH_KEY1 0x45670123
#define FLASH_KEY2 0xcdef89ab
@ -72,15 +72,15 @@
#define FLASH_OPTKEY2 0x4c5d6e7f
#define FLASH_ERASEDVALUE 0xff
/************************************************************************************
/****************************************************************************
* Private Data
************************************************************************************/
****************************************************************************/
static sem_t g_sem = SEM_INITIALIZER(1);
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
static void up_waste(void)
{
@ -131,9 +131,9 @@ static void flash_lock(void)
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
}
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
void stm32_flash_unlock(void)
{
@ -149,13 +149,13 @@ void stm32_flash_lock(void)
sem_unlock();
}
/************************************************************************************
/****************************************************************************
* Name: stm32_flash_writeprotect
*
* Description:
* Enable or disable the write protection of a flash sector.
*
************************************************************************************/
****************************************************************************/
int stm32_flash_writeprotect(size_t page, bool enabled)
{
@ -194,11 +194,11 @@ int stm32_flash_writeprotect(size_t page, bool enabled)
if (enabled)
{
val &= ~(1 << (16+page) );
val &= ~(1 << (16 + page));
}
else
{
val |= (1 << (16+page) );
val |= (1 << (16 + page));
}
/* Unlock options */
@ -216,7 +216,10 @@ int stm32_flash_writeprotect(size_t page, bool enabled)
/* Wait for completion */
while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
up_waste();
}
/* Re-lock options */
@ -399,8 +402,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
putreg8(*byte, addr);
/* Data synchronous Barrier (DSB) just after the write operation. This will
* force the CPU to respect the sequence of instruction (no optimization).
/* Data synchronous Barrier (DSB) just after the write operation. This
* will force the CPU to respect the sequence of instruction (no
* optimization).
*/
ARM_DSB();

43
arch/arm/src/stm32h7/stm32_i2c.c
View file

@ -181,7 +181,7 @@
* To configure the ISR timeout using dynamic values (CONFIG_STM32H7_I2C_DYNTIMEO=y):
*
* CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte)
* CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds)
* CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in msec)
*
* Debugging output enabled with:
*
@ -236,7 +236,8 @@
#undef INVALID_CLOCK_SOURCE
#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || defined(CONFIG_STM32H7_I2C3)
#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || \
defined(CONFIG_STM32H7_I2C3)
# if STM32_RCC_D2CCIP2R_I2C123SRC != RCC_D2CCIP2R_I2C123SEL_HSI
# warning "Clock Source STM32_RCC_D2CCIP2R_I2C123SRC must be HSI"
# define INVALID_CLOCK_SOURCE
@ -427,10 +428,10 @@ struct stm32_i2c_inst_s
static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset);
static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
uint16_t value);
static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
uint32_t value);
static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset, uint16_t value);
static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t value);
static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t clearbits,
uint32_t setbits);
@ -464,8 +465,8 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
int count);
static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
int count);
static int stm32_i2c_transfer(FAR struct i2c_master_s *dev,
FAR struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(FAR struct i2c_master_s * dev);
#endif
@ -676,7 +677,6 @@ static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv,
putreg32(value, priv->config->base + offset);
}
/************************************************************************************
* Name: stm32_i2c_modifyreg32
*
@ -759,7 +759,8 @@ static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
#ifndef CONFIG_I2C_POLLED
static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv)
{
stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE));
stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0,
(I2C_CR1_TXRX | I2C_CR1_NACKIE));
}
#endif
@ -987,7 +988,6 @@ stm32_i2c_disable_reload(FAR struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0);
}
/************************************************************************************
* Name: stm32_i2c_sem_waitstop
*
@ -1979,7 +1979,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->flags = priv->msgv->flags;
/* if this is the last message, disable reload so the
* TC event fires next time */
* TC event fires next time.
*/
if (priv->msgc == 0)
{
@ -2105,7 +2106,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0);
/* clear pointer to message content to reflect we are done
* with the current transaction */
* with the current transaction.
*/
priv->msgv = NULL;
@ -2267,7 +2269,8 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
*
************************************************************************************/
static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count)
static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
int count)
{
struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev;
FAR struct stm32_i2c_priv_s *priv = inst->priv;
@ -2359,12 +2362,12 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
errval = ETIMEDOUT;
i2cerr("ERROR: Waitdone timed out CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n",
cr1, cr2,status);
cr1, cr2, status);
}
else
{
i2cinfo("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n",
cr1, cr2,status );
cr1, cr2, status);
}
UNUSED(cr1);
@ -2467,9 +2470,9 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
status = stm32_i2c_getstatus(priv);
while(status & I2C_ISR_BUSY)
while ((status & I2C_ISR_BUSY) != 0)
{
if((clock_systimer() - start) > timeout)
if ((clock_systimer() - start) > timeout)
{
i2cerr("ERROR: I2C Bus busy");
errval = EBUSY;
@ -2496,8 +2499,8 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
*
************************************************************************************/
static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
int count)
static int stm32_i2c_transfer(FAR struct i2c_master_s *dev,
FAR struct i2c_msg_s *msgs, int count)
{
stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */
return stm32_i2c_process(dev, msgs, count);

2
arch/arm/src/stm32l4/stm32l4_can.c
View file

@ -1849,7 +1849,7 @@ static int stm32l4can_cellinit(FAR struct stm32l4_can_s *priv)
stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
ret = stm32l4can_enterinitmode(priv);
if(ret != 0)
if (ret != 0)
{
return ret;
}

36
arch/arm/src/stm32l4/stm32l4_comp.c
View file

@ -364,18 +364,21 @@ static int stm32l4_compconfig(FAR const struct comp_dev_s *dev)
switch (cfg->inp)
{
case STM32L4_COMP_INP_PIN_1:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1);
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 :
GPIO_COMP2_INP_1);
regval |= COMP_CSR_INPSEL_PIN1;
break;
case STM32L4_COMP_INP_PIN_2:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2);
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 :
GPIO_COMP2_INP_2);
regval |= COMP_CSR_INPSEL_PIN2;
break;
#if defined(CONFIG_STM32L4_STM32L4X3)
case STM32L4_COMP_INP_PIN_3:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3);
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 :
GPIO_COMP2_INP_3);
regval |= COMP_CSR_INPSEL_PIN3;
break;
#endif
@ -422,12 +425,14 @@ static int stm32l4_compconfig(FAR const struct comp_dev_s *dev)
break;
case STM32L4_COMP_INM_PIN_1:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_1 : GPIO_COMP2_INM_1);
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_1 :
GPIO_COMP2_INM_1);
regval |= COMP_CSR_INMSEL_PIN1;
break;
case STM32L4_COMP_INM_PIN_2:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2);
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 :
GPIO_COMP2_INM_2);
#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \
defined(CONFIG_STM32L4_STM32L4XR)
regval |= COMP_CSR_INMSEL_PIN2;
@ -440,21 +445,24 @@ static int stm32l4_compconfig(FAR const struct comp_dev_s *dev)
#if defined(CONFIG_STM32L4_STM32L4X3)
case STM32L4_COMP_INM_PIN_3:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_3 : GPIO_COMP2_INM_3);
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_3 :
GPIO_COMP2_INM_3);
regval |= COMP_CSR_INMSEL_INMESEL;
mask |= COMP_CSR_INMESEL_MASK;
regval |= COMP_CSR_INMESEL_PIN3;
break;
case STM32L4_COMP_INM_PIN_4:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_4 : GPIO_COMP2_INM_4);
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_4 :
GPIO_COMP2_INM_4);
regval |= COMP_CSR_INMSEL_INMESEL;
mask |= COMP_CSR_INMESEL_MASK;
regval |= COMP_CSR_INMESEL_PIN4;
break;
case STM32L4_COMP_INM_PIN_5:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_5 : GPIO_COMP2_INM_5);
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_5 :
GPIO_COMP2_INM_5);
regval |= COMP_CSR_INMSEL_INMESEL;
mask |= COMP_CSR_INMESEL_MASK;
regval |= COMP_CSR_INMESEL_PIN5;
@ -493,7 +501,7 @@ static int stm32l4_compconfig(FAR const struct comp_dev_s *dev)
/* Power/speed Mode */
mask |= COMP_CSR_PWRMODE_MASK;
switch(cfg->speed)
switch (cfg->speed)
{
case STM32L4_COMP_SPEED_HIGH:
regval |= COMP_CSR_PWRMODE_HIGH;
@ -537,8 +545,9 @@ static int stm32l4_compconfig(FAR const struct comp_dev_s *dev)
if (cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling))
{
ret = stm32l4_exti_comp(cmp, cfg->interrupt.rising, cfg->interrupt.falling,
0, stm32l4_exti_comp_isr, (void *)dev);
ret = stm32l4_exti_comp(cmp, cfg->interrupt.rising,
cfg->interrupt.falling, 0,
stm32l4_exti_comp_isr, (void *)dev);
if (ret < 0)
{
aerr("stm32l4_exti_comp failed ret = %d\n", ret);
@ -569,8 +578,9 @@ static int stm32l4_compconfig(FAR const struct comp_dev_s *dev)
*
****************************************************************************/
FAR struct comp_dev_s* stm32l4_compinitialize(int intf,
FAR const struct stm32l4_comp_config_s *cfg)
FAR struct comp_dev_s *
stm32l4_compinitialize(int intf,
FAR const struct stm32l4_comp_config_s *cfg)
{
FAR struct comp_dev_s *dev;

127
arch/arm/src/stm32l4/stm32l4_firewall.c
View file

@ -38,6 +38,9 @@
****************************************************************************/
#include <nuttx/config.h>
#include <errno.h>
#include <nuttx/arch.h>
#include "up_arch.h"
@ -45,67 +48,85 @@
#include "stm32l4_firewall.h"
/****************************************************************************
* Public Functions
****************************************************************************/
int stm32l4_firewallsetup(FAR struct stm32l4_firewall_t *setup)
{
uint32_t reg;
{
uint32_t reg;
/* code and nvdata must be aligned to 256 bytes
* data must be aligned to 64 bytes
*/
if( (setup->codestart & 0xFF) || (setup->nvdatastart & 0xFF) || (setup->datastart & 0x3F) )
{
return -1;
}
/* code and nvdata must be aligned to 256 bytes
* data must be aligned to 64 bytes
*/
/* code and nvdata length must be a multiple of 256 bytes
* data length must be a multiple of 64 bytes
*/
if( (setup->codelen & 0xFF) || (setup->nvdatalen & 0xFF) || (setup->datalen & 0x3F) )
{
return -1;
}
if ((setup->codestart & 0xff) != 0 || (setup->nvdatastart & 0xff) != 0 ||
(setup->datastart & 0x3f) != 0)
{
return -EINVAL;
}
/*
* code and nvdata must be in flash
* data must be in SRAM1
*/
if( (setup->codestart & STM32L4_REGION_MASK) != STM32L4_FLASH_BASE)
{
return -1;
}
/* code and nvdata length must be a multiple of 256 bytes
* data length must be a multiple of 64 bytes
*/
if( (setup->nvdatastart & STM32L4_REGION_MASK) != STM32L4_FLASH_BASE)
{
return -1;
}
if ((setup->codelen & 0xff) != 0 || (setup->nvdatalen & 0xff) != 0 ||
(setup->datalen & 0x3f) != 0)
{
return -EINVAL;
}
/* Define address and length registers */
modifyreg32(STM32L4_FIREWALL_CSSA , FIREWALL_CSSADD_MASK , setup->codestart );
modifyreg32(STM32L4_FIREWALL_CSL , FIREWALL_CSSLENG_MASK , setup->codelen );
modifyreg32(STM32L4_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK , setup->nvdatastart);
modifyreg32(STM32L4_FIREWALL_NVDSL , FIREWALL_NVDSLENG_MASK, setup->nvdatalen );
modifyreg32(STM32L4_FIREWALL_VDSSA , FIREWALL_VDSADD_MASK , setup->datastart );
modifyreg32(STM32L4_FIREWALL_VDSL , FIREWALL_VDSLENG_MASK , setup->datalen );
/* code and nvdata must be in flash
* data must be in SRAM1
*/
/* Define access options */
reg = getreg32(STM32L4_FIREWALL_CR);
if(setup->datashared)
{
reg |= FIREWALL_CR_VDS;
}
if(setup->dataexec)
{
reg |= FIREWALL_CR_VDE;
}
if ((setup->codestart & STM32L4_REGION_MASK) != STM32L4_FLASH_BASE)
{
return -EINVAL;
}
putreg32(reg, STM32L4_FIREWALL_CR);
if ((setup->nvdatastart & STM32L4_REGION_MASK) != STM32L4_FLASH_BASE)
{
return -EINVAL;
}
/* Enable firewall */
reg = getreg32(STM32L4_SYSCFG_CFGR1);
reg &= ~SYSCFG_CFGR1_FWDIS;
putreg32(reg, STM32L4_SYSCFG_CFGR1);
/* Define address and length registers */
/* Now protected code can only be accessed by jumping to the FW gate */
return 0;
}
modifyreg32(STM32L4_FIREWALL_CSSA, FIREWALL_CSSADD_MASK,
setup->codestart);
modifyreg32(STM32L4_FIREWALL_CSL, FIREWALL_CSSLENG_MASK,
setup->codelen);
modifyreg32(STM32L4_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK,
setup->nvdatastart);
modifyreg32(STM32L4_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK,
setup->nvdatalen);
modifyreg32(STM32L4_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK,
setup->datastart);
modifyreg32(STM32L4_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK,
setup->datalen);
/* Define access options */
reg = getreg32(STM32L4_FIREWALL_CR);
if (setup->datashared)
{
reg |= FIREWALL_CR_VDS;
}
if (setup->dataexec)
{
reg |= FIREWALL_CR_VDE;
}
putreg32(reg, STM32L4_FIREWALL_CR);
/* Enable firewall */
reg = getreg32(STM32L4_SYSCFG_CFGR1);
reg &= ~SYSCFG_CFGR1_FWDIS;
putreg32(reg, STM32L4_SYSCFG_CFGR1);
/* Now protected code can only be accessed by jumping to the FW gate */
return 0;
}

21
arch/arm/src/stm32l4/stm32l4_firewall.h
View file

@ -64,16 +64,16 @@
************************************************************************************/
struct stm32l4_firewall_t
{
uintptr_t codestart;
size_t codelen;
uintptr_t nvdatastart;
size_t nvdatalen;
uintptr_t datastart;
size_t datalen;
uint8_t datashared:1;
uint8_t dataexec :1;
};
{
uintptr_t codestart;
size_t codelen;
uintptr_t nvdatastart;
size_t nvdatalen;
uintptr_t datastart;
size_t datalen;
uint8_t datashared : 1;
uint8_t dataexec : 1;
};
/************************************************************************************
* Public Data
@ -114,4 +114,3 @@ int stm32l4_firewallsetup(FAR struct stm32l4_firewall_t *setup);
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FIREWALL_H */

348
arch/arm/src/stm32l4/stm32l4_otgfsdev.c
View file

@ -69,7 +69,8 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_STM32L4_SYSCFG
# error "CONFIG_STM32L4_SYSCFG is required"
@ -251,6 +252,7 @@
OTGFS_GINT_WKUP)
/* Debug ***********************************************************************/
/* Trace error codes */
#define STM32L4_TRACEERR_ALLOCFAIL 0x01
@ -588,6 +590,7 @@ static bool stm32l4_req_addlast(FAR struct stm32l4_ep_s *privep,
FAR struct stm32l4_req_s *req);
/* Low level data transfers and request operations *****************************/
/* Special endpoint 0 data transfer logic */
static void stm32l4_ep0in_setupresponse(FAR struct stm32l4_usbdev_s *priv,
@ -610,11 +613,14 @@ static void stm32l4_epin_request(FAR struct stm32l4_usbdev_s *priv,
static void stm32l4_rxfifo_read(FAR struct stm32l4_ep_s *privep,
FAR uint8_t *dest, uint16_t len);
static void stm32l4_rxfifo_discard(FAR struct stm32l4_ep_s *privep, int len);
static void stm32l4_rxfifo_discard(FAR struct stm32l4_ep_s *privep,
int len);
static void stm32l4_epout_complete(FAR struct stm32l4_usbdev_s *priv,
FAR struct stm32l4_ep_s *privep);
static inline void stm32l4_ep0out_receive(FAR struct stm32l4_ep_s *privep, int bcnt);
static inline void stm32l4_epout_receive(FAR struct stm32l4_ep_s *privep, int bcnt);
static inline void stm32l4_ep0out_receive(FAR struct stm32l4_ep_s *privep,
int bcnt);
static inline void stm32l4_epout_receive(FAR struct stm32l4_ep_s *privep,
int bcnt);
static void stm32l4_epout_request(FAR struct stm32l4_usbdev_s *priv,
FAR struct stm32l4_ep_s *privep);
@ -649,7 +655,8 @@ static inline void stm32l4_epout_interrupt(FAR struct stm32l4_usbdev_s *priv);
static inline void stm32l4_epin_runtestmode(FAR struct stm32l4_usbdev_s *priv);
static inline void stm32l4_epin(FAR struct stm32l4_usbdev_s *priv, uint8_t epno);
static inline void stm32l4_epin_txfifoempty(FAR struct stm32l4_usbdev_s *priv, int epno);
static inline void stm32l4_epin_txfifoempty(FAR struct stm32l4_usbdev_s *priv,
int epno);
static inline void stm32l4_epin_interrupt(FAR struct stm32l4_usbdev_s *priv);
/* Other second level interrupt processing */
@ -669,9 +676,11 @@ static inline void stm32l4_otginterrupt(FAR struct stm32l4_usbdev_s *priv);
/* First level interrupt processing */
static int stm32l4_usbinterrupt(int irq, FAR void *context, FAR void *arg);
static int stm32l4_usbinterrupt(int irq, FAR void *context,
FAR void *arg);
/* Endpoint operations *********************************************************/
/* Global OUT NAK controls */
static void stm32l4_enablegonak(FAR struct stm32l4_ep_s *privep);
@ -702,8 +711,10 @@ static void stm32l4_ep_freereq(FAR struct usbdev_ep_s *ep,
/* Endpoint buffer management */
#ifdef CONFIG_USBDEV_DMA
static void *stm32l4_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes);
static void stm32l4_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf);
static void *stm32l4_ep_allocbuffer(FAR struct usbdev_ep_s *ep,
unsigned bytes);
static void stm32l4_ep_freebuffer(FAR struct usbdev_ep_s *ep,
FAR void *buf);
#endif
/* Endpoint request submission */
@ -751,6 +762,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv);
/****************************************************************************
* Private Data
****************************************************************************/
/* Since there is only a single USB interface, all status information can be
* be simply retained in a single global instance.
*/
@ -904,8 +916,8 @@ static uint32_t stm32l4_getreg(uint32_t addr)
uint32_t val = getreg32(addr);
/* Is this the same value that we read from the same register last time? Are
* we polling the register? If so, suppress some of the output.
/* Is this the same value that we read from the same register last time?
* Are we polling the register? If so, suppress some of the output.
*/
if (addr == prevaddr && val == preval)
@ -977,7 +989,8 @@ static void stm32l4_putreg(uint32_t val, uint32_t addr)
*
****************************************************************************/
static FAR struct stm32l4_req_s *stm32l4_req_remfirst(FAR struct stm32l4_ep_s *privep)
static FAR struct stm32l4_req_s *
stm32l4_req_remfirst(FAR struct stm32l4_ep_s *privep)
{
FAR struct stm32l4_req_s *ret = privep->head;
@ -1047,7 +1060,8 @@ static void stm32l4_ep0in_setupresponse(FAR struct stm32l4_usbdev_s *priv,
*
****************************************************************************/
static inline void stm32l4_ep0in_transmitzlp(FAR struct stm32l4_usbdev_s *priv)
static inline void
stm32l4_ep0in_transmitzlp(FAR struct stm32l4_usbdev_s *priv)
{
stm32l4_ep0in_setupresponse(priv, NULL, 0);
}
@ -1199,7 +1213,8 @@ static void stm32l4_epin_transfer(FAR struct stm32l4_ep_s *privep,
* perform the transfer.
*/
pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket;
pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) /
privep->ep.maxpacket;
}
/* Set the XFRSIZ and PKTCNT */
@ -1324,9 +1339,9 @@ static void stm32l4_epin_request(FAR struct stm32l4_usbdev_s *priv,
privep->epphy, privreq, privreq->req.len,
privreq->req.xfrd, privep->zlp);
/* Check for a special case: If we are just starting a request (xfrd==0) and
* the class driver is trying to send a zero-length packet (len==0). Then set
* the ZLP flag so that the packet will be sent.
/* Check for a special case: If we are just starting a request (xfrd==0)
* and the class driver is trying to send a zero-length packet (len==0).
* Then set the ZLP flag so that the packet will be sent.
*/
if (privreq->req.len == 0)
@ -1422,7 +1437,8 @@ static void stm32l4_epin_request(FAR struct stm32l4_usbdev_s *priv,
regval = stm32l4_getreg(regaddr);
if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval);
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EMPWAIT),
(uint16_t)regval);
/* There is insufficient space in the TxFIFO. Wait for a TxFIFO
* empty interrupt and try again.
@ -1551,7 +1567,7 @@ static void stm32l4_rxfifo_discard(FAR struct stm32l4_ep_s *privep, int len)
(void)data;
}
uinfo("<<< discarding %d\n",len);
uinfo("<<< discarding %d\n", len);
}
}
@ -2782,6 +2798,7 @@ static inline void stm32l4_epout_interrupt(FAR struct stm32l4_usbdev_s *priv)
*/
#if 1
/* REVISIT: */
if ((doepint & OTGFS_DOEPINT_EPDISD) != 0)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_EPDISD),
@ -3016,6 +3033,7 @@ static inline void stm32l4_epin_interrupt(FAR struct stm32l4_usbdev_s *priv)
diepint = stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno)) & mask;
/* Decode and process the enabled, pending interrupts */
/* Transfer completed interrupt */
if ((diepint & OTGFS_DIEPINT_XFRC) != 0)
@ -3225,157 +3243,155 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv)
int bcnt;
int epphy;
while(0 != (stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL))
while (0 != (stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL))
{
/* Get the status from the top of the FIFO */
/* Get the status from the top of the FIFO */
regval = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP);
regval = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP);
/* Decode status fields */
/* Decode status fields */
epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT;
epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT;
/* Workaround for bad values read from the STM32L4_OTGFS_GRXSTSP register
* happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c
* All of which provide out of range indexes for epout[epphy]
*/
/* Workaround for bad values read from the STM32L4_OTGFS_GRXSTSP register
* happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c
* All of which provide out of range indexes for epout[epphy]
*/
if (epphy < STM32L4_NENDPOINTS)
{
privep = &priv->epout[epphy];
if (epphy < STM32L4_NENDPOINTS)
{
privep = &priv->epout[epphy];
/* Handle the RX event according to the packet status field */
/* Handle the RX event according to the packet status field */
switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
{
/* Global OUT NAK. This indicate that the global OUT NAK bit has taken
* effect.
*
* PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
* Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTNAK), 0);
/* Global OUT NAK. This indicate that the global OUT NAK bit has taken
* effect.
*
* PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
* Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTNAK), 0);
}
break;
/* OUT data packet received.
*
* PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
* EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTRECVD), epphy);
bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
if (bcnt > 0)
{
stm32l4_epout_receive(privep, bcnt);
}
}
break;
/* OUT transfer completed. This indicates that an OUT data transfer for
* the specified OUT endpoint has completed. After this entry is popped
* from the receive FIFO, the core asserts a Transfer Completed interrupt
* on the specified OUT endpoint.
*
* PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
* which the data transfer is complete, DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTDONE), epphy);
}
break;
/* SETUP transaction completed. This indicates that the Setup stage for
* the specified endpoint has completed and the Data stage has started.
* After this entry is popped from the receive FIFO, the core asserts a
* Setup interrupt on the specified control OUT endpoint (triggers an
* interrupt).
*
* PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
* DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), epphy);
/* On the L4 This event does not occur on the next SETUP
* after a SETUP OUT.
*/
}
break;
/* SETUP data packet received. This indicates that a SETUP packet for the
* specified endpoint is now available for reading from the receive FIFO.
*
* PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
{
uint16_t datlen;
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPRECVD), epphy);
/* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
* the last one overwrites the previous setup packets and only that
* last SETUP packet will be processed.
*/
stm32l4_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
USB_SIZEOF_CTRLREQ);
/* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
* then we need to wait for the completion of the data phase to
* process the setup command. If it is an IN SETUP packet, then
* we must processing the command BEFORE we enter the DATA phase.
*
* If the data associated with the OUT SETUP packet is zero length,
* then, of course, we don't need to wait.
*/
datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{
/* Reset the endpoint and Stop NAK-ing */
stm32l4_ep0out_ctrlsetup(priv);
/* Wait for the data phase. */
priv->ep0state = EP0STATE_SETUP_OUT;
}
else
{
/* We can process the setup data Now no need to wait for SETUP done word
* to be popped of the RxFIFO.
*/
priv->ep0state = EP0STATE_SETUP_READY;
stm32l4_ep0out_setup(priv);
}
}
break;
default:
{
usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS),
(regval & OTGFS_GRXSTSD_PKTSTS_MASK) >>
OTGFS_GRXSTSD_PKTSTS_SHIFT);
}
break;
}
break;
/* OUT data packet received.
*
* PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
* EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTRECVD), epphy);
bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
if (bcnt > 0)
{
stm32l4_epout_receive(privep, bcnt);
}
}
break;
/* OUT transfer completed. This indicates that an OUT data transfer for
* the specified OUT endpoint has completed. After this entry is popped
* from the receive FIFO, the core asserts a Transfer Completed interrupt
* on the specified OUT endpoint.
*
* PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
* which the data transfer is complete, DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTDONE), epphy);
}
break;
/* SETUP transaction completed. This indicates that the Setup stage for
* the specified endpoint has completed and the Data stage has started.
* After this entry is popped from the receive FIFO, the core asserts a
* Setup interrupt on the specified control OUT endpoint (triggers an
* interrupt).
*
* PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
* DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
{
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), epphy);
/* On the L4 This event does not occur on the next SETUP
* after a SETUP OUT.
*/
}
break;
/* SETUP data packet received. This indicates that a SETUP packet for the
* specified endpoint is now available for reading from the receive FIFO.
*
* PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
{
uint16_t datlen;
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPRECVD), epphy);
/* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
* the last one overwrites the previous setup packets and only that
* last SETUP packet will be processed.
*/
stm32l4_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
USB_SIZEOF_CTRLREQ);
/* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
* then we need to wait for the completion of the data phase to
* process the setup command. If it is an IN SETUP packet, then
* we must processing the command BEFORE we enter the DATA phase.
*
* If the data associated with the OUT SETUP packet is zero length,
* then, of course, we don't need to wait.
*/
datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{
/* Reset the endpoint and Stop NAK-ing */
stm32l4_ep0out_ctrlsetup(priv);
/* Wait for the data phase. */
priv->ep0state = EP0STATE_SETUP_OUT;
}
else
{
/* We can process the setup data Now no need to wait for SETUP done word
* to be popped of the RxFIFO.
*/
priv->ep0state = EP0STATE_SETUP_READY;
stm32l4_ep0out_setup(priv);
}
}
break;
default:
{
usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS),
(regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT);
}
break;
}
}
}
}
}
@ -3498,7 +3514,8 @@ static inline void stm32l4_isocoutinterrupt(FAR struct stm32l4_usbdev_s *priv)
/* When it receives an IISOOXFR interrupt, the application must read the
* control registers of all isochronous OUT endpoints to determine which
* endpoints had an incomplete transfer in the current microframe. An
* endpoint transfer is incomplete if both the following conditions are true:
* endpoint transfer is incomplete if both the following conditions are
* true:
*
* DOEPCTLx:EONUM = DSTS:SOFFN[0], and
* DOEPCTLx:EPENA = 1
@ -3644,7 +3661,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context, FAR void *arg)
stm32l4_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), STM32L4_OTGFS_GINTSTS);
/* Break out of the loop when there are no further pending (and
* unmasked) interrupts to be processes.
*/
@ -4018,7 +4034,6 @@ static int stm32l4_epin_configure(FAR struct stm32l4_ep_s *privep, uint8_t eptyp
mpsiz = (maxpacket << OTGFS_DIEPCTL_MPSIZ_SHIFT);
}
/* If the endpoint is already active don't change the endpoint control
* register.
*/
@ -4032,7 +4047,8 @@ static int stm32l4_epin_configure(FAR struct stm32l4_ep_s *privep, uint8_t eptyp
regval |= OTGFS_DIEPCTL_CNAK;
}
regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | OTGFS_DIEPCTL_TXFNUM_MASK);
regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK |
OTGFS_DIEPCTL_TXFNUM_MASK);
regval |= mpsiz;
regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT);
regval |= (privep->epphy << OTGFS_DIEPCTL_TXFNUM_SHIFT);
@ -4163,6 +4179,7 @@ static void stm32l4_epout_disable(FAR struct stm32l4_ep_s *privep)
while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0);
#else
/* REVISIT: */
up_udelay(10);
#endif
@ -4594,6 +4611,7 @@ static int stm32l4_epout_setstall(FAR struct stm32l4_ep_s *privep)
while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0);
#else
/* REVISIT: */
up_udelay(10);
#endif
@ -5392,7 +5410,6 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv)
stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(5));
#endif
/* Flush the FIFOs */
stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL);
@ -5561,7 +5578,8 @@ void up_usbinitialize(void)
#endif
/* Uninitialize the hardware so that we know that we are starting from a
* known state. */
* known state.
*/
up_usbuninitialize();

123
arch/arm/src/stm32l4/stm32l4_qspi.c
View file

@ -87,6 +87,7 @@
#define IS_ALIGNED(n) (((uint32_t)(n) & ALIGN_MASK) == 0)
/* Debug *******************************************************************/
/* Check if QSPI debug is enabled */
#ifndef CONFIG_DEBUG_DMA
@ -155,6 +156,7 @@
#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS)
/* Clocking *****************************************************************/
/* The QSPI bit rate clock is generated by dividing the peripheral clock by
* a value between 1 and 255
*/
@ -188,7 +190,7 @@ struct stm32l4_qspidev_s
xcpt_t handler; /* Interrupt handler */
uint8_t irq; /* Interrupt number */
sem_t op_sem; /* Block until complete */
struct qspi_xctnspec_s *xctn; /* context of transaction in progress*/
struct qspi_xctnspec_s *xctn; /* context of transaction in progress */
#endif
#ifdef CONFIG_STM32L4_QSPI_DMA
@ -493,12 +495,12 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg)
spiinfo("%s:\n", msg);
#if 0
/* this extra verbose output may be helpful in some cases; you'll need
to make sure your syslog is large enough to accomodate the extra output.
/* This extra verbose output may be helpful in some cases; you'll need
* to make sure your syslog is large enough to accomodate the extra output.
*/
regval = getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET); /* Control Register */
spiinfo("CR:%08x\n",regval);
spiinfo("CR:%08x\n", regval);
spiinfo(" EN:%1d ABORT:%1d DMAEN:%1d TCEN:%1d SSHIFT:%1d\n"
" FTHRES: %d\n"
" TEIE:%1d TCIE:%1d FTIE:%1d SMIE:%1d TOIE:%1d APMS:%1d PMM:%1d\n"
@ -519,14 +521,14 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg)
(regval & QSPI_CR_PRESCALER_MASK) >> QSPI_CR_PRESCALER_SHIFT);
regval = getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET); /* Device Configuration Register */
spiinfo("DCR:%08x\n",regval);
spiinfo("DCR:%08x\n", regval);
spiinfo(" CKMODE:%1d CSHT:%d FSIZE:%d\n",
(regval & QSPI_DCR_CKMODE) ? 1 : 0,
(regval & QSPI_DCR_CSHT_MASK) >> QSPI_DCR_CSHT_SHIFT,
(regval & QSPI_DCR_FSIZE_MASK) >> QSPI_DCR_FSIZE_SHIFT);
regval = getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */
spiinfo("CCR:%08x\n",regval);
spiinfo("CCR:%08x\n", regval);
spiinfo(" INST:%02x IMODE:%d ADMODE:%d ADSIZE:%d ABMODE:%d\n"
" ABSIZE:%d DCYC:%d DMODE:%d FMODE:%d\n"
" SIOO:%1d DDRM:%1d\n",
@ -543,7 +545,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg)
(regval & QSPI_CCR_DDRM) ? 1 : 0);
regval = getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET); /* Status Register */
spiinfo("SR:%08x\n",regval);
spiinfo("SR:%08x\n", regval);
spiinfo(" TEF:%1d TCF:%1d FTF:%1d SMF:%1d TOF:%1d BUSY:%1d FLEVEL:%d\n",
(regval & QSPI_SR_TEF) ? 1 : 0,
(regval & QSPI_SR_TCF) ? 1 : 0,
@ -579,22 +581,22 @@ static void qspi_dumpgpioconfig(const char *msg)
spiinfo("%s:\n", msg);
regval = getreg32(STM32L4_GPIOE_MODER);
spiinfo("E_MODER:%08x\n",regval);
spiinfo("E_MODER:%08x\n", regval);
regval = getreg32(STM32L4_GPIOE_OTYPER);
spiinfo("E_OTYPER:%08x\n",regval);
spiinfo("E_OTYPER:%08x\n", regval);
regval = getreg32(STM32L4_GPIOE_OSPEED);
spiinfo("E_OSPEED:%08x\n",regval);
spiinfo("E_OSPEED:%08x\n", regval);
regval = getreg32(STM32L4_GPIOE_PUPDR);
spiinfo("E_PUPDR:%08x\n",regval);
spiinfo("E_PUPDR:%08x\n", regval);
regval = getreg32(STM32L4_GPIOE_AFRL);
spiinfo("E_AFRL:%08x\n",regval);
spiinfo("E_AFRL:%08x\n", regval);
regval = getreg32(STM32L4_GPIOE_AFRH);
spiinfo("E_AFRH:%08x\n",regval);
spiinfo("E_AFRH:%08x\n", regval);
}
#endif
@ -645,6 +647,7 @@ static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv)
stm32l4_dmasample(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER]);
/* Then dump the sampled DMA registers */
/* Initial register values */
stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_INITIAL],
@ -684,7 +687,6 @@ static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv)
}
#endif
/****************************************************************************
* Name: qspi_setupxctnfromcmd
*
@ -726,6 +728,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
DEBUGASSERT(cmdinfo->cmd < 256);
/* Specify the instruction as per command info */
/* XXX III instruction mode, single dual quad option bits */
xctn->instrmode = CCR_IMODE_SINGLE;
@ -1009,7 +1012,7 @@ static void qspi_abort(struct stm32l4_qspidev_s *priv)
****************************************************************************/
static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv,
struct qspi_xctnspec_s* xctn,
struct qspi_xctnspec_s *xctn,
uint8_t fctn)
{
uint32_t regval;
@ -1083,16 +1086,19 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
if ((status & QSPI_SR_FTF) && (cr & QSPI_CR_FTIE))
{
volatile uint32_t *datareg = (volatile uint32_t*)(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
volatile uint32_t *datareg = (volatile uint32_t *)
(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
if (g_qspi0dev.xctn->function == CCR_FMODE_INDWR)
{
/* Write data until we have no more or have no place to put it */
while((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF)
while ((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF)
{
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
{
*(volatile uint8_t *)datareg = ((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow];
*(volatile uint8_t *)datareg = ((uint8_t *)
g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow];
++g_qspi0dev.xctn->idxnow;
}
else
@ -1107,11 +1113,12 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
{
/* Read data until we have no more or have no place to put it */
while((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF)
while ((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF)
{
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
{
((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] = *(volatile uint8_t *)datareg;
((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] =
*(volatile uint8_t *)datareg;
++g_qspi0dev.xctn->idxnow;
}
else
@ -1142,15 +1149,18 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD)
{
volatile uint32_t *datareg = (volatile uint32_t*)(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
volatile uint32_t *datareg = (volatile uint32_t *)
(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
/* Read any remaining data */
while(((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FLEVEL_MASK) != 0)
while (((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) &
QSPI_SR_FLEVEL_MASK) != 0)
{
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
{
((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] = *(volatile uint8_t *)datareg;
((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] =
*(volatile uint8_t *)datareg;
++g_qspi0dev.xctn->idxnow;
}
else
@ -1335,11 +1345,11 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
/* Save the result of the transfer if no error was previously reported */
if ( isr & DMA_CHAN_TCIF_BIT )
if (isr & DMA_CHAN_TCIF_BIT)
{
priv->result = OK;
}
else if ( isr & DMA_CHAN_TEIF_BIT )
else if (isr & DMA_CHAN_TEIF_BIT)
{
priv->result = -EIO;
}
@ -1402,13 +1412,15 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
{
/* Setup the DMA (memory-to-peripheral) */
dmaflags = (QSPI_DMA_PRIO | DMA_CCR_MSIZE_8BITS | DMA_CCR_PSIZE_8BITS | DMA_CCR_MINC | DMA_CCR_DIR);
dmaflags = (QSPI_DMA_PRIO | DMA_CCR_MSIZE_8BITS | DMA_CCR_PSIZE_8BITS |
DMA_CCR_MINC | DMA_CCR_DIR);
}
else
{
/* Setup the DMA (peripheral-to-memory) */
dmaflags = (QSPI_DMA_PRIO | DMA_CCR_MSIZE_8BITS | DMA_CCR_PSIZE_8BITS | DMA_CCR_MINC );
dmaflags = (QSPI_DMA_PRIO | DMA_CCR_MSIZE_8BITS | DMA_CCR_PSIZE_8BITS |
DMA_CCR_MINC);
}
stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv, STM32L4_QUADSPI_DR_OFFSET),
@ -1425,7 +1437,8 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
/* Set up the Communications Configuration Register as per command info */
qspi_ccrconfig(priv, xctn,
QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD);
QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR :
CCR_FMODE_INDRD);
/* Start the DMA */
@ -1488,8 +1501,8 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
/* Wait for Transfer complete, and not busy */
qspi_waitstatusflags(priv, QSPI_SR_TCF,1);
qspi_waitstatusflags(priv, QSPI_SR_BUSY,0);
qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0);
MEMORY_SYNC();
/* Dump the sampled DMA registers */
@ -1535,11 +1548,12 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
****************************************************************************/
static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
struct qspi_xctnspec_s* xctn)
struct qspi_xctnspec_s *xctn)
{
int ret = OK;
volatile uint32_t *datareg = (volatile uint32_t*)(priv->base + STM32L4_QUADSPI_DR_OFFSET);
uint8_t *dest = (uint8_t*)xctn->buffer;
volatile uint32_t *datareg =
(volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET);
uint8_t *dest = (uint8_t *)xctn->buffer;
uint32_t addrval;
uint32_t regval;
@ -1567,9 +1581,9 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
{
/* Wait for Fifo Threshold, or Transfer Complete, to read data */
qspi_waitstatusflags(priv, QSPI_SR_FTF|QSPI_SR_TCF, 1);
qspi_waitstatusflags(priv, QSPI_SR_FTF | QSPI_SR_TCF, 1);
*dest = *(volatile uint8_t*)datareg;
*dest = *(volatile uint8_t *)datareg;
dest++;
remaining--;
}
@ -1610,11 +1624,12 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
****************************************************************************/
static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv,
struct qspi_xctnspec_s* xctn)
struct qspi_xctnspec_s *xctn)
{
int ret = OK;
volatile uint32_t *datareg = (volatile uint32_t*)(priv->base + STM32L4_QUADSPI_DR_OFFSET);
uint8_t *src = (uint8_t*)xctn->buffer;
volatile uint32_t *datareg =
(volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET);
uint8_t *src = (uint8_t *)xctn->buffer;
if (src != NULL)
{
@ -1630,7 +1645,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv,
qspi_waitstatusflags(priv, QSPI_SR_FTF, 1);
*(volatile uint8_t*)datareg = *src++;
*(volatile uint8_t *)datareg = *src++;
remaining--;
}
@ -1824,12 +1839,13 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode)
uint32_t regval;
if (priv->memmap)
{
/* XXX we have no better return here, but the caller will find out
* in their subsequent calls.
*/
return;
}
{
/* XXX we have no better return here, but the caller will find out
* in their subsequent calls.
*/
return;
}
spiinfo("mode=%d\n", mode);
@ -2076,8 +2092,8 @@ static int qspi_command(struct qspi_dev_s *dev,
/* Wait for Transfer complete, and not busy */
qspi_waitstatusflags(priv, QSPI_SR_TCF,1);
qspi_waitstatusflags(priv, QSPI_SR_BUSY,0);
qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0);
#endif
@ -2233,8 +2249,8 @@ static int qspi_memory(struct qspi_dev_s *dev,
/* Wait for Transfer complete, and not busy */
qspi_waitstatusflags(priv, QSPI_SR_TCF,1);
qspi_waitstatusflags(priv, QSPI_SR_BUSY,0);
qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0);
MEMORY_SYNC();
}
@ -2263,8 +2279,8 @@ static int qspi_memory(struct qspi_dev_s *dev,
/* Wait for Transfer complete, and not busy */
qspi_waitstatusflags(priv, QSPI_SR_TCF,1);
qspi_waitstatusflags(priv, QSPI_SR_BUSY,0);
qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0);
MEMORY_SYNC();
@ -2487,6 +2503,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
if (!priv->initialized)
{
/* Now perform one time initialization */
/* Initialize the QSPI semaphore that enforces mutually exclusive
* access to the QSPI registers.
*/
@ -2603,7 +2620,7 @@ errout_with_dmahandles:
*
****************************************************************************/
void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s* dev,
void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev,
const struct qspi_meminfo_s *meminfo,
uint32_t lpto)
{
@ -2694,7 +2711,7 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s* dev,
*
****************************************************************************/
void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s* dev)
void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev)
{
struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev;

43
arch/arm/src/tiva/common/tiva_flash.c
View file

@ -106,6 +106,7 @@ static int tiva_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg);
/****************************************************************************
* Private Data
****************************************************************************/
/* This structure holds the state of the MTD driver */
static struct tiva_dev_s g_lmdev =
@ -190,8 +191,8 @@ static int tiva_erase(FAR struct mtd_dev_s *dev, off_t startblock,
*
****************************************************************************/
static ssize_t tiva_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
FAR uint8_t *buf)
static ssize_t tiva_bread(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR uint8_t *buf)
{
DEBUGASSERT(startblock + nblocks <= TIVA_VIRTUAL_NPAGES);
@ -209,11 +210,12 @@ static ssize_t tiva_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nb
*
****************************************************************************/
static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
FAR const uint8_t *buf)
static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR const uint8_t *buf)
{
FAR uint32_t *src = (uint32_t *)buf;
FAR uint32_t *dst = (uint32_t *)(TIVA_VIRTUAL_BASE + startblock * TIVA_FLASH_PAGESIZE);
FAR uint32_t *dst = (uint32_t *)(TIVA_VIRTUAL_BASE +
startblock * TIVA_FLASH_PAGESIZE);
int i;
DEBUGASSERT(nblocks <= TIVA_VIRTUAL_NPAGES);
@ -248,8 +250,8 @@ static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
*
****************************************************************************/
static ssize_t tiva_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
FAR uint8_t *buf)
static ssize_t tiva_read(FAR struct mtd_dev_s *dev, off_t offset,
size_t nbytes, FAR uint8_t *buf)
{
DEBUGASSERT(offset + nbytes < TIVA_VIRTUAL_NPAGES * TIVA_FLASH_PAGESIZE);
@ -268,15 +270,16 @@ static ssize_t tiva_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
****************************************************************************/
#ifdef CONFIG_MTD_BYTE_WRITE
static ssize_t tiva_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
FAR const uint8_t *buf)
static ssize_t tiva_write(FAR struct mtd_dev_s *dev, off_t offset,
size_t nbytes, FAR const uint8_t *buf)
{
FAR const uint32_t *src = (uint32_t *)((uintptr_t)buf & ~3);
ssize_t remaining;
uint32_t regval;
DEBUGASSERT(dev != NULL && buf != NULL);
DEBUGASSERT(((uintptr_t)buf & 3) == 0 && (offset & 3) == 0 && (nbytes && 3) == 0);
DEBUGASSERT(((uintptr_t)buf & 3) == 0 && (offset & 3) == 0 &&
(nbytes && 3) == 0);
/* Clear the flash access and error interrupts. */
@ -302,8 +305,8 @@ static ssize_t tiva_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
/* Loop over the words in this 32-word block. */
while(((offset & 0x7c) || (getreg32(TIVA_FLASH_FWBN) == 0)) &&
(remaining > 0))
while (((offset & 0x7c) || (getreg32(TIVA_FLASH_FWBN) == 0)) &&
(remaining > 0))
{
/* Write this word into the write buffer. */
@ -318,7 +321,7 @@ static ssize_t tiva_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
/* Wait until the write buffer has been programmed. */
while(getreg32(TIVA_FLASH_FMC2) & FLASH_FMC2_WRBUF)
while (getreg32(TIVA_FLASH_FMC2) & FLASH_FMC2_WRBUF)
{
}
}
@ -333,7 +336,7 @@ static ssize_t tiva_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
/* Wait until the word has been programmed. */
while(getreg32(TIVA_FLASH_FMC) & FLASH_FMC_WRITE);
while (getreg32(TIVA_FLASH_FMC) & FLASH_FMC_WRITE);
/* Increment to the next word. */
@ -373,13 +376,13 @@ static int tiva_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)arg;
if (geo)
{
/* Populate the geometry structure with information needed to know
* the capacity and how to access the device.
/* Populate the geometry structure with information needed to
* know the capacity and how to access the device.
*
* NOTE: that the device is treated as though it where just an array
* of fixed size blocks. That is most likely not true, but the client
* will expect the device logic to do whatever is necessary to make it
* appear so.
* NOTE: that the device is treated as though it where just an
* array of fixed size blocks. That is most likely not true,
* but the client will expect the device logic to do whatever
* is necessary to make it appear so.
*/
geo->blocksize = TIVA_FLASH_PAGESIZE; /* Size of one read/write block */

4
arch/arm/src/tms570/tms570_boot.c
View file

@ -197,7 +197,7 @@ static void tms570_memory_initialize(uint32_t ramset)
/* Wait until Memory Hardware Initialization complete */
while((getreg32(TMS570_SYS_MSTCGSTAT) & SYS_MSTCGSTAT_MINIDONE) == 0);
while ((getreg32(TMS570_SYS_MSTCGSTAT) & SYS_MSTCGSTAT_MINIDONE) == 0);
/* Disable Memory Hardware Initialization */
@ -419,11 +419,13 @@ void arm_boot(void)
#ifdef CONFIG_TMS570_SELFTEST
/* Test the parity protection mechanism for peripheral RAMs */
#warning Missing logic
#endif
#ifdef CONFIG_TMS570_MIBASPI1
/* Wait for MibSPI1 RAM to complete initialization */
#warning Missing logic
#endif

64
arch/arm/src/tms570/tms570_clockconfig.c
View file

@ -145,36 +145,36 @@ static uint32_t check_frequency(uint32_t cnt1_clksrc)
(uint32_t)((uint32_t)0x5u << 4u) | /* No Error Interrupt */
(uint32_t)((uint32_t)0xau << 8u) | /* Single Shot mode */
(uint32_t)((uint32_t)0x5u << 12u); /* No Done Interrupt */
putreg32(regval,TMS570_DCC_BASE);
putreg32(regval, TMS570_DCC_BASE);
/* Clear ERR and DONE bits */
regval = 3u;
putreg32(regval,TMS570_DCC_BASE + 0x14);
putreg32(regval, TMS570_DCC_BASE + 0x14);
/* DCC1 Clock0 Counter Seed value configuration */
regval = 68u;
putreg32(regval,TMS570_DCC_BASE + 0x08);
putreg32(regval, TMS570_DCC_BASE + 0x08);
/* DCC1 Clock0 Valid Counter Seed value configuration */
regval = 4u;
putreg32(regval,TMS570_DCC_BASE + 0x0c);
putreg32(regval, TMS570_DCC_BASE + 0x0c);
/* DCC1 Clock1 Counter Seed value configuration */
regval = 972u;
putreg32(regval,TMS570_DCC_BASE + 0x10);
putreg32(regval, TMS570_DCC_BASE + 0x10);
/* DCC1 Clock1 Source 1 Select */
regval = (uint32_t)((uint32_t)10u << 12u) | /* DCC Enable / Disable Key */
(uint32_t) cnt1_clksrc; /* DCC1 Clock Source 1 */
putreg32(regval,TMS570_DCC_BASE + 0x24);
putreg32(regval, TMS570_DCC_BASE + 0x24);
regval = (uint32_t)15; /* DCC1 Clock Source 0 */
putreg32(regval,TMS570_DCC_BASE + 0x28);
putreg32(regval, TMS570_DCC_BASE + 0x28);
/* DCC1 Global Control register configuration */
@ -183,8 +183,8 @@ static uint32_t check_frequency(uint32_t cnt1_clksrc)
(uint32_t)((uint32_t)0xau << 8u) | /* Single Shot mode */
(uint32_t)((uint32_t)0x5u << 12u); /* No Done Interrupt */
putreg32(regval,TMS570_DCC_BASE);
while(getreg32(TMS570_DCC_BASE + 0x14) == 0u)
putreg32(regval, TMS570_DCC_BASE);
while (getreg32(TMS570_DCC_BASE + 0x14) == 0u)
{
/* Wait */
}
@ -203,7 +203,7 @@ static uint32_t check_frequency(uint32_t cnt1_clksrc)
*
****************************************************************************/
uint32_t _errata_SSWF021_45_both_plls( uint32_t count)
uint32_t _errata_SSWF021_45_both_plls(uint32_t count)
{
uint32_t failcode;
uint32_t retries;
@ -224,7 +224,7 @@ uint32_t _errata_SSWF021_45_both_plls( uint32_t count)
regval = SYS_CLKCNTL_PENA;
putreg32(regval, TMS570_SYS_CLKCNTL);
for(retries = 0u; (retries < count) || (count == 0u); retries++)
for (retries = 0u; (retries < count) || (count == 0u); retries++)
{
failcode = 0u;
@ -233,27 +233,27 @@ uint32_t _errata_SSWF021_45_both_plls( uint32_t count)
regval = 0x00000002u | 0x00000040u;
putreg32(regval, TMS570_SYS_CSDISSET);
while((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
while ((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
{
}
/* Clear Global Status Register */
regval = 0x00000301u;
putreg32(regval,TMS570_SYS_GLBSTAT);
putreg32(regval, TMS570_SYS_GLBSTAT);
/* Clear the ESM PLL slip flags */
putreg32(ESM_SR1_PLL1SLIP,TMS570_ESM_SR1);
putreg32(ESM_SR4_PLL2SLIP,TMS570_ESM_SR4);
putreg32(ESM_SR1_PLL1SLIP, TMS570_ESM_SR1);
putreg32(ESM_SR4_PLL2SLIP, TMS570_ESM_SR4);
/* Set both PLLs to OSCIN/1*27/(2*1) */
regval = 0x20001a00u;
putreg32(regval,TMS570_SYS_PLLCTL1);
putreg32(regval, TMS570_SYS_PLLCTL1);
regval = 0x3fc0723du;
putreg32(regval,TMS570_SYS_PLLCTL2);
putreg32(regval, TMS570_SYS_PLLCTL2);
regval = 0x20001a00u;
putreg32(regval, 0xffffe100);
@ -273,7 +273,7 @@ uint32_t _errata_SSWF021_45_both_plls( uint32_t count)
/* If PLL1 valid, check the frequency */
if((getreg32(TMS570_ESM_SR1) & ESM_SR1_PLL1SLIP) != 0u)
if ((getreg32(TMS570_ESM_SR1) & ESM_SR1_PLL1SLIP) != 0u)
{
failcode |= 1u;
}
@ -284,7 +284,7 @@ uint32_t _errata_SSWF021_45_both_plls( uint32_t count)
/* If PLL2 valid, check the frequency */
if((getreg32(TMS570_ESM_SR4) & ESM_SR4_PLL2SLIP) != 0u)
if ((getreg32(TMS570_ESM_SR4) & ESM_SR4_PLL2SLIP) != 0u)
{
failcode |= 2u;
}
@ -304,11 +304,11 @@ uint32_t _errata_SSWF021_45_both_plls( uint32_t count)
regval = 0x00000002U | 0x00000040U;
putreg32(regval, TMS570_SYS_CSDISSET);
while((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
while ((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
{
}
/* restore CLKCNTL, VCLKR and PENA first */
/* Restore CLKCNTL, VCLKR and PENA first */
clkcntrlsave = getreg32(TMS570_SYS_CLKCNTL);
@ -391,7 +391,7 @@ static void tms570_pll_setup(void)
regval = SYS_CSDIS_CLKSRC_PLL1 | SYS_CSDIS_CLKSRC_PLL2;
putreg32(regval, TMS570_SYS_CSDISSET);
while((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
while ((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
{
}
@ -408,16 +408,16 @@ static void tms570_pll_setup(void)
SYS_CSDIS_CLKSRC_OSC;
putreg32(regval, TMS570_SYS_CSDISSET);
while((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
while ((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
{
}
putreg32(SYS_GLBSTAT_OSC_ERR_CLR,TMS570_SYS_GLBSTAT);
putreg32(SYS_GLBSTAT_OSC_ERR_CLR, TMS570_SYS_GLBSTAT);
regval = SYS_CSDIS_CLKSRC_OSC;
putreg32(regval, TMS570_SYS_CSDISCLR);
while((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
while ((getreg32(TMS570_SYS_CSDIS) & regval) != regval)
{
}
}
@ -448,7 +448,7 @@ static void tms570_pll_setup(void)
regval = SYS_CSDIS_CLKSRC_PLL1 | SYS_CSDIS_CLKSRC_PLL2;
putreg32(regval, TMS570_SYS_CSDISCLR);
while((getreg32(TMS570_SYS_CSDIS) & regval) != 0)
while ((getreg32(TMS570_SYS_CSDIS) & regval) != 0)
{
}
}
@ -634,7 +634,9 @@ static void tms570_flash_setup(void)
putreg32(FLASH_FSMWRENA_ENABLE, TMS570_FLASH_FSMWRENA);
regval = FLASH_EEPROMCFG_GRACE(2) | FLASH_EEPROMCFG_EWAIT(BOARD_EWAIT);
putreg32(regval, TMS570_FLASH_EEPROMCFG);
//putreg32(FLASH_FSMWRENA_DISABLE, TMS570_FLASH_FSMWRENA);
#if 0
putreg32(FLASH_FSMWRENA_DISABLE, TMS570_FLASH_FSMWRENA);
#endif
putreg32(0x0a, TMS570_FLASH_FSMWRENA);
/* Setup flash bank power modes */
@ -659,8 +661,8 @@ static void tms570_clocksrc_configure(void)
uint32_t csvstat;
uint32_t csdis;
/* Disable / Enable clock domains. Writing a '1' to the CDDIS register turns
* the clock off.
/* Disable / Enable clock domains. Writing a '1' to the CDDIS register
* turns the clock off.
*
* GCLK Bit 0 On
* HCLK/VCLK_sys Bit 1 On
@ -732,7 +734,7 @@ static void tms570_clocksrc_configure(void)
putreg32(regval, TMS570_SYS_VCLKASRC);
#if defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT)
regval = SYS_VCLKASRC_VCLKA4S_VCLK |SYS_VCLKASRC_VCLKA3R_VCLK;
regval = SYS_VCLKASRC_VCLKA4S_VCLK | SYS_VCLKASRC_VCLKA3R_VCLK;
putreg32(regval, TMS570_SYS2_VCLKACON1);
#endif
@ -744,7 +746,7 @@ static void tms570_clocksrc_configure(void)
putreg32(regval, TMS570_SYS_CLKCNTL);
regval = getreg32(TMS570_SYS_CLKCNTL);
regval &= ~( SYS_CLKCNTL_VCLKR_MASK);
regval &= ~(SYS_CLKCNTL_VCLKR_MASK);
regval |= SYS_CLKCNTL_VCLKR;
putreg32(regval, TMS570_SYS_CLKCNTL);

49
arch/arm/src/xmc4/xmc4_clockconfig.c
View file

@ -37,15 +37,15 @@
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
* Infineon Technologies AG (Infineon) is supplying this software for use
* with Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
* SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR
* SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
****************************************************************************/
@ -130,7 +130,7 @@ static void delay(uint32_t cycles)
{
volatile uint32_t i;
for (i = 0; i < cycles ;++i)
for (i = 0; i < cycles; ++i)
{
__asm__ __volatile__ ("nop");
}
@ -177,6 +177,7 @@ void xmc4_clock_configure(void)
/* Automatic calibration uses the fSTDBY */
/* Enable HIB domain */
/* Power up HIB domain if and only if it is currently powered down */
regval = getreg32(XMC4_SCU_PWRSTAT);
@ -188,7 +189,7 @@ void xmc4_clock_configure(void)
/* Wait until HIB domain is enabled */
while((getreg32(XMC4_SCU_PWRSTAT) & SCU_PWR_HIBEN) == 0)
while ((getreg32(XMC4_SCU_PWRSTAT) & SCU_PWR_HIBEN) == 0)
{
}
}
@ -235,8 +236,8 @@ void xmc4_clock_configure(void)
do
{
/* Check SCU_MIRRSTS to ensure that no transfer over serial interface
* is pending.
/* Check SCU_MIRRSTS to ensure that no transfer over serial
* interface is pending.
*/
while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCLR) != 0)
@ -292,7 +293,8 @@ void xmc4_clock_configure(void)
{
regval = getreg32(XMC4_SCU_OSCHPCTRL);
regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK);
regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT;
regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) <<
SCU_OSCHPCTRL_OSCVAL_SHIFT;
putreg32(regval, XMC4_SCU_OSCHPCTRL);
/* Select OSC_HP clock as PLL input */
@ -309,7 +311,8 @@ void xmc4_clock_configure(void)
/* Wait till OSC_HP output frequency is usable */
while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE)
while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) !=
SCU_PLLSTAT_OSC_USABLE)
{
}
@ -361,7 +364,7 @@ void xmc4_clock_configure(void)
regval |= SCU_PLLCON0_RESLD;
putreg32(regval, XMC4_SCU_PLLCON0);
/* wait for PLL Lock at 24MHz*/
/* wait for PLL Lock at 24MHz */
while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_VCOLOCK) == 0)
{
@ -428,7 +431,8 @@ void xmc4_clock_configure(void)
putreg32(regval, XMC4_SCU_EXTCLKCR);
#if BOARD_ENABLE_PLL
/* PLL frequency stepping...*/
/* PLL frequency stepping... */
/* Reset OSCDISCDIS */
regval = getreg32(XMC4_SCU_PLLCON0);
@ -482,6 +486,7 @@ void xmc4_clock_configure(void)
getreg32(regval, XMC4_SCU_USBPLLCON);
/* USB PLL uses as clock input the OSC_HP */
/* check and if not already running enable OSC_HP */
if ((getreg32(XMC4_SCU_OSCHPCTRL) & SCU_OSCHPCTRL_MODE_MASK) != 0U)
@ -500,7 +505,8 @@ void xmc4_clock_configure(void)
regval = getreg32(XMC4_SCU_OSCHPCTRL);
regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK);
regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT;
regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) <<
SCU_OSCHPCTRL_OSCVAL_SHIFT;
putreg32(regval, XMC4_SCU_OSCHPCTRL);
/* Restart OSC Watchdog */
@ -511,12 +517,14 @@ void xmc4_clock_configure(void)
/* Wait till OSC_HP output frequency is usable */
while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE)
while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) !=
SCU_PLLSTAT_OSC_USABLE)
{
}
}
/* Setup USB PLL */
/* Go to bypass the USB PLL */
regval = getreg32(XMC4_SCU_USBPLLCON);
@ -530,7 +538,8 @@ void xmc4_clock_configure(void)
/* Setup Divider settings for USB PLL */
regval = (SCU_USBPLLCON_NDIV(BOARD_USB_NDIV) | SCU_USBPLLCON_PDIV(BOARD_USB_PDIV));
regval = (SCU_USBPLLCON_NDIV(BOARD_USB_NDIV) |
SCU_USBPLLCON_PDIV(BOARD_USB_PDIV));
putreg32(regval, XMC4_SCU_USBPLLCON);
/* Set OSCDISCDIS */
@ -570,7 +579,8 @@ void xmc4_clock_configure(void)
#if BOARD_EXTCKL_ENABLE
#if BOARD_EXTCLK_PIN == EXTCLK_PIN_P0_8
/* enable EXTCLK output on P0.8 */
/* Enable EXTCLK output on P0.8 */
regval = getreg32(XMC4_PORT0_HWSEL);
regval &= ~PORT_HWSEL_HW8_MASK;
putreg32(regval, XMC4_PORT0_HWSEL);
@ -584,7 +594,8 @@ void xmc4_clock_configure(void)
regval |= PORT_IOCR8_PC8(0x11); /* push-pull output, alt func 1 */
putreg32(regval, XMC4_PORT0_IOCR8);
#else
/* enable EXTCLK output on P1.15 */
/* Enable EXTCLK output on P1.15 */
# warn "Not yet implemented"
#endif
#endif

40
arch/xtensa/src/esp32/esp32_serial.c
View file

@ -620,14 +620,15 @@ static void esp32_shutdown(struct uart_dev_s *dev)
* Name: esp32_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
* Configure the UART to operation in interrupt driven mode. This method
* is called when the serial port is opened. Normally, this is just after
* the the setup() method is called, however, the serial console may
* operate in a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
* RX and TX interrupts are not enabled when by the attach method (unless
* the hardware supports multiple levels of interrupt enabling). The RX
* and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
*
****************************************************************************/
@ -680,8 +681,8 @@ static int esp32_attach(struct uart_dev_s *dev)
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception
* is the serial console which is never shutdown.
* closed normally just before the shutdown method is called. The
* exception is the serial console which is never shutdown.
*
****************************************************************************/
@ -760,7 +761,8 @@ static int esp32_interrupt(int cpuint, void *context, FAR void *arg)
* data, possibly resulting in an overrun error.
*/
if ((enabled & (UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA)) != 0)
if ((enabled & (UART_RXFIFO_FULL_INT_ENA |
UART_RXFIFO_TOUT_INT_ENA)) != 0)
{
/* Is there any data waiting in the Rx FIFO? */
@ -774,8 +776,8 @@ static int esp32_interrupt(int cpuint, void *context, FAR void *arg)
}
}
/* Are Tx interrupts enabled? The upper layer will disable Tx interrupts
* when it has nothing to send.
/* Are Tx interrupts enabled? The upper layer will disable Tx
* interrupts when it has nothing to send.
*/
if ((enabled & (UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA)) != 0)
@ -1016,7 +1018,8 @@ static int esp32_receive(struct uart_dev_s *dev, unsigned int *status)
/* Then return the actual received byte */
return (int)(esp32_serialin(priv, UART_FIFO_OFFSET) & UART_RXFIFO_RD_BYTE_M);
return (int)(esp32_serialin(priv, UART_FIFO_OFFSET) &
UART_RXFIFO_RD_BYTE_M);
}
/****************************************************************************
@ -1037,8 +1040,8 @@ static void esp32_rxint(struct uart_dev_s *dev, bool enable)
if (enable)
{
/* Receive an interrupt when their is anything in the Rx data register (or an Rx
* timeout occurs).
/* Receive an interrupt when their is anything in the Rx data register
* (or an Rx timeout occurs).
*/
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
@ -1149,7 +1152,8 @@ static bool esp32_txready(struct uart_dev_s *dev)
{
struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv;
return ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_TXFIFO_CNT_M) < 0x7f);
return ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_TXFIFO_CNT_M) <
0x7f);
}
/****************************************************************************
@ -1256,11 +1260,11 @@ int up_putc(int ch)
{
/* Add CR */
while(!esp32_txready(&CONSOLE_DEV));
while (!esp32_txready(&CONSOLE_DEV));
esp32_send(&CONSOLE_DEV, '\r');
}
while(!esp32_txready(&CONSOLE_DEV));
while (!esp32_txready(&CONSOLE_DEV));
esp32_send(&CONSOLE_DEV, ch);
esp32_restoreuartint(CONSOLE_DEV.priv, intena);

6
arch/xtensa/src/esp32/esp32_start.c
View file

@ -98,8 +98,8 @@ void IRAM_ATTR __start(void)
register uint32_t *ptr;
register int i;
/* If stack debug is enabled, then fill the stack with a recognizable value
* that we can use later to test for high water marks.
/* If stack debug is enabled, then fill the stack with a recognizable
* value that we can use later to test for high water marks.
*/
for (i = 0, ptr = g_idlestack; i < IDLETHREAD_STACKWORDS; i++)
@ -153,5 +153,5 @@ void IRAM_ATTR __start(void)
/* Bring up NuttX */
nx_start();
for(; ; ); /* Should not return */
for (; ; ); /* Should not return */
}

5
audio/audio_comp.c
View file

@ -960,12 +960,13 @@ int audio_comp_initialize(FAR const char *name, ...)
priv->export.ops = &g_audio_comp_ops;
while(va_arg(ap, FAR struct audio_lowerhalf_s *))
while (va_arg(ap, FAR struct audio_lowerhalf_s *))
{
priv->count++;
}
priv->lower = kmm_calloc(priv->count, sizeof(FAR struct audio_lowerhalf_s *));
priv->lower = kmm_calloc(priv->count,
sizeof(FAR struct audio_lowerhalf_s *));
if (priv->lower == NULL)
{
goto free_priv;

18
configs/nucleo-f302r8/src/stm32_highpri.c
View file

@ -68,6 +68,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
@ -242,7 +243,8 @@ void adc12_handler(void)
/* Do some floating point operations */
g_highpri.r_volt[g_highpri.current] = (float)g_highpri.r_val[g_highpri.current] * ref / bit;
g_highpri.r_volt[g_highpri.current] =
(float)g_highpri.r_val[g_highpri.current] * ref / bit;
if (g_highpri.current >= REG_NCHANNELS-1)
{
@ -424,7 +426,8 @@ int highpri_main(int argc, char *argv[])
ret = up_ramvec_attach(STM32_IRQ_ADC12, adc12_handler);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -434,7 +437,8 @@ int highpri_main(int argc, char *argv[])
ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -448,7 +452,8 @@ int highpri_main(int argc, char *argv[])
ret = up_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -458,7 +463,8 @@ int highpri_main(int argc, char *argv[])
ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -492,7 +498,7 @@ int highpri_main(int argc, char *argv[])
PWM_TIM_ENABLE(pwm1, true);
#endif
while(1)
while (1)
{
#ifndef CONFIG_STM32_ADC1_DMA
/* Software trigger for regular sequence */

18
configs/nucleo-f334r8/src/stm32_highpri.c
View file

@ -69,6 +69,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
@ -257,7 +258,8 @@ void adc12_handler(void)
/* Do some floating point operations */
g_highpri.r_volt[g_highpri.current] = (float)g_highpri.r_val[g_highpri.current] * ref / bit;
g_highpri.r_volt[g_highpri.current] =
(float)g_highpri.r_val[g_highpri.current] * ref / bit;
if (g_highpri.current >= REG_NCHANNELS-1)
{
@ -460,7 +462,8 @@ int highpri_main(int argc, char *argv[])
ret = up_ramvec_attach(STM32_IRQ_ADC12, adc12_handler);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -470,7 +473,8 @@ int highpri_main(int argc, char *argv[])
ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -484,7 +488,8 @@ int highpri_main(int argc, char *argv[])
ret = up_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -494,7 +499,8 @@ int highpri_main(int argc, char *argv[])
ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -534,7 +540,7 @@ int highpri_main(int argc, char *argv[])
PWM_TIM_ENABLE(pwm1, true);
#endif
while(1)
while (1)
{
#ifndef CONFIG_STM32_ADC1_DMA
/* Software trigger for regular sequence */

276
configs/nucleo-f334r8/src/stm32_spwm.c
View file

@ -64,6 +64,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Asserions ****************************************************************/
#ifndef CONFIG_ARCH_CHIP_STM32F334R8
@ -92,42 +93,42 @@
/* Phase 1 is TIM1 CH1 */
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 0
# ifndef CONFIG_STM32_TIM1_CH1OUT
# error
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 0
# ifndef CONFIG_STM32_TIM1_CH1OUT
# error
# endif
# ifndef CONFIG_STM32_TIM6
# error
# endif
# endif
# ifndef CONFIG_STM32_TIM6
# error
# endif
#endif
/* Phase 2 is TIM1 CH2 */
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 1
# ifndef CONFIG_STM32_TIM1_CH2OUT
# error
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 1
# ifndef CONFIG_STM32_TIM1_CH2OUT
# error
# endif
# endif
#endif
/* Phase 3 is TIM1 CH3 */
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 2
# ifndef CONFIG_STM32_TIM1_CH3OUT
# error
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 2
# ifndef CONFIG_STM32_TIM1_CH3OUT
# error
# endif
# endif
#endif
/* Phase 4 is TIM1 CH4 */
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 3
# ifndef CONFIG_STM32_TIM1_CH4OUT
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 3
# ifndef CONFIG_STM32_TIM1_CH4OUT
# error
# endif
# endif
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM != PWM_TIM1_NCHANNELS
# error
# endif
#endif
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM != PWM_TIM1_NCHANNELS
# error
#endif
#endif /* CONFIG_NUCLEOF334R8_SPWM_USE_TIM1 */
@ -137,57 +138,57 @@
/* Phase 1 is TIMA */
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 0
# ifndef CONFIG_STM32_HRTIM_TIMA
# error
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 0
# ifndef CONFIG_STM32_HRTIM_TIMA
# error
# endif
# ifndef CONFIG_STM32_HRTIM_MASTER
# error
# endif
# endif
# ifndef CONFIG_STM32_HRTIM_MASTER
# error
# endif
#endif
/* Phase 2 is TIMB */
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 1
# ifndef CONFIG_STM32_HRTIM_TIMB
# error
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 1
# ifndef CONFIG_STM32_HRTIM_TIMB
# error
# endif
# endif
#endif
/* Phase 3 is TIMC */
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 2
# ifndef CONFIG_STM32_HRTIM_TIMC
# error
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 2
# ifndef CONFIG_STM32_HRTIM_TIMC
# error
# endif
# endif
#endif
/* Phase 4 is TIMD */
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 3
# ifndef CONFIG_STM32_HRTIM_TIMD
# error
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 3
# ifndef CONFIG_STM32_HRTIM_TIMD
# error
# endif
# endif
#endif
/* Phase 5 is TIME */
#if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 4
# ifndef CONFIG_STM32_HRTIM_TIME
# error
# if CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM > 4
# ifndef CONFIG_STM32_HRTIM_TIME
# error
# endif
# endif
#endif
#endif /* CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1 */
/* Configuration ************************************************************/
#ifdef CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1
#define PWM_TIMERS_IN_USE CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM
# define PWM_TIMERS_IN_USE CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM
#endif
#ifdef CONFIG_NUCLEOF334R8_SPWM_USE_TIM1
#define PWM_TIMERS_IN_USE 1
# define PWM_TIMERS_IN_USE 1
#endif
#define SPWM_PHASE_SHIFT ((360.0f/CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM))
@ -211,19 +212,20 @@
struct spwm_s
{
FAR struct pwm_timer_s *pwm;
FAR struct pwm_timer_s *pwm;
#ifdef CONFIG_NUCLEOF334R8_SPWM_USE_TIM1
FAR struct stm32_tim_dev_s *tim;
#endif
float waveform[SAMPLES_NUM]; /* Waveform samples */
float phase_step; /* Waveform phase step */
float waveform_freq; /* Waveform frequency */
uint16_t cmp[SAMPLES_NUM]; /* PWM TIM compare table */
uint16_t per; /* PWM TIM period */
uint16_t samples; /* Modulation waveform samples num */
uint16_t phase_shift[PHASES_NUM]; /* Phase offset */
volatile uint16_t sample_now[PHASES_NUM]; /* Current sumple number for phase */
uint8_t phases; /* Number of PWM phases */
float waveform[SAMPLES_NUM]; /* Waveform samples */
float phase_step; /* Waveform phase step */
float waveform_freq; /* Waveform frequency */
uint16_t cmp[SAMPLES_NUM]; /* PWM TIM compare table */
uint16_t per; /* PWM TIM period */
uint16_t samples; /* Modulation waveform samples num */
uint16_t phase_shift[PHASES_NUM]; /* Phase offset */
volatile uint16_t sample_now[PHASES_NUM]; /* Current sample number for
* phase */
uint8_t phases; /* Number of PWM phases */
};
/****************************************************************************
@ -233,8 +235,8 @@ struct spwm_s
static struct spwm_s g_spwm =
{
.waveform_freq = ((float)CONFIG_NUCLEOF334R8_SPWM_FREQ),
.phases = PHASES_NUM,
.samples = SAMPLES_NUM,
.phases = PHASES_NUM,
.samples = SAMPLES_NUM,
};
/****************************************************************************
@ -278,11 +280,11 @@ static int spwm_setup(FAR struct spwm_s *spwm);
static float waveform_func(float x)
{
DEBUGASSERT(x >= 0 && x <= 2*M_PI);
DEBUGASSERT(x >= 0 && x <= 2 * M_PI);
/* Sine modulation */
return (sinf(x)+1.0f)/2.0f;
return (sinf(x) + 1.0f) / 2.0f;
}
/****************************************************************************
@ -295,35 +297,34 @@ static float waveform_func(float x)
static int waveform_init(FAR struct spwm_s *spwm, float (*f)(float))
{
uint16_t i = 0;
int ret = 0;
uint16_t i = 0;
int ret = 0;
printf("Initialize waveform\n");
/* Get phase step to acheive one sine waveform period */
spwm->phase_step = (float)(2*M_PI/spwm->samples);
spwm->phase_step = (float)(2 * M_PI / spwm->samples);
/* Initialize sine and PWM compare tables */
for (i = 0; i< spwm->samples; i += 1)
for (i = 0; i < spwm->samples; i += 1)
{
/* We need sine in range from 0 to 1.0 */
spwm->waveform[i] = f(spwm->phase_step*i);
spwm->waveform[i] = f(spwm->phase_step * i);
DEBUGASSERT(spwm->waveform[i] >= 0.0 && spwm->waveform[i] <= 2*M_PI);
DEBUGASSERT(spwm->waveform[i] >= 0.0 && spwm->waveform[i] <= 2 * M_PI);
spwm->cmp[i] = (uint16_t)(spwm->waveform[i] * spwm->per);
}
/* Configure phase shift
* TODO: this should be configurable
*/
/* Configure phase shift TODO: this should be configurable */
for (i = 0; i < spwm->phases; i += 1)
{
spwm->phase_shift[i] = (spwm->samples / CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM) * i;
spwm->phase_shift[i] =
(spwm->samples / CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM) * i;
}
/* Initialize offstes */
@ -360,7 +361,7 @@ static int spwm_start(FAR struct spwm_s *spwm)
spwm_hrtim_start(spwm);
#elif defined(CONFIG_NUCLEOF334R8_SPWM_USE_TIM1)
/* Start TIM1 */
/* Start TIM1 */
spwm_tim1_start(spwm);
@ -413,15 +414,14 @@ static int spwm_stop(FAR struct spwm_s *spwm)
static int master_configure(FAR struct spwm_s *spwm)
{
FAR struct hrtim_dev_s *hrtim = spwm->pwm;
uint64_t per = 0;
uint64_t per = 0;
uint64_t fclk = 0;
uint64_t freq = 0;
uint16_t cmp = 0;
int ret = 0;
uint16_t cmp = 0;
int ret = 0;
/* Frequency with which we will change samples.
*
* master_freq = samples_num * waveform_freq
/* Frequency with which we will change samples. master_freq = samples_num *
* waveform_freq.
*/
freq = spwm->samples * spwm->waveform_freq;
@ -429,7 +429,7 @@ static int master_configure(FAR struct spwm_s *spwm)
/* Configure Master Timer period */
fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_MASTER);
per = fclk/freq;
per = fclk / freq;
if (per > HRTIM_PER_MAX)
{
printf("ERROR: can not achieve master freq=%llu if fclk=%llu\n",
@ -456,16 +456,16 @@ errout:
static int slaves_configure(FAR struct spwm_s *spwm)
{
FAR struct hrtim_dev_s *hrtim = spwm->pwm;
uint64_t fclk = 0;
uint64_t per = 0;
uint8_t index = 0;
uint8_t i = 0;
int ret = 0;
uint64_t fclk = 0;
uint64_t per = 0;
uint8_t index = 0;
uint8_t i = 0;
int ret = 0;
/* Get timer period value for given frequency */
fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMA);
per = fclk/CONFIG_NUCLEOF334R8_SPWM_PWM_FREQ;
per = fclk / CONFIG_NUCLEOF334R8_SPWM_PWM_FREQ;
if (per > HRTIM_PER_MAX)
{
printf("ERROR: can not achieve pwm freq=%llu if fclk=%llu\n",
@ -476,17 +476,18 @@ static int slaves_configure(FAR struct spwm_s *spwm)
spwm->per = (uint16_t)per;
for(i = 0; i < spwm->phases; i+=1)
for (i = 0; i < spwm->phases; i += 1)
{
/* Get slave timer index */
index = (1<<(i+1));
index = (1 << (i + 1));
/* Prescalers for slave timers must be the same !!! */
if (fclk != HRTIM_FCLK_GET(hrtim, index))
{
printf("ERROR: prescaler for HRTIM TIMER %d doesn't match!\n", index);
printf("ERROR: prescaler for HRTIM TIMER %d doesn't match!\n",
index);
ret = -EINVAL;
goto errout;
}
@ -506,10 +507,10 @@ errout:
static void hrtim_master_handler(void)
{
FAR struct spwm_s *spwm = &g_spwm;
FAR struct spwm_s *spwm = &g_spwm;
FAR struct hrtim_dev_s *hrtim = spwm->pwm;
uint32_t pending = 0;
uint8_t i = 0;
uint8_t i = 0;
pending = HRTIM_IRQ_GET(hrtim, HRTIM_TIMER_MASTER);
@ -517,14 +518,13 @@ static void hrtim_master_handler(void)
{
/* Update CMP for slaves */
for(i = 0; i < spwm->phases; i += 1)
for (i = 0; i < spwm->phases; i += 1)
{
/* Set new CMP for timers */
HRTIM_CMP_SET(hrtim, (1<<(i+1)), HRTIM_CMP1,
HRTIM_CMP_SET(hrtim, (1 << (i + 1)), HRTIM_CMP1,
spwm->cmp[spwm->sample_now[i]]);
/* Increase sample pointer */
spwm->sample_now[i] += 1;
@ -537,9 +537,9 @@ static void hrtim_master_handler(void)
/* Software update all slaves */
for(i = 0; i < spwm->phases; i += 1)
for (i = 0; i < spwm->phases; i += 1)
{
HRTIM_SOFT_UPDATE(hrtim, 1<<(i+1));
HRTIM_SOFT_UPDATE(hrtim, 1 << (i + 1));
}
}
@ -552,7 +552,7 @@ static void hrtim_master_handler(void)
static int spwm_hrtim_setup(FAR struct spwm_s *spwm)
{
FAR struct hrtim_dev_s *pwm = NULL;
FAR struct hrtim_dev_s *pwm = NULL;
int ret = OK;
/* Configure HRTIM */
@ -572,7 +572,8 @@ static int spwm_hrtim_setup(FAR struct spwm_s *spwm)
ret = up_ramvec_attach(STM32_IRQ_HRTIMTM, hrtim_master_handler);
if (ret < 0)
{
fprintf(stderr, "spwm_main: ERROR: up_ramvec_attach failed: %d\n", ret);
fprintf(stderr, "spwm_main: ERROR: up_ramvec_attach failed: %d\n",
ret);
ret = -1;
goto errout;
}
@ -582,7 +583,8 @@ static int spwm_hrtim_setup(FAR struct spwm_s *spwm)
ret = up_prioritize_irq(STM32_IRQ_HRTIMTM, NVIC_SYSH_HIGH_PRIORITY);
if (ret < 0)
{
fprintf(stderr, "spwm_main: ERROR: up_prioritize_irq failed: %d\n", ret);
fprintf(stderr, "spwm_main: ERROR: up_prioritize_irq failed: %d\n",
ret);
ret = -1;
goto errout;
}
@ -622,9 +624,9 @@ errout:
static int spwm_hrtim_start(FAR struct spwm_s *spwm)
{
FAR struct hrtim_dev_s *hrtim = spwm->pwm;
uint8_t timers = 0;
uint8_t timers = 0;
uint16_t outputs = 0;
int i = 0;
int i = 0;
/* Enable HRTIM Master interrupt */
@ -632,16 +634,16 @@ static int spwm_hrtim_start(FAR struct spwm_s *spwm)
/* Get HRTIM timers (master+slaves) */
for(i = 0; i < spwm->phases+1; i += 1)
for (i = 0; i < spwm->phases + 1; i += 1)
{
timers |= (1<<i);
timers |= (1 << i);
}
/* Get HRTIM outputs */
for(i = 0; i < spwm->phases; i += 1)
for (i = 0; i < spwm->phases; i += 1)
{
outputs |= (1<<(i*2));
outputs |= (1 << (i * 2));
}
/* Enable HRTIM outpus */
@ -662,9 +664,9 @@ static int spwm_hrtim_start(FAR struct spwm_s *spwm)
static int spwm_hrtim_stop(FAR struct spwm_s *spwm)
{
FAR struct hrtim_dev_s *hrtim = spwm->pwm;
uint8_t timers = 0;
uint8_t timers = 0;
uint16_t outputs = 0;
int i = 0;
int i = 0;
/* Disable HRTIM Master interrupt */
@ -672,16 +674,16 @@ static int spwm_hrtim_stop(FAR struct spwm_s *spwm)
/* Get HRTIM timers (master+slaves) */
for(i = 0; i < spwm->phases+1; i += 1)
for (i = 0; i < spwm->phases + 1; i += 1)
{
timers |= (1<<i);
timers |= (1 << i);
}
/* Get HRTIM outputs */
for(i = 0; i < spwm->phases; i += 1)
for (i = 0; i < spwm->phases; i += 1)
{
outputs |= (1<<(i*2));
outputs |= (1 << (i * 2));
}
/* Disable HRTIM outpus */
@ -705,16 +707,16 @@ static int spwm_hrtim_stop(FAR struct spwm_s *spwm)
static void tim6_handler(void)
{
FAR struct spwm_s *spwm = &g_spwm;
FAR struct spwm_s *spwm = &g_spwm;
FAR struct stm32_pwm_dev_s *pwm = spwm->pwm;
FAR struct stm32_tim_dev_s *tim = spwm->tim;
FAR struct stm32_tim_dev_s *tim = spwm->tim;
uint8_t i = 0;
for(i = 0; i < spwm->phases; i += 1)
for (i = 0; i < spwm->phases; i += 1)
{
/* Set new CMP for timers */
PWM_CCR_UPDATE(pwm, i+1, spwm->cmp[spwm->sample_now[i]]);
PWM_CCR_UPDATE(pwm, i + 1, spwm->cmp[spwm->sample_now[i]]);
/* Increase sample pointer */
@ -737,10 +739,10 @@ static void tim6_handler(void)
static int spwm_tim6_setup(FAR struct spwm_s *spwm)
{
FAR struct stm32_tim_dev_s *tim = NULL;
FAR struct stm32_tim_dev_s *tim = NULL;
uint64_t freq = 0;
uint32_t per = 0;
int ret = OK;
uint32_t per = 0;
int ret = OK;
/* Get TIM6 interface */
@ -756,11 +758,11 @@ static int spwm_tim6_setup(FAR struct spwm_s *spwm)
/* Frequency with which we will change samples.
*
* tim6_freq = samples_num * waveform_freq
* tim6_freq = samples_num * waveform_freq.
*/
freq = spwm->samples * spwm->waveform_freq;
per = BOARD_TIM6_FREQUENCY/freq;
per = BOARD_TIM6_FREQUENCY / freq;
if (per > 0xFFFF)
{
printf("ERROR: can not achieve TIM6 frequency\n");
@ -805,7 +807,7 @@ errout:
static int spwm_tim6_start(FAR struct spwm_s *spwm)
{
FAR struct stm32_tim_dev_s *tim = spwm->tim;
FAR struct stm32_tim_dev_s *tim = spwm->tim;
/* Enable the timer interrupt at the NVIC and at TIM6 */
@ -821,7 +823,7 @@ static int spwm_tim6_start(FAR struct spwm_s *spwm)
static int spwm_tim6_stop(FAR struct spwm_s *spwm)
{
FAR struct stm32_tim_dev_s *tim = spwm->tim;
FAR struct stm32_tim_dev_s *tim = spwm->tim;
/* Disable the timer interrupt at the NVIC and at TIM6 */
@ -837,7 +839,7 @@ static int spwm_tim6_stop(FAR struct spwm_s *spwm)
static int spwm_tim1_setup(FAR struct spwm_s *spwm)
{
FAR struct stm32_pwm_dev_s *pwm = NULL;
FAR struct stm32_pwm_dev_s *pwm = NULL;
int ret = OK;
/* Get TIM1 PWM interface */
@ -888,15 +890,15 @@ errout:
static int spwm_tim1_start(FAR struct spwm_s *spwm)
{
FAR struct stm32_pwm_dev_s *pwm = spwm->pwm;
FAR struct stm32_pwm_dev_s *pwm = spwm->pwm;
uint16_t outputs = 0;
int i = 0;
int i = 0;
/* Get outputs */
for(i = 0; i < spwm->phases; i+=1)
for (i = 0; i < spwm->phases; i += 1)
{
outputs |= (1<<(i*2));
outputs |= (1 << (i * 2));
}
/* Enable PWM outputs */
@ -916,15 +918,15 @@ static int spwm_tim1_start(FAR struct spwm_s *spwm)
static int spwm_tim1_stop(FAR struct spwm_s *spwm)
{
FAR struct stm32_pwm_dev_s *pwm = spwm->pwm;
FAR struct stm32_pwm_dev_s *pwm = spwm->pwm;
uint16_t outputs = 0;
int i = 0;
int i = 0;
/* Get outputs */
for(i = 0; i < spwm->phases; i+=1)
for (i = 0; i < spwm->phases; i += 1)
{
outputs |= (1<<(i*2));
outputs |= (1 << (i * 2));
}
/* Disable PWM outputs */
@ -996,9 +998,9 @@ errout:
int spwm_main(int argc, char *argv[])
{
FAR struct spwm_s *spwm = NULL;
FAR struct spwm_s *spwm = NULL;
int ret = OK;
int i = 0;
int i = 0;
spwm = &g_spwm;
@ -1008,10 +1010,10 @@ int spwm_main(int argc, char *argv[])
ret = spwm_setup(spwm);
if (ret < 0)
{
printf("ERROR: failed to setup SPWM %d!\n", ret);
goto errout;
}
{
printf("ERROR: failed to setup SPWM %d!\n", ret);
goto errout;
}
/* Initialize modulation waveform */
@ -1054,4 +1056,4 @@ errout:
return 0;
}
#endif /* CONFIG_NUCLEOF334R8_SPWM */
#endif /* CONFIG_NUCLEOF334R8_SPWM */

20
configs/olimex-stm32-h405/src/stm32_autoleds.c
View file

@ -72,11 +72,15 @@ void board_autoled_initialize(void)
void board_autoled_on(int led)
{
if(led == LED_STARTED)
stm32_gpiowrite(GPIO_LED_STATUS, true);
if (led == LED_STARTED)
{
stm32_gpiowrite(GPIO_LED_STATUS, true);
}
if(led == LED_ASSERTION || led == LED_PANIC)
if (led == LED_ASSERTION || led == LED_PANIC)
{
stm32_gpiowrite(GPIO_LED_STATUS, false);
}
}
/****************************************************************************
@ -85,11 +89,15 @@ void board_autoled_on(int led)
void board_autoled_off(int led)
{
if(led == LED_STARTED)
if (led == LED_STARTED)
{
stm32_gpiowrite(GPIO_LED_STATUS, false);
}
if(led == LED_ASSERTION || led == LED_PANIC)
stm32_gpiowrite(GPIO_LED_STATUS, true);
if (led == LED_ASSERTION || led == LED_PANIC)
{
stm32_gpiowrite(GPIO_LED_STATUS, true);
}
}
#endif /* CONFIG_ARCH_LEDS */

14
configs/photon/src/stm32_wdt.c
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* configs/photon/src/stm32_wdt.c
*
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
@ -31,11 +31,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
@ -55,9 +55,9 @@
#include <nuttx/kthread.h>
#include <nuttx/clock.h>
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
/* Watchdog daemon thread */
@ -86,7 +86,7 @@ static int wdog_daemon(int argc, char *argv[])
goto exit_close_dev;
}
while(1)
while (1)
{
nxsig_usleep((CONFIG_PHOTON_WDG_THREAD_INTERVAL)*1000);

22
configs/sam4s-xplained-pro/src/sam_wdt.c
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* configs/sam4s-xplained-pro/src/up_wdt.c
*
* Copyright (C) 2014, 2016-2018 Gregory Nutt. All rights reserved.
@ -32,11 +32,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
@ -60,10 +60,12 @@
#ifdef CONFIG_WATCHDOG
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration *******************************************************************/
****************************************************************************/
/* Configuration ************************************************************/
/* Watchdog hardware should be enabled */
#if !defined(CONFIG_SAM34_WDT)
@ -84,9 +86,9 @@
# error "WDT_THREAD_INTERVAL must be greater than or equal to WDT_MINTIME"
#endif
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
/* Watchdog kicker task */
@ -117,7 +119,7 @@ static int wdog_daemon(int argc, char *argv[])
}
nxsig_usleep(200);
while(1)
while (1)
{
nxsig_usleep((CONFIG_WDT_THREAD_INTERVAL)*1000);

13
configs/sama5d4-ek/src/dram_main.c
View file

@ -131,7 +131,7 @@ int dram_main(int argc, char *argv)
printf("ERROR: Intel HEX file load failed: %d\n", ret);
fflush(stdout);
for(;;);
for (; ; );
}
/* No success indication.. The following cache/MMU operations will clobber
@ -144,12 +144,13 @@ int dram_main(int argc, char *argv)
*/
arch_clean_dcache((uintptr_t)SAM_DDRCS_VSECTION,
(uintptr_t)(SAM_DDRCS_VSECTION + CONFIG_SAMA5_DDRCS_SIZE));
(uintptr_t)(SAM_DDRCS_VSECTION +
CONFIG_SAMA5_DDRCS_SIZE));
/* Interrupts must be disabled through the following. In this configuration,
* there should only be timer interrupts. Your NuttX configuration must use
* CONFIG_SERIAL_LOWCONSOLE=y or printf() will hang when the interrupts
* are disabled!
/* Interrupts must be disabled through the following. In this
* configuration, there should only be timer interrupts. Your NuttX
* configuration must use CONFIG_SERIAL_LOWCONSOLE=y or printf() will
* hang when the interrupts are disabled!
*/
(void)up_irq_save();

2
configs/samv71-xult/src/sam_appinit.c
View file

@ -92,7 +92,7 @@ int board_app_initialize(uintptr_t arg)
#ifdef CONFIG_BOARDCTL_IOCTL
int board_ioctl(unsigned int cmd, uintptr_t arg)
{
switch(cmd)
switch (cmd)
{
default:
return -ENOTTY; /* Standard return for command not supported */

5
configs/stm32_tiny/src/stm32_spi.c
View file

@ -77,6 +77,7 @@ void stm32_spidev_initialize(void)
#ifdef CONFIG_STM32_SPI2
# ifdef CONFIG_WL_NRF24L01
/* Configure the SPI-based NRF24L01 chip select GPIO */
spiinfo("Configure GPIO for SPI2/CS\n");
stm32_configgpio(GPIO_NRF24L01_CS);
# endif
@ -122,7 +123,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
{
switch(devid)
switch (devid)
{
#ifdef CONFIG_WL_NRF24L01
case SPIDEV_WIRELESS(0):
@ -141,7 +142,7 @@ void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
{
uint8_t status = 0;
switch(devid)
switch (devid)
{
#ifdef CONFIG_WL_NRF24L01
case SPIDEV_WIRELESS(0):

18
configs/stm32f429i-disco/src/stm32_highpri.c
View file

@ -66,6 +66,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
@ -226,7 +227,8 @@ void adc_handler(void)
/* Do some floating point operations */
g_highpri.r_volt[g_highpri.current] = (float)g_highpri.r_val[g_highpri.current] * ref / bit;
g_highpri.r_volt[g_highpri.current] =
(float)g_highpri.r_val[g_highpri.current] * ref / bit;
if (g_highpri.current >= REG_NCHANNELS-1)
{
@ -408,7 +410,8 @@ int highpri_main(int argc, char *argv[])
ret = up_ramvec_attach(STM32_IRQ_ADC, adc_handler);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -418,7 +421,8 @@ int highpri_main(int argc, char *argv[])
ret = up_prioritize_irq(STM32_IRQ_ADC, NVIC_SYSH_HIGH_PRIORITY);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -432,7 +436,8 @@ int highpri_main(int argc, char *argv[])
ret = up_ramvec_attach(STM32_IRQ_DMA2S0, dma2s0_handler);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -442,7 +447,8 @@ int highpri_main(int argc, char *argv[])
ret = up_prioritize_irq(STM32_IRQ_DMA2S0, NVIC_SYSH_HIGH_PRIORITY);
if (ret < 0)
{
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", ret);
fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n",
ret);
ret = EXIT_FAILURE;
goto errout;
}
@ -482,7 +488,7 @@ int highpri_main(int argc, char *argv[])
PWM_TIM_ENABLE(pwm1, true);
#endif
while(1)
while (1)
{
#ifndef CONFIG_STM32_ADC1_DMA
/* Software trigger for regular sequence */

28
configs/stm32l476vg-disco/src/stm32_appinit.c
View file

@ -208,7 +208,8 @@ FAR struct mtd_dev_s *mtd_temp;
/* Setup a partition of 256KiB for our file system. */
ret = MTD_IOCTL(g_mtd_fs, MTDIOC_GEOMETRY, (unsigned long)(uintptr_t)&geo);
ret = MTD_IOCTL(g_mtd_fs, MTDIOC_GEOMETRY,
(unsigned long)(uintptr_t)&geo);
if (ret < 0)
{
_err("ERROR: MTDIOC_GEOMETRY failed\n");
@ -291,8 +292,8 @@ FAR struct mtd_dev_s *mtd_temp;
#endif
#ifdef HAVE_USBHOST
/* Initialize USB host operation. stm32l4_usbhost_initialize() starts a thread
* will monitor for USB connection and disconnection events.
/* Initialize USB host operation. stm32l4_usbhost_initialize() starts a
* thread that will monitor for USB connection and disconnection events.
*/
ret = stm32l4_usbhost_initialize();
@ -321,24 +322,26 @@ FAR struct mtd_dev_s *mtd_temp;
#ifdef CONFIG_BOARDCTL_IOCTL
int board_ioctl(unsigned int cmd, uintptr_t arg)
{
switch(cmd)
switch (cmd)
{
#ifdef HAVE_N25QXXX
case BIOC_ENTER_MEMMAP:
{
struct qspi_meminfo_s meminfo;
/* Set up the meminfo like a regular memory transaction, many of the fields
* are not used, the others are to set up for the 'read' command that will
* automatically be issued by the controller as needed.
* 6 = CONFIG_N25QXXX_DUMMIES;
* 0xeb = N25QXXX_FAST_READ_QUADIO;
/* Set up the meminfo like a regular memory transaction, many of
* the fields are not used, the others are to set up for the
* 'read' command that will automatically be issued by the
* controller as needed.
*
* 6 = CONFIG_N25QXXX_DUMMIES;
* 0xeb = N25QXXX_FAST_READ_QUADIO;
*/
meminfo.flags = QSPIMEM_READ | QSPIMEM_QUADIO;
meminfo.addrlen = 3;
meminfo.dummies = 6; //CONFIG_N25QXXX_DUMMIES;
meminfo.cmd = 0xeb;//N25QXXX_FAST_READ_QUADIO;
meminfo.dummies = 6; /* CONFIG_N25QXXX_DUMMIES; */
meminfo.cmd = 0xeb; /* N25QXXX_FAST_READ_QUADIO; */
meminfo.addr = 0;
meminfo.buflen = 0;
meminfo.buffer = NULL;
@ -354,8 +357,7 @@ int board_ioctl(unsigned int cmd, uintptr_t arg)
#endif
default:
return -EINVAL;
break;
return -EINVAL;
}
return OK;

9
configs/stm32l4r9ai-disco/src/stm32_appinit.c
View file

@ -157,8 +157,8 @@ int board_app_initialize(uintptr_t arg)
#endif
#ifdef HAVE_USBHOST
/* Initialize USB host operation. stm32l4_usbhost_initialize() starts a thread
* will monitor for USB connection and disconnection events.
/* Initialize USB host operation. stm32l4_usbhost_initialize() starts a
* thread that will monitor for USB connection and disconnection events.
*/
ret = stm32l4_usbhost_initialize();
@ -199,11 +199,10 @@ int board_app_initialize(uintptr_t arg)
#ifdef CONFIG_BOARDCTL_IOCTL
int board_ioctl(unsigned int cmd, uintptr_t arg)
{
switch(cmd)
switch (cmd)
{
default:
return -EINVAL;
break;
return -EINVAL;
}
return OK;

225
configs/us7032evb1/shterm/shterm.c
View file

@ -124,6 +124,7 @@ static void flushconsole(void)
{
(void)fflush(g_logstream);
}
(void)fflush(stdout);
}
@ -153,10 +154,10 @@ static void sendfile(int fdtarg, char *filename, int verify)
{
char chin;
char chout;
int fdin;
int nbytes;
int ndots;
int ret;
int fdin;
int nbytes;
int ndots;
int ret;
/* Source the source file */
@ -176,12 +177,14 @@ static void sendfile(int fdtarg, char *filename, int verify)
{
printconsole("Loading file '%s':\n", filename);
}
flushconsole();
/* This loop processes each byte from the source file */
nbytes = 0;
ndots = 0;
while ((ret = readbyte(fdin, &chout)) == 1)
{
/* If verbose debug is OFF, then output dots at a low rate */
@ -192,11 +195,13 @@ static void sendfile(int fdtarg, char *filename, int verify)
{
nbytes = 0;
putconsole('.');
if (++ndots > 72)
{
putconsole('\n');
ndots = 0;
putconsole('\n');
ndots = 0;
}
flushconsole();
}
}
@ -220,8 +225,8 @@ static void sendfile(int fdtarg, char *filename, int verify)
writebyte(fdtarg, chout);
/* Get the response from the target. Loop until the target responds
* by either echoing the byte sent or by sending '>'
/* Get the response from the target. Loop until the target responds by
* either echoing the byte sent or by sending '>'
*/
do
@ -263,10 +268,11 @@ static void sendfile(int fdtarg, char *filename, int verify)
writebyte(fdtarg, '>');
do
{
ret = readbyte(fdtarg, &chin);
}
{
ret = readbyte(fdtarg, &chin);
}
while (ret == 1 && chin != ENQ);
close(fdin);
writebyte(fdtarg, ACK);
}
@ -278,10 +284,10 @@ static void sendfile(int fdtarg, char *filename, int verify)
static void receivefile(int fdtarg, char *filename)
{
char ch;
int fdout;
int nbytes;
int ndots;
int ret;
int fdout;
int nbytes;
int ndots;
int ret;
fdout = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0644);
if (fdout < 0)
@ -326,10 +332,11 @@ static void receivefile(int fdtarg, char *filename)
putconsole('.');
if (++ndots > 72)
{
putconsole('\n');
ndots = 0;
putconsole('\n');
ndots = 0;
}
flushconsole();
flushconsole();
}
ret = readbyte(fdtarg, &ch);
@ -339,7 +346,7 @@ static void receivefile(int fdtarg, char *filename)
}
}
close (fdout);
close(fdout);
}
/****************************************************************************
@ -364,8 +371,9 @@ static void getfilename(int fd, char *name)
while (ret == 1 && ch > ' ')
{
*name++ = ch;
ret = readbyte(fd, &ch);
ret = readbyte(fd, &ch);
}
*name++ = 0;
}
@ -384,18 +392,22 @@ static int readbyte(int fd, char *ch)
{
if (errno != EAGAIN)
{
printconsole("ERROR: Failed to read from fd=%d: %s\n", fd, strerror(errno));
printconsole("ERROR: Failed to read from fd=%d: %s\n", fd,
strerror(errno));
close_tty();
exit(12);
}
return -EAGAIN;
}
else if (ret > 1)
{
printconsole("ERROR: Unexpected number of bytes read(%d) from fd=%d\n", ret, fd);
printconsole("ERROR: Unexpected number of bytes read(%d) from fd=%d\n",
ret, fd);
close_tty();
exit(13);
}
return ret;
}
@ -408,7 +420,8 @@ static void writebyte(int fd, char byte)
int ret = write(fd, &byte, 1);
if (ret < 0)
{
printconsole("ERROR: Failed to write to fd=%d: %s\n", fd, strerror(errno));
printconsole("ERROR: Failed to write to fd=%d: %s\n", fd,
strerror(errno));
close_tty();
exit(14);
}
@ -432,8 +445,10 @@ static void close_tty(void)
ret = tcsetattr(g_fd, TCSANOW, &g_termios);
if (ret < 0)
{
printconsole("ERROR: Failed to restore termios for %s: %s\n", g_ttydev, strerror(errno));
printconsole("ERROR: Failed to restore termios for %s: %s\n",
g_ttydev, strerror(errno));
}
(void)close(g_fd);
}
@ -460,11 +475,14 @@ static void interrupt(int signo)
static void show_usage(const char *progname, int exitcode)
{
fprintf(stderr, "\nUSAGE: %s [-h] [-d] [-t <ttyname>] [-b <baud>] [-l <log-file>]\n", progname);
fprintf(stderr,
"\nUSAGE: %s [-h] [-d] [-t <ttyname>] [-b <baud>] [-l <log-file>]\n",
progname);
fprintf(stderr, "\nWhere:\n");
fprintf(stderr, "\t-h: Prints this message then exit.\n");
fprintf(stderr, "\t-d: Enable debug output (twice for verbose output).\n");
fprintf(stderr, "\t-t <ttyname>: Use <ttyname> device instead of %s.\n", g_dfttydev);
fprintf(stderr, "\t-t <ttyname>: Use <ttyname> device instead of %s.\n",
g_dfttydev);
fprintf(stderr, "\t-b <baud>: Use <baud> instead of %d.\n", DEFAULT_BAUD);
fprintf(stderr, "\t-l <log-file>: Echo console output in <log-file>.\n");
exit(exitcode);
@ -479,14 +497,14 @@ int main(int argc, char **argv, char **envp)
struct termios tty;
char filename[MAX_FILEPATH];
char ch;
int speed;
int opt;
int oflags;
int ret;
int speed;
int opt;
int oflags;
int ret;
while ((opt = getopt(argc, argv, ":dt:b:hl:")) != -1)
{
switch(opt)
switch (opt)
{
case 'd':
debug++;
@ -528,25 +546,81 @@ int main(int argc, char **argv, char **envp)
switch (g_baud)
{
case 0: speed = B0; break;
case 50: speed = B50; break;
case 75: speed = B75; break;
case 110: speed = B110; break;
case 134: speed = B134; break;
case 150: speed = B150; break;
case 200: speed = B200; break;
case 300: speed = B300; break;
case 600: speed = B600; break;
case 1200: speed = B1200; break;
case 1800: speed = B1800; break;
case 2400: speed = B2400; break;
case 4800: speed = B4800; break;
case 9600: speed = B9600; break;
case 19200: speed = B19200; break;
case 38400: speed = B38400; break;
case 57600: speed = B57600; break;
case 115200: speed = B115200; break;
case 230400: speed = B230400; break;
case 0:
speed = B0;
break;
case 50:
speed = B50;
break;
case 75:
speed = B75;
break;
case 110:
speed = B110;
break;
case 134:
speed = B134;
break;
case 150:
speed = B150;
break;
case 200:
speed = B200;
break;
case 300:
speed = B300;
break;
case 600:
speed = B600;
break;
case 1200:
speed = B1200;
break;
case 1800:
speed = B1800;
break;
case 2400:
speed = B2400;
break;
case 4800:
speed = B4800;
break;
case 9600:
speed = B9600;
break;
case 19200:
speed = B19200;
break;
case 38400:
speed = B38400;
break;
case 57600:
speed = B57600;
break;
case 115200:
speed = B115200;
break;
case 230400:
speed = B230400;
break;
default:
fprintf(stderr, "ERROR: Unsupported BAUD=%d\n", g_baud);
@ -560,7 +634,8 @@ int main(int argc, char **argv, char **envp)
g_logstream = fopen(g_logfile, "w");
if (!g_logstream)
{
fprintf(stderr, "ERROR: Failed to open '%s' for writing\n", g_logfile);
fprintf(stderr, "ERROR: Failed to open '%s' for writing\n",
g_logfile);
return 5;
}
}
@ -581,32 +656,35 @@ int main(int argc, char **argv, char **envp)
return 7;
}
/* Open the selected serial port (blocking)*/
/* Open the selected serial port (blocking) */
g_fd = open(g_ttydev, O_RDWR);
if (g_fd < 0)
{
printconsole("ERROR: Failed to open %s: %s\n", g_ttydev, strerror(errno));
printconsole("ERROR: Failed to open %s: %s\n",
g_ttydev, strerror(errno));
return 8;
}
/* Configure the serial port in at the selected baud in 8-bit, no-parity, raw mode
* and turn off echo, etc.
/* Configure the serial port in at the selected baud in 8-bit, no-parity,
* raw mode and turn off echo, etc.
*/
ret = tcgetattr(g_fd, &g_termios);
if (ret < 0)
{
printconsole("ERROR: Failed to get termios for %s: %s\n", g_ttydev, strerror(errno));
printconsole("ERROR: Failed to get termios for %s: %s\n", g_ttydev,
strerror(errno));
close(g_fd);
return 9;
}
memcpy(&tty, &g_termios, sizeof(struct termios));
tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP|INLCR|IGNCR|ICRNL|IXON);
tty.c_iflag &=
~(IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR | ICRNL | IXON);
tty.c_oflag &= ~OPOST;
tty.c_lflag &= ~(ECHO|ECHONL|ICANON|ISIG|IEXTEN);
tty.c_cflag &= ~(CSIZE|PARENB);
tty.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN);
tty.c_cflag &= ~(CSIZE | PARENB);
tty.c_cflag |= CS8;
(void)cfsetispeed(&tty, speed);
@ -615,18 +693,20 @@ int main(int argc, char **argv, char **envp)
ret = tcsetattr(g_fd, TCSANOW, &tty);
if (ret < 0)
{
printconsole("ERROR: Failed to set termios for %s: %s\n", g_ttydev, strerror(errno));
printconsole("ERROR: Failed to set termios for %s: %s\n", g_ttydev,
strerror(errno));
close(g_fd);
return 10;
}
#if 1
/* Open the selected serial port (non-blocking)*/
/* Open the selected serial port (non-blocking) */
g_fdnb = open(g_ttydev, O_RDONLY | O_NONBLOCK);
if (g_fdnb < 0)
{
printconsole("ERROR: Failed to open %s: %s\n", g_ttydev, strerror(errno));
printconsole("ERROR: Failed to open %s: %s\n",
g_ttydev, strerror(errno));
return 11;
}
#else
@ -635,7 +715,8 @@ int main(int argc, char **argv, char **envp)
g_fdnb = dup(g_fd);
if (g_fdnb < 0)
{
printconsole("ERROR: Failed to dup %s fd=%d: %s\n", g_ttydev, g_fd, strerror(errno));
printconsole("ERROR: Failed to dup %s fd=%d: %s\n", g_ttydev, g_fd,
strerror(errno));
close_tty();
return 12;
}
@ -657,15 +738,15 @@ int main(int argc, char **argv, char **envp)
}
#endif
/* Catch attempts to control-C out of the program so that we can restore
* the TTY settings.
/* Catch attempts to control-C out of the program so that we can restore the
* TTY settings.
*/
signal(SIGINT, interrupt);
/* Loopo until control-C */
for (;;)
for (; ; )
{
/* Read characters from the console, and echo them to the target tty */
@ -686,7 +767,8 @@ int main(int argc, char **argv, char **envp)
ret = readbyte(g_fdnb, &ch);
if (ret == 0)
{
printconsole("ERROR: Unexpected number of bytes read(%d) from %s\n", ret, g_ttydev);
printconsole("ERROR: Unexpected number of bytes read(%d) from %s\n",
ret, g_ttydev);
close_tty();
return 15;
}
@ -701,14 +783,19 @@ int main(int argc, char **argv, char **envp)
ret = readbyte(g_fd, &ch1);
if (ret != 1)
{
printconsole("ERROR: Unexpected number of bytes read(%d) from %s\n", ret, g_ttydev);
printconsole
("ERROR: Unexpected number of bytes read(%d) from %s\n",
ret, g_ttydev);
close_tty();
return 15;
}
ret = readbyte(g_fd, &ch2);
if (ret != 1)
{
printconsole("ERROR: Unexpected number of bytes read(%d) from %s\n", ret, g_ttydev);
printconsole
("ERROR: Unexpected number of bytes read(%d) from %s\n",
ret, g_ttydev);
close_tty();
return 16;
}

47
crypto/blake2s.c
View file

@ -168,7 +168,8 @@ static void blake2s_set_lastblock(FAR blake2s_state *S)
S->f[0] = (uint32_t)-1;
}
static void blake2s_increment_counter(FAR blake2s_state *S, const uint32_t inc)
static void blake2s_increment_counter(FAR blake2s_state *S,
const uint32_t inc)
{
S->t[0] += inc;
S->t[1] += (S->t[0] < inc);
@ -236,8 +237,9 @@ static void blake2s_compress(FAR blake2s_state *S,
} while(0)
/* Size vs performance trade-off. With unrolling, on ARMv7-M function text
* is ~4 KiB and without ~1 KiB. Without unrolling we take ~25% performance
* hit. */
* is ~4 KiB and without ~1 KiB. Without unrolling we take ~25%
* performance hit.
*/
#if 1
/* Smaller, slightly slower. */
@ -249,7 +251,7 @@ static void blake2s_compress(FAR blake2s_state *S,
#else
/* Larger, slightly faster. */
(void)(round=0);
(void)(round = 0);
ROUND(0);
ROUND(1);
ROUND(2);
@ -277,11 +279,15 @@ static void blake2s_compress(FAR blake2s_state *S,
static void selftest_seq(FAR uint8_t *out, size_t len, uint32_t seed)
{
size_t i;
uint32_t t, a, b;
uint32_t t;
uint32_t a;
uint32_t b;
a = 0xDEAD4BAD * seed; /* prime */
b = 1;
/* fill the buf */
for (i = 0; i < len; i++)
{
t = a + b;
@ -304,11 +310,21 @@ static int blake2s_selftest(void)
/* Parameter sets. */
static const size_t b2s_md_len[4] = { 16, 20, 28, 32 };
static const size_t b2s_in_len[6] = { 0, 3, 64, 65, 255, 1024 };
size_t i, j, outlen, inlen;
static const size_t b2s_md_len[4] =
{
16, 20, 28, 32
};
static const size_t b2s_in_len[6] =
{
0, 3, 64, 65, 255, 1024
};
size_t i;
size_t j;
size_t outlen;
size_t inlen;
FAR uint8_t *in;
uint8_t md[32], key[32];
uint8_t md[32];
uint8_t key[32];
blake2s_state ctx;
int ret = -1;
@ -418,7 +434,9 @@ int blake2s_init(FAR blake2s_state *S, size_t outlen)
blake2_store16(P->xof_length, 0);
P->node_depth = 0;
P->inner_length = 0;
/* memset(P->reserved, 0, sizeof(P->reserved)); */
#if 0
memset(P->reserved, 0, sizeof(P->reserved));
#endif
blake2_memset(P->salt, 0, sizeof(P->salt));
blake2_memset(P->personal, 0, sizeof(P->personal));
return blake2s_init_param(S, P);
@ -449,7 +467,9 @@ int blake2s_init_key(FAR blake2s_state *S, size_t outlen, FAR const void *key,
blake2_store16(P->xof_length, 0);
P->node_depth = 0;
P->inner_length = 0;
/* memset(P->reserved, 0, sizeof(P->reserved)); */
#if 0
memset(P->reserved, 0, sizeof(P->reserved));
#endif
blake2_memset(P->salt, 0, sizeof(P->salt));
blake2_memset(P->personal, 0, sizeof(P->personal));
@ -465,8 +485,9 @@ int blake2s_init_key(FAR blake2s_state *S, size_t outlen, FAR const void *key,
int blake2s_update(FAR blake2s_state *S, FAR const void *pin, size_t inlen)
{
FAR const unsigned char * in = FAR (const unsigned char *)pin;
size_t left, fill;
FAR const unsigned char *in = FAR (const unsigned char *)pin;
size_t left;
size_t fill;
if (inlen <= 0)
{

43
drivers/contactless/mfrc522.c
View file

@ -100,9 +100,10 @@ static void mfrc522_unlock(FAR struct spi_dev_s *spi);
static int mfrc522_open(FAR struct file *filep);
static int mfrc522_close(FAR struct file *filep);
static ssize_t mfrc522_read(FAR struct file *, FAR char *, size_t);
static ssize_t mfrc522_write(FAR struct file *filep, FAR const char *buffer,
size_t buflen);
static ssize_t mfrc522_read(FAR struct file *filep, FAR char *buffer,
size_t buflen);
static ssize_t mfrc522_write(FAR struct file *filep,
FAR const char *buffer, size_t buflen);
static int mfrc522_ioctl(FAR struct file *filep, int cmd,
unsigned long arg);
@ -119,10 +120,13 @@ void mfrc522_softreset(FAR struct mfrc522_dev_s *dev);
int mfrc522_picc_select(FAR struct mfrc522_dev_s *dev,
FAR struct picc_uid_s *uid, uint8_t validbits);
/* IRQ Handling TODO:
static int mfrc522_irqhandler(FAR int irq, FAR void *context, FAR void* dev);
static inline int mfrc522_attachirq(FAR struct mfrc522_dev_s *dev, xcpt_t isr);
*/
#if 0 /* TODO */
/* IRQ Handling */
static int mfrc522_irqhandler(FAR int irq, FAR void *context, FAR void *dev);
static inline int mfrc522_attachirq(FAR struct mfrc522_dev_s *dev,
xcpt_t isr);
#endif
/****************************************************************************
* Private Data
@ -384,12 +388,12 @@ int mfrc522_calc_crc(FAR struct mfrc522_dev_s *dev, uint8_t *buffer,
tstart.tv_nsec -= 1000 * 1000 * 1000;
}
while(1)
while (1)
{
uint8_t irqreg;
irqreg = mfrc522_readu8(dev, MFRC522_DIV_IRQ_REG);
if ( irqreg & MFRC522_CRC_IRQ)
if (irqreg & MFRC522_CRC_IRQ)
{
break;
}
@ -488,7 +492,8 @@ int mfrc522_comm_picc(FAR struct mfrc522_dev_s *dev, uint8_t command,
if (command == MFRC522_TRANSCV_CMD)
{
value = mfrc522_readu8(dev, MFRC522_BIT_FRAMING_REG);
mfrc522_writeu8(dev, MFRC522_BIT_FRAMING_REG, value | MFRC522_START_SEND);
mfrc522_writeu8(dev, MFRC522_BIT_FRAMING_REG,
value | MFRC522_START_SEND);
}
/* Wait for the command to complete */
@ -962,7 +967,8 @@ int mfrc522_picc_select(FAR struct mfrc522_dev_s *dev,
/* Transmit the buffer and receive the response */
result = mfrc522_transcv_data(dev, buffer, buffer_used, resp_buf,
&resp_len, &txlastbits, rxalign, false);
&resp_len, &txlastbits, rxalign,
false);
/* More than one PICC in the field => collision */
@ -1023,6 +1029,7 @@ int mfrc522_picc_select(FAR struct mfrc522_dev_s *dev,
else
{
/* This was an ANTICOLLISION. */
/* We have all 32 bits of the UID in this Cascade Level */
curr_level_known_bits = 32;
@ -1033,6 +1040,7 @@ int mfrc522_picc_select(FAR struct mfrc522_dev_s *dev,
}
/* We do not check the CBB - it was constructed by us above. */
/* Copy the found UID bytes from buffer[] to uid->uid_data[] */
i = (buffer[2] == PICC_CMD_CT) ? 3 : 2; /* source index in buffer[] */
@ -1286,11 +1294,12 @@ void mfrc522_init(FAR struct mfrc522_dev_s *dev)
int mfrc522_selftest(FAR struct mfrc522_dev_s *dev)
{
uint8_t zeros[25] = {0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0};
uint8_t zeros[25] =
{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0
};
char outbuf[3 * 8 + 1];
uint8_t result[64];
int i;
@ -1599,7 +1608,7 @@ int mfrc522_register(FAR const char *devpath, FAR struct spi_dev_s *spi)
/* If returned firmware version is unknown don't register the device */
if (fwver != 0x90 && fwver != 0x91 && fwver != 0x92 && fwver != 0x88 )
if (fwver != 0x90 && fwver != 0x91 && fwver != 0x92 && fwver != 0x88)
{
mfrc522err("None supported device detected!\n");
goto firmware_error;

185
drivers/contactless/pn532.c
View file

@ -57,6 +57,7 @@
****************************************************************************/
/* Configuration ************************************************************/
/* Bit order H/W feature must be enabled in order to support LSB first
* operation.
*/
@ -109,20 +110,22 @@ static void pn532_unlock(FAR struct spi_dev_s *spi);
static int _open(FAR struct file *filep);
static int _close(FAR struct file *filep);
static ssize_t _read(FAR struct file *, FAR char *, size_t);
static ssize_t _read(FAR struct file *filep, FAR char *buffer, size_t buflen);
static ssize_t _write(FAR struct file *filep, FAR const char *buffer,
size_t buflen);
static int _ioctl(FAR struct file *filep,int cmd,unsigned long arg);
static int _ioctl(FAR struct file *filep, int cmd, unsigned long arg);
static uint8_t pn532_checksum(uint8_t value);
static uint8_t pn532_data_checksum(uint8_t *data, int datalen);
static uint8_t pn532_data_checksum(FAR uint8_t *data, int datalen);
int pn532_read(struct pn532_dev_s *dev, uint8_t *buff, uint8_t n);
int pn532_read(FAR struct pn532_dev_s *dev, uFAR int8_t *buff, uint8_t n);
/* IRQ Handling TODO:
static int pn532_irqhandler(FAR int irq, FAR void *context, FAR void* dev);
#if 0 /* TODO */
/* IRQ Handling */
static int pn532_irqhandler(FAR int irq, FAR void *context, FAR void *dev);
static inline int pn532_attachirq(FAR struct pn532_dev_s *dev, xcpt_t isr);
*/
#endif
/****************************************************************************
* Private Data
@ -137,10 +140,10 @@ static const struct file_operations g_pn532fops =
0,
_ioctl
#ifndef CONFIG_DISABLE_POLL
,0
, 0
#endif
#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
,0
, 0
#endif
};
@ -194,7 +197,7 @@ static inline void pn532_configspi(FAR struct spi_dev_s *spi)
(void)SPI_SETFREQUENCY(spi, CONFIG_PN532_SPI_FREQ);
}
static inline void pn532_select(struct pn532_dev_s *dev)
static inline void pn532_select(FAR struct pn532_dev_s *dev)
{
if (dev->config->select)
{
@ -206,7 +209,7 @@ static inline void pn532_select(struct pn532_dev_s *dev)
}
}
static inline void pn532_deselect(struct pn532_dev_s *dev)
static inline void pn532_deselect(FAR struct pn532_dev_s *dev)
{
if (dev->config->select)
{
@ -218,7 +221,7 @@ static inline void pn532_deselect(struct pn532_dev_s *dev)
}
}
static void pn532_frame_init(struct pn532_frame *frame, uint8_t cmd)
static void pn532_frame_init(FAR struct pn532_frame *frame, uint8_t cmd)
{
frame->preamble = PN532_PREAMBLE;
frame->start_code = PN532_SOF;
@ -227,7 +230,7 @@ static void pn532_frame_init(struct pn532_frame *frame, uint8_t cmd)
frame->len = 2;
}
static void pn532_frame_finish(struct pn532_frame *frame)
static void pn532_frame_finish(FAR struct pn532_frame *frame)
{
frame->lcs = pn532_checksum(frame->len);
frame->data[frame->len-1] = pn532_data_checksum(&frame->tfi, frame->len);
@ -239,7 +242,7 @@ static inline uint8_t pn532_checksum(uint8_t value)
return ~value + 1;
}
static uint8_t pn532_data_checksum(uint8_t *data, int datalen)
static uint8_t pn532_data_checksum(FAR uint8_t *data, int datalen)
{
uint8_t sum = 0x00;
int i;
@ -252,7 +255,7 @@ static uint8_t pn532_data_checksum(uint8_t *data, int datalen)
return pn532_checksum(sum);
}
bool pn532_rx_frame_is_valid(struct pn532_frame *f, bool check_data)
bool pn532_rx_frame_is_valid(FAR struct pn532_frame *f, bool check_data)
{
uint8_t chk;
@ -289,7 +292,7 @@ bool pn532_rx_frame_is_valid(struct pn532_frame *f, bool check_data)
return true;
}
static uint8_t pn532_status(struct pn532_dev_s *dev)
static uint8_t pn532_status(FAR struct pn532_dev_s *dev)
{
int rs;
@ -320,7 +323,7 @@ static uint8_t pn532_status(struct pn532_dev_s *dev)
*
****************************************************************************/
static int pn532_wait_rx_ready(struct pn532_dev_s *dev, int timeout)
static int pn532_wait_rx_ready(FAR struct pn532_dev_s *dev, int timeout)
{
int ret = OK;
@ -361,10 +364,10 @@ static int pn532_wait_rx_ready(struct pn532_dev_s *dev, int timeout)
****************************************************************************/
#if 0
static void pn532_writecommand(struct pn532_dev_s *dev, uint8_t cmd)
static void pn532_writecommand(FAR struct pn532_dev_s *dev, uint8_t cmd)
{
char cmd_buffer[16];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
FAR struct pn532_frame *f = (FAR struct pn532_frame *)cmd_buffer;
pn532_frame_init(f, cmd);
pn532_frame_finish(f);
@ -396,7 +399,7 @@ static void pn532_writecommand(struct pn532_dev_s *dev, uint8_t cmd)
*
****************************************************************************/
int pn532_read(struct pn532_dev_s *dev, uint8_t *buff, uint8_t n)
int pn532_read(FAR struct pn532_dev_s *dev, FAR uint8_t *buff, uint8_t n)
{
pn532_lock(dev->spi);
pn532_select(dev);
@ -409,7 +412,7 @@ int pn532_read(struct pn532_dev_s *dev, uint8_t *buff, uint8_t n)
return n;
}
int pn532_read_more(struct pn532_dev_s *dev, uint8_t *buff, uint8_t n)
int pn532_read_more(FAR struct pn532_dev_s *dev, FAR uint8_t *buff, uint8_t n)
{
pn532_lock(dev->spi);
pn532_select(dev);
@ -435,7 +438,7 @@ int pn532_read_more(struct pn532_dev_s *dev, uint8_t *buff, uint8_t n)
*
****************************************************************************/
int pn532_read_ack(struct pn532_dev_s *dev)
int pn532_read_ack(FAR struct pn532_dev_s *dev)
{
int res = 0;
uint8_t ack[6];
@ -473,7 +476,7 @@ int pn532_read_ack(struct pn532_dev_s *dev)
*
****************************************************************************/
int pn532_write_frame(struct pn532_dev_s *dev, struct pn532_frame *f)
int pn532_write_frame(FAR struct pn532_dev_s *dev, FAR struct pn532_frame *f)
{
int res = OK;
@ -502,7 +505,8 @@ int pn532_write_frame(struct pn532_dev_s *dev, struct pn532_frame *f)
return res;
}
int pn532_read_frame(struct pn532_dev_s *dev, struct pn532_frame *f, int max_size)
int pn532_read_frame(FAR struct pn532_dev_s *dev, FAR struct pn532_frame *f,
int max_size)
{
int res = -EIO;
@ -537,10 +541,10 @@ int pn532_read_frame(struct pn532_dev_s *dev, struct pn532_frame *f, int max_siz
return res;
}
bool pn532_set_config(struct pn532_dev_s *dev, uint8_t flags)
bool pn532_set_config(FAR struct pn532_dev_s *dev, uint8_t flags)
{
char cmd_buffer[2+7];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
char cmd_buffer[2 + 7];
FAR struct pn532_frame *f = (FAR struct pn532_frame *)cmd_buffer;
pn532_frame_init(f, PN532_COMMAND_SETPARAMETERS);
f->data[1] = flags;
@ -560,10 +564,11 @@ bool pn532_set_config(struct pn532_dev_s *dev, uint8_t flags)
return res;
}
int pn532_sam_config(struct pn532_dev_s *dev, struct pn_sam_settings_s *settings)
int pn532_sam_config(FAR struct pn532_dev_s *dev,
FAR struct pn_sam_settings_s *settings)
{
char cmd_buffer[4+7];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
char cmd_buffer[4 + 7];
FAR struct pn532_frame *f = (FAR struct pn532_frame *) cmd_buffer;
int res;
pn532_frame_init(f, PN532_COMMAND_SAMCONFIGURATION);
@ -596,11 +601,11 @@ int pn532_sam_config(struct pn532_dev_s *dev, struct pn_sam_settings_s *settings
return res;
}
int pn532_get_fw_version(struct pn532_dev_s *dev,
struct pn_firmware_version *fv)
int pn532_get_fw_version(FAR struct pn532_dev_s *dev,
FAR struct pn_firmware_version *fv)
{
uint8_t cmd_buffer[4+8+1];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
uint8_t cmd_buffer[4 + 8 + 1];
FAR struct pn532_frame *f = (FAR struct pn532_frame *) cmd_buffer;
struct pn_firmware_version *fw;
int res = -EIO;
@ -613,7 +618,7 @@ int pn532_get_fw_version(struct pn532_dev_s *dev,
{
if (f->data[0] == PN532_COMMAND_GETFIRMWAREVERSION + 1)
{
fw = (struct pn_firmware_version*) &f->data[1];
fw = (FAR struct pn_firmware_version *) &f->data[1];
pn532info("FW: %d.%d on IC:0x%X (Features: 0x%X)\n",
fw->ver, fw->rev, fw->ic, fw->support);
if (fv)
@ -629,10 +634,10 @@ int pn532_get_fw_version(struct pn532_dev_s *dev,
return res;
}
int pn532_write_gpio(struct pn532_dev_s *dev, uint8_t p3, uint8_t p7)
int pn532_write_gpio(FAR struct pn532_dev_s *dev, uint8_t p3, uint8_t p7)
{
uint8_t cmd_buffer[3+7];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
uint8_t cmd_buffer[3 + 7];
FAR struct pn532_frame *f = (FAR struct pn532_frame *) cmd_buffer;
int res = -EIO;
pn532_frame_init(f, PN532_COMMAND_WRITEGPIO);
@ -646,7 +651,8 @@ int pn532_write_gpio(struct pn532_dev_s *dev, uint8_t p3, uint8_t p7)
pn532_read(dev, cmd_buffer, 10);
tracetx("Resp:", cmd_buffer, 10);
pn532info("TFI=%x, data0=%X", f->tfi, f->data[0]);
if ((f->tfi == PN532_PN532TOHOST) && (f->data[0] == PN532_COMMAND_WRITEGPIO+1))
if ((f->tfi == PN532_PN532TOHOST) &&
(f->data[0] == PN532_COMMAND_WRITEGPIO + 1))
{
res = OK;
}
@ -655,11 +661,12 @@ int pn532_write_gpio(struct pn532_dev_s *dev, uint8_t p3, uint8_t p7)
return res;
}
uint32_t pn532_write_passive_data(struct pn532_dev_s *dev, uint8_t address,
uint8_t *data, uint8_t len)
uint32_t pn532_write_passive_data(FAR struct pn532_dev_s *dev,
uint8_t address, FAR uint8_t *data,
uint8_t len)
{
uint8_t cmd_buffer[8+7];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
FAR struct pn532_frame *f = (FAR struct pn532_frame *) cmd_buffer;
uint8_t resp[20];
uint32_t res = -EIO;
@ -675,10 +682,11 @@ uint32_t pn532_write_passive_data(struct pn532_dev_s *dev, uint8_t address,
{
if (dev->state == PN532_STATE_DATA_READY)
{
if (pn532_read_frame(dev, (struct pn532_frame *) resp, 15) == OK)
if (pn532_read_frame(dev, (FAR struct pn532_frame *) resp, 15)
== OK)
{
dev->state = PN532_STATE_IDLE;
f = (struct pn532_frame *) resp;
f = (FAR struct pn532_frame *) resp;
tracerx("passive target id resp:", f, f->len+6);
if (f->data[0] == PN532_COMMAND_INDATAEXCHANGE+1)
@ -692,11 +700,11 @@ uint32_t pn532_write_passive_data(struct pn532_dev_s *dev, uint8_t address,
return res;
}
uint32_t pn532_read_passive_data(struct pn532_dev_s *dev, uint8_t address,
uint8_t *data, uint8_t len)
uint32_t pn532_read_passive_data(FAR struct pn532_dev_s *dev, uint8_t address,
FAR uint8_t *data, uint8_t len)
{
uint8_t cmd_buffer[4+7];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
FAR struct pn532_frame *f = (FAR struct pn532_frame *) cmd_buffer;
uint8_t resp[30];
uint32_t res = -1;
@ -711,15 +719,15 @@ uint32_t pn532_read_passive_data(struct pn532_dev_s *dev, uint8_t address,
{
if (dev->state == PN532_STATE_DATA_READY)
{
if (pn532_read_frame(dev, (struct pn532_frame *)resp, 25) == OK)
if (pn532_read_frame(dev, (FAR struct pn532_frame *)resp, 25) == OK)
{
dev->state = PN532_STATE_IDLE;
f = (struct pn532_frame *) resp;
f = (FAR struct pn532_frame *) resp;
tracerx("passive target id resp:", f, f->len+6);
if (f->data[0] == PN532_COMMAND_INDATAEXCHANGE+1)
{
if(f->data[1] == 0 && data && len)
if (f->data[1] == 0 && data && len)
{
memcpy(data, &f->data[2], len);
}
@ -733,10 +741,11 @@ uint32_t pn532_read_passive_data(struct pn532_dev_s *dev, uint8_t address,
return res;
}
uint32_t pn532_read_passive_target_id(struct pn532_dev_s *dev, uint8_t baudrate)
uint32_t pn532_read_passive_target_id(FAR struct pn532_dev_s *dev,
uint8_t baudrate)
{
uint8_t cmd_buffer[4+7];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
FAR struct pn532_frame *f = (FAR struct pn532_frame *) cmd_buffer;
uint8_t resp[20];
uint32_t res = -EAGAIN;
int i;
@ -744,11 +753,14 @@ uint32_t pn532_read_passive_target_id(struct pn532_dev_s *dev, uint8_t baudrate)
if (dev->state == PN532_STATE_DATA_READY)
{
res = -EIO;
if (pn532_read_frame(dev, (struct pn532_frame *) resp, 15) == OK)
if (pn532_read_frame(dev, (FAR struct pn532_frame *) resp, 15) == OK)
{
FAR struct pn_poll_response *r;
dev->state = PN532_STATE_IDLE;
f = (struct pn532_frame *) resp;
struct pn_poll_response *r = (struct pn_poll_response *) &f->data[1];
f = (FAR struct pn532_frame *) resp;
r = (FAR struct pn_poll_response *) &f->data[1];
tracerx("passive target id resp:", f, f->len+6);
if (f->data[0] == PN532_COMMAND_INLISTPASSIVETARGET+1)
@ -757,13 +769,15 @@ uint32_t pn532_read_passive_target_id(struct pn532_dev_s *dev, uint8_t baudrate)
if (r->nbtg == 1)
{
FAR struct pn_target_type_a *t =
(FAR struct pn_target_type_a *)&r->target_data;
pn532info("Found %d card(s)\n", r->nbtg);
/* now supports only type_a cards
* if (poll_mode == PN532_POLL_MOD_106KBPS_A)
*/
struct pn_target_type_a *t = (struct pn_target_type_a *) &r->target_data;
pn532info("sens:0x%x sel:0x%x", t->sens_res, t->sel_res);
pn532info("idlen:0x%x ", t->nfcid_len);
@ -771,7 +785,7 @@ uint32_t pn532_read_passive_target_id(struct pn532_dev_s *dev, uint8_t baudrate)
* HACK: Using only top 4 bytes.
*/
for (i = 0; i < 4 /*t->nfcid_len*/; i++)
for (i = 0; i < 4 /* t->nfcid_len */; i++)
{
cid <<= 8;
cid |= t->nfcid_data[i];
@ -787,10 +801,11 @@ uint32_t pn532_read_passive_target_id(struct pn532_dev_s *dev, uint8_t baudrate)
}
static int pn532_read_passive_target(struct pn532_dev_s *dev, uint8_t baudrate)
static int pn532_read_passive_target(FAR struct pn532_dev_s *dev,
uint8_t baudrate)
{
uint8_t cmd_buffer[4+7];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
FAR struct pn532_frame *f = (FAR struct pn532_frame *) cmd_buffer;
pn532_frame_init(f, PN532_COMMAND_INLISTPASSIVETARGET);
f->data[1] = 1;
@ -804,7 +819,7 @@ bool pn532_set_rf_config(struct pn532_dev_s *dev, struct pn_rf_config_s *conf)
{
bool res = false;
uint8_t cmd_buffer[15+7];
struct pn532_frame *f = (struct pn532_frame *) cmd_buffer;
FAR struct pn532_frame *f = (FAR struct pn532_frame *) cmd_buffer;
pn532_frame_init(f, PN532_COMMAND_RFCONFIGURATION);
f->data[1] = conf->cfg_item;
@ -843,16 +858,16 @@ bool pn532_set_rf_config(struct pn532_dev_s *dev, struct pn_rf_config_s *conf)
#if 0
static inline int (FAR struct pn532_dev_s *dev, xcpt_t isr)
{
return dev->config->irqattach(dev,isr);
return dev->config->irqattach(dev, isr);
}
static int irq_handler(int irq, FAR void *context)
{
(void) irq;
(void) context;
(void)irq;
(void)context;
/* pn532info("*IRQ*\n"); */
/* work_queue(HPWORK, &g_dev->irq_work, pn532_worker, dev, 0); */
pn532info("*IRQ*\n");
work_queue(HPWORK, &g_dev->irq_work, pn532_worker, dev, 0);
return OK;
}
@ -912,9 +927,11 @@ static int _close(FAR struct file *filep)
dev->state = PN532_STATE_NOT_INIT;
#ifdef CONFIG_PM
if(dev->pm_level >= PM_SLEEP)
if (dev->pm_level >= PM_SLEEP)
{
//priv->config->reset(0);
#if 0
priv->config->reset(0);
#endif
}
#endif
@ -996,8 +1013,10 @@ static int _ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
case PN532IOC_READ_TAG_DATA:
{
struct pn_mifare_tag_data_s *tag_data = (struct pn_mifare_tag_data_s *) arg;
if (tag_data)
FAR struct pn_mifare_tag_data_s *tag_data =
(FAR struct pn_mifare_tag_data_s *) arg;
if (tag_data != 0)
{
/* HACK: get rid of previous command */
@ -1005,7 +1024,7 @@ static int _ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
if (pn532_wait_rx_ready(dev, 1))
{
pn532_read_passive_target_id(dev,0);
pn532_read_passive_target_id(dev, 0);
}
}
@ -1020,8 +1039,10 @@ static int _ioctl(FAR struct file *filep, int cmd, unsigned long arg)
case PN532IOC_WRITE_TAG_DATA:
{
struct pn_mifare_tag_data_s *tag_data = (struct pn_mifare_tag_data_s *) arg;
if (tag_data)
FAR struct pn_mifare_tag_data_s *tag_data =
(FAR struct pn_mifare_tag_data_s *) arg;
if (tag_data != 0)
{
/* HACK: get rid of previous command */
@ -1029,12 +1050,12 @@ static int _ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
if (pn532_wait_rx_ready(dev, 1))
{
pn532_read_passive_target_id(dev,0);
pn532_read_passive_target_id(dev, 0);
}
}
ret = pn532_write_passive_data(dev, tag_data->address,
(uint8_t *) &tag_data->data,
(FAR uint8_t *) &tag_data->data,
sizeof(tag_data->data));
dev->state = PN532_STATE_IDLE;
@ -1043,28 +1064,28 @@ static int _ioctl(FAR struct file *filep, int cmd, unsigned long arg)
break;
case PN532IOC_SET_SAM_CONF:
pn532_sam_config(dev, (struct pn_sam_settings_s *) arg);
pn532_sam_config(dev, (FAR struct pn_sam_settings_s *) arg);
break;
case PN532IOC_READ_PASSIVE:
if (dev->state == PN532_STATE_CMD_SENT)
{
uint32_t *ptr = (uint32_t *)((uintptr_t)arg);
*ptr = pn532_read_passive_target_id(dev,0);
FAR uint32_t *ptr = (FAR uint32_t *)((uintptr_t)arg);
*ptr = pn532_read_passive_target_id(dev, 0);
}
else
{
uint32_t *ptr = (uint32_t *)((uintptr_t)arg);
FAR uint32_t *ptr = (FAR uint32_t *)((uintptr_t)arg);
*ptr = -1;
}
break;
case PN532IOC_SET_RF_CONF:
pn532_set_rf_config(dev, (struct pn_rf_config_s *) arg);
pn532_set_rf_config(dev, (FAR struct pn_rf_config_s *) arg);
break;
case PN532IOC_SEND_CMD_READ_PASSIVE:
ret = pn532_read_passive_target(dev,0);
ret = pn532_read_passive_target(dev, 0);
if (ret == 0)
{
dev->state = PN532_STATE_CMD_SENT;
@ -1088,8 +1109,8 @@ static int _ioctl(FAR struct file *filep, int cmd, unsigned long arg)
case PN532IOC_GET_TAG_ID:
{
uint32_t *ptr = (uint32_t *)((uintptr_t)arg);
*ptr = pn532_read_passive_target_id(dev,0);
FAR uint32_t *ptr = (FAR uint32_t *)((uintptr_t)arg);
*ptr = pn532_read_passive_target_id(dev, 0);
}
break;

31
drivers/eeprom/i2c_xx24xx.c
View file

@ -249,7 +249,7 @@ static int ee24xx_waitwritecomplete(FAR struct ee24xx_dev_s *eedev,
ret = I2C_TRANSFER(eedev->i2c, msgs, 1);
retries--;
}
while(ret != 0 && retries > 0);
while (ret != 0 && retries > 0);
return ret;
}
@ -279,7 +279,7 @@ static int ee24xx_writepage(FAR struct ee24xx_dev_s *eedev, uint32_t memaddr,
msgs[0].frequency = eedev->freq;
msgs[0].addr = eedev->addr | (addr_hi & ((1 << eedev->haddrbits) - 1));
msgs[0].flags = 0;
msgs[0].buffer = eedev->addrlen==2 ? &maddr[0] : &maddr[1];
msgs[0].buffer = eedev->addrlen == 2 ? &maddr[0] : &maddr[1];
msgs[0].length = eedev->addrlen;
/* Write data without a restart nor a control byte */
@ -287,7 +287,7 @@ static int ee24xx_writepage(FAR struct ee24xx_dev_s *eedev, uint32_t memaddr,
msgs[1].frequency = msgs[0].frequency;
msgs[1].addr = msgs[0].addr;
msgs[1].flags = I2C_M_NOSTART;
msgs[1].buffer = (uint8_t*)buffer;
msgs[1].buffer = (uint8_t *)buffer;
msgs[1].length = len;
return I2C_TRANSFER(eedev->i2c, msgs, 2);
@ -441,22 +441,23 @@ static off_t ee24xx_seek(FAR struct file *filep, off_t offset, int whence)
/* Opengroup.org:
*
* "The lseek() function shall allow the file offset to be set beyond the end
* of the existing data in the file. If data is later written at this point,
* subsequent reads of data in the gap shall return bytes with the value 0
* until data is actually written into the gap."
* "The lseek() function shall allow the file offset to be set beyond the
* end of the existing data in the file. If data is later written at
* this point, subsequent reads of data in the gap shall return bytes
* with the value 0 until data is actually written into the gap."
*
* We can conform to the first part, but not the second. But return EINVAL if
* We can conform to the first part, but not the second. But return EINVAL
* if
*
* "...the resulting file offset would be negative for a regular file, block
* special file, or directory."
* "...the resulting file offset would be negative for a regular file,
* block special file, or directory."
*/
if (newpos >= 0)
{
filep->f_pos = newpos;
ret = newpos;
finfo("SEEK newpos %d\n",newpos);
finfo("SEEK newpos %d\n", newpos);
}
else
{
@ -513,7 +514,7 @@ static ssize_t ee24xx_read(FAR struct file *filep, FAR char *buffer,
msgs[0].frequency = eedev->freq;
msgs[0].addr = eedev->addr | (addr_hi & ((1 << eedev->haddrbits) - 1));
msgs[0].flags = 0;
msgs[0].buffer = eedev->addrlen==2 ? &addr[0] : &addr[1];
msgs[0].buffer = eedev->addrlen == 2 ? &addr[0] : &addr[1];
msgs[0].length = eedev->addrlen;
/* Read data */
@ -521,7 +522,7 @@ static ssize_t ee24xx_read(FAR struct file *filep, FAR char *buffer,
msgs[1].frequency = msgs[0].frequency;
msgs[1].addr = msgs[0].addr;
msgs[1].flags = I2C_M_READ;
msgs[1].buffer = (uint8_t*)buffer;
msgs[1].buffer = (uint8_t *)buffer;
msgs[1].length = len;
ret = I2C_TRANSFER(eedev->i2c, msgs, 2);
@ -602,8 +603,8 @@ static ssize_t ee24xx_write(FAR struct file *filep, FAR const char *buffer,
if (pageoff > 0)
{
finfo("First %d unaligned bytes at %d (pageoff %d)\n", cnt, filep->f_pos,
pageoff);
finfo("First %d unaligned bytes at %d (pageoff %d)\n",
cnt, filep->f_pos, pageoff);
ret = ee24xx_writepage(eedev, filep->f_pos, buffer, cnt);
if (ret < 0)

895
drivers/lcd/pcf8574_lcd_backpack.c
View file

File diff suppressed because it is too large Load diff

10
drivers/mtd/mx35.c
View file

@ -59,7 +59,9 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* Per the data sheet, MX35 parts can be driven with either SPI mode 0 (CPOL=0 and
* CPHA=0) or mode 3 (CPOL=1 and CPHA=1). If CONFIG_MX35_SPIMODE is not defined,
* mode 0 will be used.
@ -176,7 +178,7 @@
#define MX35_BP_BP1 (1 << 4) /* Bit 4: Block Protection 1 */
#define MX35_BP_BP2 (1 << 5) /* Bit 5: Block Protection 2 */
#define MX35_BP_BPRWD (1 << 7) /* Bit 7: Block Protection Register
Write Disable */
* Write Disable */
/* ECC Status register */
@ -628,7 +630,7 @@ static ssize_t mx35_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
mx35_waitstatus(priv, MX35_SR_OIP, false);
while(bytesleft)
while (bytesleft)
{
const uint32_t pageaddress = (position >> priv->pageshift) << priv->pageshift;
const uint32_t spaceleft = pageaddress + (1 << priv->pageshift) - position;
@ -646,7 +648,6 @@ static ssize_t mx35_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
bytesleft -= chunklength;
}
mx35_unlock(priv->dev);
mx35info("return nbytes: %d\n", (int)(nbytes - bytesleft));
@ -727,7 +728,7 @@ static ssize_t mx35_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
mx35_waitstatus(priv, MX35_SR_OIP, false);
while(bytesleft)
while (bytesleft)
{
const uint32_t pageaddress = (position >> priv->pageshift) << priv->pageshift;
const uint32_t spaceleft = pageaddress + (1 << priv->pageshift) - position;
@ -793,6 +794,7 @@ static int mx35_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
case MTDIOC_BULKERASE:
{
/* Erase the entire device */
ret = mx35_erase(dev, 0, priv->nsectors);
}
break;

7
drivers/sensors/apds9960.c
View file

@ -814,7 +814,7 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
}
else
{
if ( (ud_delta != 0) && (lr_delta != 0))
if ((ud_delta != 0) && (lr_delta != 0))
{
priv->gesture_state = FAR_STATE;
}
@ -1006,7 +1006,7 @@ static int apds9960_readgesture(FAR struct apds9960_dev_s *priv)
/* Keep looping as long as gesture data is valid */
while(1)
while (1)
{
/* Wait some time to collect next batch of FIFO data */
@ -1087,8 +1087,7 @@ static int apds9960_readgesture(FAR struct apds9960_dev_s *priv)
{
if (apds9960_decodegesture(priv))
{
//***TODO: U-Turn Gestures
//sninfo("gesture_motion = %d\n", gesture_motion);
/* TODO: U-Turn Gestures */
}
}

6
drivers/timers/arch_alarm.c
View file

@ -274,7 +274,7 @@ void up_timer_getmask(FAR uint64_t *mask)
ONESHOT_MAX_DELAY(g_oneshot_lower, &maxts);
maxticks = timespec_to_usec(&maxts) / USEC_PER_TICK;
for(; ; )
for (; ; )
{
uint64_t next = (*mask << 1) | 1;
if (next > maxticks)
@ -392,7 +392,7 @@ int up_alarm_start(FAR const struct timespec *ts)
}
#endif
/********************************************************************************
/*****************************************************************************
* Name: up_critmon_*
*
* Description:
@ -409,7 +409,7 @@ int up_alarm_start(FAR const struct timespec *ts)
*
* The second interface simple converts an elapsed time into well known
* units.
********************************************************************************/
*****************************************************************************/
#ifdef CONFIG_SCHED_CRITMONITOR
uint32_t up_critmon_gettime(void)

14
drivers/wireless/bluetooth/bt_uart_cc2564.c
View file

@ -11,13 +11,13 @@
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@ -103,7 +103,6 @@ static void cc2564_recv(FAR const struct btuart_lowerhalf_s *lower,
}
}
static int cc2564_load(FAR const struct btuart_lowerhalf_s *lower,
FAR const uint8_t *chipdata)
{
@ -113,7 +112,7 @@ static int cc2564_load(FAR const struct btuart_lowerhalf_s *lower,
uint32_t length = 0;
FAR const uint8_t *data;
for(data = chipdata; *data++; data += length)
for (data = chipdata; *data++; data += length)
{
uint16_t opcode;
opcode = ((uint16_t)(*(data+1)) << 8) + *data;
@ -223,4 +222,3 @@ int btuart_register(FAR const struct btuart_lowerhalf_s *lower)
return ret;
}

120
drivers/wireless/ieee802154/at86rf23x/at86rf23x.c
View file

@ -61,9 +61,9 @@
#include "at86rf23x.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#ifndef CONFIG_SCHED_HPWORK
# error High priority work queue required in this driver
@ -94,14 +94,14 @@
#define AT86RF23X_PA_ED 2
#define AT86RF23X_PA_SLEEP 3
/************************************************************************************
/****************************************************************************
* Private Types
************************************************************************************/
****************************************************************************/
/* AT86RF23x device instance
*
* Make sure that struct ieee802154_radio_s remains first. If not it will break the
* code
* Make sure that struct ieee802154_radio_s remains first. If not it will
* break the code
*/
struct at86rf23x_dev_s
@ -132,8 +132,8 @@ static void at86rf23x_unlock(FAR struct spi_dev_s *spi);
static void at86rf23x_setreg(FAR struct spi_dev_s *spi, uint32_t addr,
uint8_t val);
static uint8_t at86rf23x_getreg(FAR struct spi_dev_s *spi, uint32_t addr);
static int at86rf23x_writeframe(FAR struct spi_dev_s *spi, FAR uint8_t *frame,
uint8_t len);
static int at86rf23x_writeframe(FAR struct spi_dev_s *spi,
FAR uint8_t *frame, uint8_t len);
static uint8_t at86rf23x_readframe(FAR struct spi_dev_s *spi,
FAR uint8_t *frame_rx);
static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
@ -148,7 +148,6 @@ static void at86rf23x_irqwork_tx(FAR struct at86rf23x_dev_s *dev);
static void at86rf23x_irqworker(FAR void *arg);
static int at86rf23x_interrupt(int irq, FAR void *context, FAR void *arg);
static int at86rf23x_setchannel(FAR struct ieee802154_radio_s *ieee,
uint8_t chan);
static int at86rf23x_getchannel(FAR struct ieee802154_radio_s *ieee,
@ -293,7 +292,7 @@ static uint8_t at86rf23x_getreg(FAR struct spi_dev_s *spi, uint32_t addr)
at86rf23x_unlock(spi);
wlinfo("r[0x%02X]=0x%02X\n",addr,val[1]);
wlinfo("r[0x%02X]=0x%02X\n", addr, val[1]);
return val[1];
}
@ -349,9 +348,12 @@ static uint8_t at86rf23x_getregbits(FAR struct spi_dev_s *spi, uint8_t addr,
static int at86rf23x_writeframe(FAR struct spi_dev_s *spi, FAR uint8_t *frame,
uint8_t len)
{
//report_packet(frame_wr, len);
uint8_t reg = RF23X_SPI_FRAME_WRITE;
#if 0
report_packet(frame_wr, len);
#endif
at86rf23x_lock(spi);
SPI_SELECT(spi, SPIDEV_IEEE802154(0), true);
@ -378,7 +380,8 @@ static int at86rf23x_writeframe(FAR struct spi_dev_s *spi, FAR uint8_t *frame,
static uint8_t at86rf23x_readframe(FAR struct spi_dev_s *spi,
FAR uint8_t *frame_rx)
{
uint8_t len, reg;
uint8_t len;
uint8_t reg;
reg = RF23X_SPI_FRAME_READ;
@ -413,10 +416,10 @@ static uint8_t at86rf23x_getTRXstate(FAR struct at86rf23x_dev_s *dev)
*
* Description:
* Set the TRX state machine to the desired state. If the state machine
* cannot move to the desired state an ERROR is returned. If the transistion
* is successful an OK is returned. This is a long running function due to
* waiting for the transistion delay between states. This can be as long as
* 510us.
* cannot move to the desired state an ERROR is returned. If the
* transistion is successful an OK is returned. This is a long running
* function due to waiting for the transistion delay between states. This
* can be as long as 510us.
*
****************************************************************************/
@ -446,7 +449,7 @@ static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
/* Start the state change */
switch(state)
switch (state)
{
case TRX_CMD_TRXOFF:
if (status == TRX_STATUS_TRXOFF)
@ -473,7 +476,8 @@ static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
}
else if (force)
{
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE, TRX_CMD_FORCETRXOFF);
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE,
TRX_CMD_FORCETRXOFF);
up_udelay(RF23X_TIME_FORCE_TRXOFF);
}
@ -550,14 +554,16 @@ static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
{
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE, TRX_CMD_RX_ON);
(status == TRX_STATUS_TRXOFF) ? up_udelay(RF23X_TIME_TRXOFF_TO_PLL) :
up_udelay(RF23X_TIME_TRANSITION_PLL_ACTIVE);
(status == TRX_STATUS_TRXOFF) ?
up_udelay(RF23X_TIME_TRXOFF_TO_PLL) :
up_udelay(RF23X_TIME_TRANSITION_PLL_ACTIVE);
}
status = at86rf23x_getTRXstate(dev);
if ((status == TRX_STATUS_RXON) || (status == TRX_STATUS_PLLON))
{
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE, TRX_CMD_RX_AACK_ON);
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE,
TRX_CMD_RX_AACK_ON);
up_udelay(RF23X_TIME_TRANSITION_PLL_ACTIVE);
}
@ -577,21 +583,25 @@ static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
if (status == TRX_STATUS_TRXOFF)
{
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE, TRX_CMD_RX_ON);
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE,
TRX_CMD_RX_ON);
up_udelay(RF23X_TIME_TRXOFF_TO_PLL);
}
if ((status == TRX_STATUS_RXON) || (status == TRX_STATUS_PLLON))
{
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE, TRX_CMD_TX_ARET_ON);
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE,
TRX_CMD_TX_ARET_ON);
up_udelay(RF23X_TIME_TRANSITION_PLL_ACTIVE);
}
else if (status == TRX_STATUS_RXAACKON)
{
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE, TRX_CMD_RX_ON);
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE,
TRX_CMD_RX_ON);
up_udelay(RF23X_TIME_TRANSITION_PLL_ACTIVE);
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE, TRX_CMD_TX_ARET_ON);
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE,
TRX_CMD_TX_ARET_ON);
up_udelay(RF23X_TIME_TRANSITION_PLL_ACTIVE);
}
@ -615,7 +625,7 @@ static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
default:
wlerr("ERRPR: %s \n", EINVAL_STR);
init_status = 0;/* Placed this here to keep compiler happy when not in debug */
init_status = 0; /* Placed this here to keep compiler if no debug */
return -EINVAL;
}
@ -624,7 +634,8 @@ static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
wlerr("ERROR: State Transistion Error\n");
}
wlinfo("Radio state change state[0x%02x]->state[0x%02x]\n", init_status, status);
wlinfo("Radio state change state[0x%02x]->state[0x%02x]\n",
init_status, status);
return ret;
}
@ -653,7 +664,7 @@ static int at86rf23x_setchannel(FAR struct ieee802154_radio_s *ieee,
if (chan < 11 || chan > 26)
{
wlerr("ERROR: Invalid requested chan: %d\n",chan);
wlerr("ERROR: Invalid requested chan: %d\n", chan);
return -EINVAL;
}
@ -663,7 +674,8 @@ static int at86rf23x_setchannel(FAR struct ieee802154_radio_s *ieee,
if ((TRX_STATUS_SLEEP == state) || (TRX_STATUS_PON == state))
{
wlerr("ERROR: Radio in invalid mode [%02x] to set the channel\n", state);
wlerr("ERROR: Radio in invalid mode [%02x] to set the channel\n",
state);
return ERROR;
}
@ -862,8 +874,8 @@ static int at86rf23x_setpromisc(FAR struct ieee802154_radio_s *ieee,
FAR struct at86rf23x_dev_s *dev = (struct at86rf23x_dev_s *)ieee;
/* TODO: Check what mode I should be in to activate promiscuous mode:
* This is way to simple of an implementation. Many other things should be set
* and/or checked before we set the device into promiscuous mode
* This is way to simple of an implementation. Many other things should
* be set and/or checked before we set the device into promiscuous mode
*/
at86rf23x_setregbits(dev->spi, RF23X_XAHCTRL1_BITS_PROM_MODE, promisc);
@ -1000,7 +1012,7 @@ static int at86rf23x_gettxpower(FAR struct ieee802154_radio_s *ieee,
break;
case RF23X_TXPWR_POS_3_7:
*txpwr =0;
*txpwr = 0;
break;
case RF23X_TXPWR_POS_3_4:
@ -1024,7 +1036,7 @@ static int at86rf23x_gettxpower(FAR struct ieee802154_radio_s *ieee,
break;
case RF23X_TXPWR_0:
*txpwr =0;
*txpwr = 0;
break;
case RF23X_TXPWR_NEG_1:
@ -1177,7 +1189,8 @@ int at86rf23x_initialize(FAR struct at86rf23x_dev_s *dev)
static int at86rf23x_resetrf(FAR struct at86rf23x_dev_s *dev)
{
FAR const struct at86rf23x_lower_s *lower = dev->lower;
uint8_t trx_status, retry_cnt = 0;
uint8_t trx_status;
uint8_t retry_cnt = 0;
/* Reset the radio */
@ -1287,7 +1300,7 @@ static int at86rf23x_regdump(FAR struct at86rf23x_dev_s *dev)
{
uint32_t i;
char buf[4 + 16 * 3 + 2 + 1];
int len=0;
int len = 0;
wlinfo("RF23X regs:\n");
@ -1311,7 +1324,7 @@ static int at86rf23x_regdump(FAR struct at86rf23x_dev_s *dev)
if ((i & 15) == 15 || i == 0x2f)
{
sprintf(buf + len, "\n");
wlinfo("%s" ,buf);q
wlinfo("%s", buf);
}
}
@ -1335,9 +1348,9 @@ static void at86rf23x_irqworker(FAR void *arg)
wlinfo("IRQ: 0x%02X\n", irq_status);
if ((irq_status & (1<<3)) != 0)
if ((irq_status & (1 << 3)) != 0)
{
if ((irq_status & (1<<2)) != 0)
if ((irq_status & (1 << 2)) != 0)
{
at86rf23x_irqwork_rx(dev);
}
@ -1430,10 +1443,11 @@ static int at86rf23x_transmit(FAR struct ieee802154_radio_s *ieee,
FAR struct at86rf23x_dev_s *dev = (FAR struct at86rf23x_dev_s *)ieee;
/* TODO:
* A plan needs to be made on when we declare the transmission successful.
* 1. If the packet is sent
* 2. If we receive an ACK.
* 3. Where do we control the retry process?
* A plan needs to be made on when we declare the transmission successful.
*
* 1. If the packet is sent
* 2. If we receive an ACK.
* 3. Where do we control the retry process?
*/
if (at86rf23x_setTRXstate(dev, TRX_CMD_PLL_ON, false))
@ -1469,8 +1483,9 @@ static int at86rf23x_transmit(FAR struct ieee802154_radio_s *ieee,
*
****************************************************************************/
FAR struct ieee802154_radio_s *at86rf23x_init(FAR struct spi_dev_s *spi,
FAR const struct at86rf23x_lower_s *lower)
FAR struct ieee802154_radio_s *
at86rf23x_init(FAR struct spi_dev_s *spi,
FAR const struct at86rf23x_lower_s *lower)
{
FAR struct at86rf23x_dev_s *dev;
struct ieee802154_cca_s cca;
@ -1530,17 +1545,23 @@ FAR struct ieee802154_radio_s *at86rf23x_init(FAR struct spi_dev_s *spi,
at86rf23x_setchannel(&dev->ieee, 12);
#if 0
/* Configure the Pan id */
//at86rf23x_setpanid(&dev->ieee, IEEE802154_PAN_DEFAULT);
at86rf23x_setpanid(&dev->ieee, IEEE802154_PAN_DEFAULT);
#endif
#if 0
/* Configure the Short Addr */
//at86rf23x_setsaddr(&dev->ieee, IEEE802154_SADDR_UNSPEC);
at86rf23x_setsaddr(&dev->ieee, IEEE802154_SADDR_UNSPEC);
#endif
#if 0
/* Configure the IEEE Addr */
//at86rf23x_seteaddr(&dev->ieee, IEEE802154_EADDR_UNSPEC);
at86rf23x_seteaddr(&dev->ieee, IEEE802154_EADDR_UNSPEC);
#endif
/* Default device params at86rf23x defaults to energy detect only */
@ -1550,8 +1571,11 @@ FAR struct ieee802154_radio_s *at86rf23x_init(FAR struct spi_dev_s *spi,
* threshold -69 dBm */
at86rf23x_setcca(&dev->ieee, &cca);
#if 0
/* Put the Device to RX ON Mode */
//at86rf23x_setTRXstate(dev, TRX_CMD_RX_ON, false);
at86rf23x_setTRXstate(dev, TRX_CMD_RX_ON, false);
#endif
/* Enable Radio IRQ */

27
drivers/wireless/ieee802154/mrf24j40/mrf24j40.c
View file

@ -98,7 +98,7 @@ static int mrf24j40_energydetect(FAR struct mrf24j40_radio_s *dev,
{
uint8_t reg;
/* Manually enable the LNA*/
/* Manually enable the LNA */
mrf24j40_setpamode(dev, MRF24J40_PA_ED);
@ -116,7 +116,7 @@ static int mrf24j40_energydetect(FAR struct mrf24j40_radio_s *dev,
* complete.
*/
while(!(mrf24j40_getreg(dev->spi, MRF24J40_BBREG6) & 0x01));
while (!(mrf24j40_getreg(dev->spi, MRF24J40_BBREG6) & 0x01));
/* 3. Read RSSI 0x210<7:0> – The RSSI register contains the averaged RSSI
* received power level for 8 symbol periods.
@ -239,7 +239,7 @@ void mrf24j40_dopoll_gts(FAR void *arg)
{
/* Now the txdesc is in use */
dev->gts_busy[gts]= 1;
dev->gts_busy[gts] = 1;
/* Setup the transaction on the device in the open GTS FIFO */
@ -287,7 +287,8 @@ void mrf24j40_norm_setup(FAR struct mrf24j40_radio_s *dev,
/* Setup the FIFO */
mrf24j40_setup_fifo(dev, frame->io_data, frame->io_len, MRF24J40_TXNORM_FIFO);
mrf24j40_setup_fifo(dev, frame->io_data, frame->io_len,
MRF24J40_TXNORM_FIFO);
/* If the frame control field contains an acknowledgment request, set the
* TXNACKREQ bit. See IEEE 802.15.4/2003 7.2.1.1 page 112 for info.
@ -364,8 +365,9 @@ void mrf24j40_gts_setup(FAR struct mrf24j40_radio_s *dev, uint8_t fifo,
*
****************************************************************************/
void mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev, FAR const uint8_t *buf,
uint8_t length, uint32_t fifo_addr)
void mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev,
FAR const uint8_t *buf, uint8_t length,
uint32_t fifo_addr)
{
int hlen = 3; /* Include frame control and seq number */
@ -377,11 +379,13 @@ void mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev, FAR const uint8_t *bu
frame_ctrl = buf[0];
frame_ctrl |= (buf[1] << 8);
if ((frame_ctrl & IEEE802154_FRAMECTRL_DADDR)== IEEE802154_ADDRMODE_SHORT)
if ((frame_ctrl & IEEE802154_FRAMECTRL_DADDR) ==
IEEE802154_ADDRMODE_SHORT)
{
hlen += 2 + 2; /* Destination PAN + shortaddr */
}
else if ((frame_ctrl & IEEE802154_FRAMECTRL_DADDR) == IEEE802154_ADDRMODE_EXTENDED)
else if ((frame_ctrl & IEEE802154_FRAMECTRL_DADDR) ==
IEEE802154_ADDRMODE_EXTENDED)
{
hlen += 2 + 8; /* Destination PAN + extaddr */
}
@ -391,11 +395,13 @@ void mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev, FAR const uint8_t *bu
hlen += 2; /* No PAN compression, source PAN is different from dest PAN */
}
if ((frame_ctrl & IEEE802154_FRAMECTRL_SADDR)== IEEE802154_ADDRMODE_SHORT)
if ((frame_ctrl & IEEE802154_FRAMECTRL_SADDR) ==
IEEE802154_ADDRMODE_SHORT)
{
hlen += 2; /* Source saddr */
}
else if ((frame_ctrl & IEEE802154_FRAMECTRL_SADDR) == IEEE802154_ADDRMODE_EXTENDED)
else if ((frame_ctrl & IEEE802154_FRAMECTRL_SADDR) ==
IEEE802154_ADDRMODE_EXTENDED)
{
hlen += 8; /* Ext saddr */
}
@ -404,7 +410,6 @@ void mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev, FAR const uint8_t *bu
mrf24j40_setreg(dev->spi, fifo_addr++, hlen);
/* Frame length */
mrf24j40_setreg(dev->spi, fifo_addr++, length);

20
drivers/wireless/ieee802154/mrf24j40/mrf24j40_getset.c
View file

@ -149,7 +149,7 @@ int mrf24j40_setchannel(FAR struct mrf24j40_radio_s *dev, uint8_t chan)
{
if (chan < 11 || chan > 26)
{
wlerr("ERROR: Invalid chan: %d\n",chan);
wlerr("ERROR: Invalid chan: %d\n", chan);
return -EINVAL;
}
@ -240,9 +240,11 @@ int mrf24j40_seteaddr(FAR struct mrf24j40_radio_s *dev,
* Name: mrf24j40_setcoordsaddr
*
* Description:
* Define the coordinator short address. The following addresses are special:
* FFFEh : Broadcast
* FFFFh : Unspecified
* Define the coordinator short address. The following addresses are
* special:
*
* FFFEh : Broadcast
* FFFFh : Unspecified
*
****************************************************************************/
@ -262,8 +264,10 @@ int mrf24j40_setcoordsaddr(FAR struct mrf24j40_radio_s *dev,
* Name: mrf24j40_setcoordeaddr
*
* Description:
* Define the coordinator extended address. The following addresses are special:
* FFFFFFFFFFFFFFFFh : Unspecified
* Define the coordinator extended address. The following addresses are
* special:
*
* FFFFFFFFFFFFFFFFh : Unspecified
*
****************************************************************************/
@ -364,9 +368,9 @@ int mrf24j40_settxpower(FAR struct mrf24j40_radio_s *dev,
return -EINVAL;
}
wlinfo("Remaining attenuation: %d mBm\n",txpwr);
wlinfo("Remaining attenuation: %d mBm\n", txpwr);
switch(txpwr/100)
switch (txpwr / 100)
{
case -9:
case -8:

93
drivers/wireless/ieee802154/mrf24j40/mrf24j40_radif.c
View file

@ -70,7 +70,8 @@
* Private Function Prototypes
****************************************************************************/
static void mrf24j40_mactimer(FAR struct mrf24j40_radio_s *dev, int numsymbols);
static void mrf24j40_mactimer(FAR struct mrf24j40_radio_s *dev,
int numsymbols);
static void mrf24j40_setorder(FAR struct mrf24j40_radio_s *dev, uint8_t bo,
uint8_t so);
static void mrf24j40_slpclkcal(FAR struct mrf24j40_radio_s *dev);
@ -81,7 +82,7 @@ static void mrf24j40_slpclkcal(FAR struct mrf24j40_radio_s *dev);
static const uint8_t g_allones[8] =
{
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
};
/****************************************************************************
@ -92,7 +93,8 @@ static const uint8_t g_allones[8] =
* Private Functions
****************************************************************************/
static void mrf24j40_mactimer(FAR struct mrf24j40_radio_s *dev, int numsymbols)
static void mrf24j40_mactimer(FAR struct mrf24j40_radio_s *dev,
int numsymbols)
{
uint16_t nhalfsym;
uint8_t reg;
@ -113,10 +115,10 @@ static void mrf24j40_mactimer(FAR struct mrf24j40_radio_s *dev, int numsymbols)
/* Set the timer count and enable interrupts */
reg = (nhalfsym & 0xFF);
reg = (nhalfsym & 0xff);
mrf24j40_setreg(dev->spi, MRF24J40_HSYMTMRL, reg);
reg = (nhalfsym >> 8) & 0xFF;
reg = (nhalfsym >> 8) & 0xff;
mrf24j40_setreg(dev->spi, MRF24J40_HSYMTMRH, reg);
}
@ -154,17 +156,17 @@ static void mrf24j40_setorder(FAR struct mrf24j40_radio_s *dev, uint8_t bo,
wlinfo("MAINCNT: %lu, REMCNT: %lu\n", maincnt, remcnt);
/* Program the Main Counter, MAINCNT (0x229<1:0>, 0x228, 0x227, 0x226), and
* Remain Counter, REMCNT (0x225, 0x224), according to BO and SO values. Refer
* to Section 3.15.1.3 “Sleep Mode * Counters”
/* Program the Main Counter, MAINCNT (0x229<1:0>, 0x228, 0x227,
* 0x226), and Remain Counter, REMCNT (0x225, 0x224), according to BO
* and SO values. Refer to Section 3.15.1.3 “Sleep Mode * Counters”
*/
mrf24j40_setreg(dev->spi, MRF24J40_REMCNTL, (remcnt & 0xFF));
mrf24j40_setreg(dev->spi, MRF24J40_REMCNTH, ((remcnt >> 8) & 0xFF));
mrf24j40_setreg(dev->spi, MRF24J40_REMCNTL, (remcnt & 0xff));
mrf24j40_setreg(dev->spi, MRF24J40_REMCNTH, ((remcnt >> 8) & 0xff));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT0, (maincnt & 0xFF));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT1, ((maincnt >> 8) & 0xFF));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT2, ((maincnt >> 16) & 0xFF));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT0, (maincnt & 0xff));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT1, ((maincnt >> 8) & 0xff));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT2, ((maincnt >> 16) & 0xff));
mrf24j40_setreg(dev->spi, MRF24J40_MAINCNT3, ((maincnt >> 24) & 0x03));
}
@ -172,7 +174,7 @@ static void mrf24j40_setorder(FAR struct mrf24j40_radio_s *dev, uint8_t bo,
* After configuring BO and SO, the beacon frame will be sent immediately.
*/
mrf24j40_setreg(dev->spi, MRF24J40_ORDER, ((bo << 4) & 0xF0) | (so & 0x0F));
mrf24j40_setreg(dev->spi, MRF24J40_ORDER, ((bo << 4) & 0xf0) | (so & 0x0f));
}
static void mrf24j40_slpclkcal(FAR struct mrf24j40_radio_s *dev)
@ -190,14 +192,14 @@ static void mrf24j40_slpclkcal(FAR struct mrf24j40_radio_s *dev)
mrf24j40_setreg(dev->spi, MRF24J40_SLPCON1,
0x01 | MRF24J40_SLPCON1_CLKOUT_DISABLED);
/* Begin calibration by setting the SLPCALEN bit (SLPCAL2 0x20B<4>) to
/* Begin calibration by setting the SLPCALEN bit (SLPCAL2 0x20b<4>) to
* ‘1’. Sixteen samples of the SLPCLK are counted and stored in the
* SLPCAL register. No need to mask, this is the only writable bit
*/
mrf24j40_setreg(dev->spi, MRF24J40_SLPCAL2, MRF24J40_SLPCAL2_SLPCALEN);
/* Calibration is complete when the SLPCALRDY bit (SLPCAL2 0x20B<7>) is
/* Calibration is complete when the SLPCALRDY bit (SLPCAL2 0x20b<7>) is
* set to ‘1’.
*/
@ -211,7 +213,7 @@ static void mrf24j40_slpclkcal(FAR struct mrf24j40_radio_s *dev)
dev->slpclkper = reg;
reg = mrf24j40_getreg(dev->spi, MRF24J40_SLPCAL1);
dev->slpclkper |= (reg << 8);
reg = mrf24j40_getreg(dev->spi, MRF24J40_SLPCAL2) & 0x0F;
reg = mrf24j40_getreg(dev->spi, MRF24J40_SLPCAL2) & 0x0f;
dev->slpclkper |= (reg << 16);
dev->slpclkper = (dev->slpclkper * 50 / 16);
@ -220,10 +222,9 @@ static void mrf24j40_slpclkcal(FAR struct mrf24j40_radio_s *dev)
/****************************************************************************
* Public Functions
****************************************************************************/
/* Radio Interface Functions ***********************************************/
int mrf24j40_bind(FAR struct ieee802154_radio_s *radio,
FAR struct ieee802154_radiocb_s *radiocb)
FAR struct ieee802154_radiocb_s *radiocb)
{
FAR struct mrf24j40_radio_s *dev = (FAR struct mrf24j40_radio_s *)radio;
@ -279,7 +280,8 @@ int mrf24j40_txnotify(FAR struct ieee802154_radio_s *radio, bool gts)
{
/* Schedule to serialize the poll on the worker thread. */
work_queue(HPWORK, &dev->csma_pollwork, mrf24j40_dopoll_csma, dev, 0);
work_queue(HPWORK, &dev->csma_pollwork, mrf24j40_dopoll_csma,
dev, 0);
}
}
@ -291,8 +293,9 @@ int mrf24j40_txnotify(FAR struct ieee802154_radio_s *radio, bool gts)
*
* Description:
* Transmit a packet without regard to supeframe structure after a certain
* number of symbols. This function is used to send Data Request responses.
* It can also be used to send data immediately if the delay is set to 0.
* number of symbols. This function is used to send Data Request
* responses. It can also be used to send data immediately if the delay
* is set to 0.
*
* Input Parameters:
* radio - Reference to the radio driver state structure
@ -389,7 +392,6 @@ int mrf24j40_rxenable(FAR struct ieee802154_radio_s *radio, bool enable)
dev->rxenabled = enable;
if (enable)
{
/* Disable packet reception. See pg. 109 of datasheet */
@ -433,17 +435,17 @@ int mrf24j40_reset(FAR struct ieee802154_radio_s *radio)
/* Software reset */
mrf24j40_setreg(dev->spi, MRF24J40_SOFTRST , 0x07); /* 00000111 Reset */
while(mrf24j40_getreg(dev->spi, MRF24J40_SOFTRST) & 0x07);
while (mrf24j40_getreg(dev->spi, MRF24J40_SOFTRST) & 0x07);
/* Apply recommended settings */
mrf24j40_setreg(dev->spi, MRF24J40_PACON2 , 0x98); /* 10011000 Enable FIFO (default), TXONTS=6 (recommended), TXONT<8:7>=0 */
mrf24j40_setreg(dev->spi, MRF24J40_TXSTBL , 0x95); /* 10010101 set the SIFS period. RFSTBL=9, MSIFS=5, aMinSIFSPeriod=14 (min 12) */
mrf24j40_setreg(dev->spi, MRF24J40_TXPEND , 0x7C); /* 01111100 set the LIFS period, MLIFS=1Fh=31 aMinLIFSPeriod=40 (min 40) */
mrf24j40_setreg(dev->spi, MRF24J40_TXPEND , 0x7c); /* 01111100 set the LIFS period, MLIFS=1Fh=31 aMinLIFSPeriod=40 (min 40) */
mrf24j40_setreg(dev->spi, MRF24J40_TXTIME , 0x30); /* 00110000 set the turnaround time, TURNTIME=3 aTurnAroundTime=12 */
mrf24j40_setreg(dev->spi, MRF24J40_RFCON1 , 0x02); /* 00000010 VCO optimization, recommended value */
mrf24j40_setreg(dev->spi, MRF24J40_RFCON2 , 0x80); /* 10000000 Enable PLL */
mrf24j40_setreg(dev->spi, MRF24J40_RFCON6 , 0x90); /* 10010000 TX filter enable, fast 20M recovery, No bat monitor*/
mrf24j40_setreg(dev->spi, MRF24J40_RFCON6 , 0x90); /* 10010000 TX filter enable, fast 20M recovery, No bat monitor */
mrf24j40_setreg(dev->spi, MRF24J40_RFCON7 , 0x80); /* 10000000 Sleep clock on internal 100 kHz */
mrf24j40_setreg(dev->spi, MRF24J40_RFCON8 , 0x10); /* 00010000 VCO control bit, as recommended */
mrf24j40_setreg(dev->spi, MRF24J40_BBREG6 , 0x40); /* 01000000 Append RSSI to rx packets */
@ -455,32 +457,35 @@ int mrf24j40_reset(FAR struct ieee802154_radio_s *radio)
mrf24j40_slpclkcal(dev);
/* For now, we want to always just have the frame pending bit set when
* acknowledging a Data Request command. The standard says that the coordinator
* can do this if it needs time to figure out whether it has data or not
* acknowledging a Data Request command. The standard says that the
* coordinator* can do this if it needs time to figure out whether it has
* data or not
*/
mrf24j40_setreg(dev->spi, MRF24J40_ACKTMOUT, 0x39 | MRF24J40_ACKTMOUT_DRPACK);
mrf24j40_setreg(dev->spi, MRF24J40_ACKTMOUT,
0x39 | MRF24J40_ACKTMOUT_DRPACK);
/* Set WAKETIME to recommended value for 100kHz SLPCLK Source.
*
* NOTE!!!: The datasheet specifies that WAKETIME > WAKECNT. It appears that
* it is even sensitive to the order in which you set WAKECNT and WAKETIME.
* Meaning, if you set WAKECNT first and it goes higher than WAKETIME, and
* then raise WAKETIME above WAKECNT, the device will not function correctly.
* Therefore, be careful when changing these registers
* NOTE!!!: The datasheet specifies that WAKETIME > WAKECNT. It appears
* that it is even sensitive to the order in which you set WAKECNT and
* WAKETIME. Meaning, if you set WAKECNT first and it goes higher than
* WAKETIME, and then raise WAKETIME above WAKECNT, the device will not
* function correctly. Therefore, be careful when changing these registers
*/
mrf24j40_setreg(dev->spi, MRF24J40_WAKETIMEL, 0xD2);
mrf24j40_setreg(dev->spi, MRF24J40_WAKETIMEL, 0xd2);
mrf24j40_setreg(dev->spi, MRF24J40_WAKETIMEH, 0x00);
/* Set WAKECNT (SLPACK 0x35<6:0>) value = 0x5F to set the main oscillator
/* Set WAKECNT (SLPACK 0x35<6:0>) value = 0x5f to set the main oscillator
* (20 MHz) start-up timer value.
*/
mrf24j40_setreg(dev->spi, MRF24J40_SLPACK, (0x0C8 & MRF24J40_SLPACK_WAKECNT0_6));
mrf24j40_setreg(dev->spi, MRF24J40_SLPACK,
(0x0c8 & MRF24J40_SLPACK_WAKECNT0_6));
reg = mrf24j40_getreg(dev->spi, MRF24J40_RFCTL);
reg &= ~MRF24J40_RFCTRL_WAKECNT7_8;
reg |= ((0x0C8 >> 7) & 0x03) << 3;
reg |= ((0x0c8 >> 7) & 0x03) << 3;
mrf24j40_setreg(dev->spi, MRF24J40_RFCTL, reg);
/* Enable the SLPIF and WAKEIF flags */
@ -510,7 +515,7 @@ int mrf24j40_reset(FAR struct ieee802154_radio_s *radio)
mrf24j40_setrxmode(dev, MRF24J40_RXMODE_NORMAL);
mrf24j40_settxpower(dev, 0); /*16. Set transmitter power .*/
mrf24j40_settxpower(dev, 0); /* 16. Set transmitter power. */
mrf24j40_setpamode(dev, MRF24J40_PA_AUTO);
@ -566,7 +571,7 @@ int mrf24j40_setattr(FAR struct ieee802154_radio_s *radio,
FAR const union ieee802154_attr_u *attrval)
{
FAR struct mrf24j40_radio_s *dev = (FAR struct mrf24j40_radio_s *)radio;
int ret = IEEE802154_STATUS_SUCCESS;;
int ret = IEEE802154_STATUS_SUCCESS;
switch (attr)
{
@ -653,9 +658,10 @@ int mrf24j40_beaconstart(FAR struct ieee802154_radio_s *radio,
reg |= MRF24J40_TXMCR_SLOTTED;
mrf24j40_setreg(dev->spi, MRF24J40_TXMCR, reg);
/* Load the beacon frame into the TXBFIFO (0x080-0x0FF). */
/* Load the beacon frame into the TXBFIFO (0x080-0x0ff). */
mrf24j40_setup_fifo(dev, beacon->bf_data, beacon->bf_len, MRF24J40_BEACON_FIFO);
mrf24j40_setup_fifo(dev, beacon->bf_data, beacon->bf_len,
MRF24J40_BEACON_FIFO);
/* The radio layer is responsible for setting the BSN. */
@ -701,7 +707,8 @@ int mrf24j40_beaconupdate(FAR struct ieee802154_radio_s *radio,
{
FAR struct mrf24j40_radio_s *dev = (FAR struct mrf24j40_radio_s *)radio;
mrf24j40_setup_fifo(dev, beacon->bf_data, beacon->bf_len, MRF24J40_BEACON_FIFO);
mrf24j40_setup_fifo(dev, beacon->bf_data, beacon->bf_len,
MRF24J40_BEACON_FIFO);
mrf24j40_beacon_trigger(dev);
return OK;

19
fs/hostfs/hostfs.c
View file

@ -244,7 +244,8 @@ static void hostfs_mkpath(FAR struct hostfs_mountpt_s *fs,
x += 2;
}
else if (relpath[x] == '/' && relpath[x+1] != '/' && relpath[x+1] != '\0')
else if (relpath[x] == '/' && relpath[x + 1] != '/' &&
relpath[x + 1] != '\0')
{
depth++;
x++;
@ -278,7 +279,6 @@ static int hostfs_open(FAR struct file *filep, FAR const char *relpath,
DEBUGASSERT((filep->f_priv == NULL) && (filep->f_inode != NULL));
/* Get the mountpoint inode reference from the file structure and the
* mountpoint private data from the inode structure
*/
@ -391,12 +391,14 @@ static int hostfs_close(FAR struct file *filep)
hostfs_semtake(fs);
/* Check if we are the last one with a reference to the file and
* only close if we are. */
* only close if we are.
*/
if (hf->crefs > 1)
{
/* The file is opened more than once. Just decrement the
* reference count and return. */
* reference count and return.
*/
hf->crefs--;
goto okout;
@ -933,7 +935,9 @@ static int hostfs_bind(FAR struct inode *blkdriver, FAR const void *data,
/* Create an instance of the mountpt state structure */
fs = (FAR struct hostfs_mountpt_s *)kmm_zalloc(sizeof(struct hostfs_mountpt_s));
fs = (FAR struct hostfs_mountpt_s *)
kmm_zalloc(sizeof(struct hostfs_mountpt_s));
if (fs == NULL)
{
return -ENOMEM;
@ -951,7 +955,7 @@ static int hostfs_bind(FAR struct inode *blkdriver, FAR const void *data,
}
ptr = strtok_r(options, ",", &saveptr);
while(ptr != NULL)
while (ptr != NULL)
{
if ((strncmp(ptr, "fs=", 3) == 0))
{
@ -964,7 +968,8 @@ static int hostfs_bind(FAR struct inode *blkdriver, FAR const void *data,
kmm_free(options);
/* If the global semaphore hasn't been initialized, then
* initialized it now. */
* initialized it now.
*/
fs->fs_sem = &g_sem;
if (!g_seminitialized)

4
libs/libc/math/lib_gamma.c
View file

@ -36,7 +36,7 @@
* "Lanczos Implementation of the Gamma Function" - Paul Godfrey (2001)
* "An Analysis of the Lanczos Gamma Approximation" - Glendon Ralph Pugh (2004)
*
* approximation method:
* Approximation method:
*
* (x - 0.5) S(x)
* Gamma(x) = (x + g - 0.5) * ----------------
@ -94,7 +94,7 @@
__x = (x); \
} \
} \
while(0)
while (0)
#define N 12

9
libs/libc/netdb/lib_parsehostfile.c
View file

@ -76,7 +76,6 @@ struct hostent_info_s
char hi_data[1];
};
/****************************************************************************
* Private functions
****************************************************************************/
@ -181,8 +180,9 @@ static int lib_skipline(FAR FILE *stream, FAR size_t *nread)
*
****************************************************************************/
static ssize_t lib_copystring(FAR FILE *stream, FAR char *ptr, FAR size_t *nread,
size_t buflen, FAR int *terminator)
static ssize_t lib_copystring(FAR FILE *stream, FAR char *ptr,
FAR size_t *nread, size_t buflen,
FAR int *terminator)
{
size_t nwritten = 0;
int ch;
@ -191,7 +191,7 @@ static ssize_t lib_copystring(FAR FILE *stream, FAR char *ptr, FAR size_t *nread
* encountered
*/
for(;;)
for (; ; )
{
/* Read the next character from the file */
@ -214,6 +214,7 @@ static ssize_t lib_copystring(FAR FILE *stream, FAR char *ptr, FAR size_t *nread
*ptr++ = '\0';
/* Return EOF if nothing has written */
return nwritten == 0 ? 0 : nwritten + 1;
}

3
libs/libc/stdio/lib_libvscanf.c
View file

@ -156,7 +156,7 @@ static FAR const char *findscanset(FAR const char *fmt,
if (n == ']' || n < c)
{
c = '-';
break; /* Resume the for(;;) */
break; /* Resume the for (; ; ) */
}
fmt++;
@ -1210,3 +1210,4 @@ int lib_vscanf(FAR struct lib_instream_s *obj, FAR int *lastc,
*lastc = c;
return (count || !conv) ? assigncount : EOF;
}

15
tools/initialconfig.c
View file

@ -60,7 +60,8 @@
* Private Types
****************************************************************************/
typedef int (*direntcb_t)(const char *dirpath, struct dirent *entry, void *arg);
typedef int (*direntcb_t)(const char *dirpath, struct dirent *entry,
void *arg);
/****************************************************************************
* Private Data
@ -160,7 +161,7 @@ static char *read_line(FILE *stream)
{
char *ptr;
for (;;)
for (; ; )
{
g_line[MAX_LINE] = '\0';
if (!fgets(g_line, MAX_LINE, stream))
@ -415,7 +416,7 @@ static int foreach_dirent(const char *dirpath, direntcb_t cb, void *arg)
exit(EXIT_FAILURE);
}
for (;;)
for (; ; )
{
ret = readdir_r(dirp, &entry, &result);
if (ret != 0)
@ -458,7 +459,8 @@ static int foreach_dirent(const char *dirpath, direntcb_t cb, void *arg)
*
****************************************************************************/
static int enum_architectures(const char *dirpath, struct dirent *entry, void *arg)
static int enum_architectures(const char *dirpath, struct dirent *entry,
void *arg)
{
char *archpath;
char *testpath;
@ -689,7 +691,7 @@ char *list_select(char **list, unsigned nitems)
}
}
for(; ; )
for (; ; )
{
bool input = false;
@ -819,7 +821,8 @@ int main(int argc, char **argv)
/* Enumerate the MCUs for the selected architecture */
g_nmcu = 0;
asprintf(&archpath, "%s%c%s%csrc", g_archdir, g_delim, g_selected_arch, g_delim);
asprintf(&archpath, "%s%c%s%csrc",
g_archdir, g_delim, g_selected_arch, g_delim);
foreach_dirent(archpath, enum_mcus, NULL);
/* Select an MCU */

544
wireless/ieee802154/mac802154.c
View file

File diff suppressed because it is too large Load diff

129
wireless/ieee802154/mac802154_assoc.c
View file

@ -95,9 +95,9 @@ int mac802154_req_associate(MACHANDLE mac,
}
/* Get exlusive access to the operation sempaphore. This must happen before
* getting exclusive access to the MAC struct or else there could be a lockup
* condition. This would occur if another thread is using the cmdtrans but
* needs access to the MAC in order to unlock it.
* getting exclusive access to the MAC struct or else there could be a
* lockup condition. This would occur if another thread is using the
* cmdtrans but needs access to the MAC in order to unlock it.
*/
ret = mac802154_takesem(&priv->opsem, true);
@ -204,7 +204,7 @@ int mac802154_req_associate(MACHANDLE mac,
mac802154_puteaddr(iob, priv->pandesc.coordaddr.eaddr);
}
/* The Source PAN Identifier field shall contain the broadcast PAN identifier.*/
/* The Source PAN Identifier field shall contain the broadcast PAN identifier. */
mac802154_putsaddr(iob, &IEEE802154_SADDR_BCAST);
@ -235,22 +235,24 @@ int mac802154_req_associate(MACHANDLE mac,
txdesc->frame = iob;
txdesc->frametype = IEEE802154_FRAME_COMMAND;
/* Save a copy of the destination addressing infromation into the tx descriptor.
* We only do this for commands to help with handling their progession.
/* Save a copy of the destination addressing infromation into the tx
* descriptor. We only do this for commands to help with handling their
* progession.
*/
memcpy(&txdesc->destaddr, &req->coordaddr, sizeof(struct ieee802154_addr_s));
memcpy(&txdesc->destaddr, &req->coordaddr,
sizeof(struct ieee802154_addr_s));
/* Save a reference of the tx descriptor */
priv->cmd_desc = txdesc;
/* Search the list of PAN descriptors, that would have been populated by the
* latest scan procedure. If we have seen a beacon from the coordinator that
* we are about to associate with, we can check the beacon order to determine
* whether we can send the command during the CAP. If we haven't received
* a beacon frame from the desired coordinator address, we have to just
* send the frame out immediately.
/* Search the list of PAN descriptors, that would have been populated by
* the latest scan procedure. If we have seen a beacon from the
* coordinator that we are about to associate with, we can check the
* beacon order to determine whether we can send the command during the
* CAP. If we haven't received a beacon frame from the desired
* coordinator address, we have to just send the frame out immediately.
*/
for (i = 0; i < priv->npandesc; i++)
@ -364,14 +366,15 @@ int mac802154_resp_associate(MACHANDLE mac,
iob->io_data[iob->io_len++] = priv->dsn++;
/* In accordance with this value of the PAN ID Compression field, the
* Destination PAN Identifier field shall contain the value of macPANId, while
* the Source PAN Identifier field shall be omitted. [1] pg. 69
* Destination PAN Identifier field shall contain the value of macPANId,
* while the Source PAN Identifier field shall be omitted. [1] pg. 69
*/
mac802154_putpanid(iob, priv->addr.panid);
/* The Destination Address field shall contain the extended address of the
* device requesting association. [1] pg. 69 */
* device requesting association. [1] pg. 69
*/
mac802154_puteaddr(iob, resp->devaddr);
@ -455,7 +458,7 @@ void mac802154_txdone_assocreq(FAR struct ieee802154_privmac_s *priv,
FAR struct ieee802154_primitive_s *primitive =
(FAR struct ieee802154_primitive_s *)txdesc->conf;
if(txdesc->conf->status != IEEE802154_STATUS_SUCCESS)
if (txdesc->conf->status != IEEE802154_STATUS_SUCCESS)
{
/* if the association request command cannot be sent due to a
* channel access failure, the MAC sublayer shall notify the next
@ -479,8 +482,8 @@ void mac802154_txdone_assocreq(FAR struct ieee802154_privmac_s *priv,
* if the association attempt was unsuccessful. [1] pg. 81
*/
IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr, &IEEE802154_SADDR_UNSPEC);
IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr,
&IEEE802154_SADDR_UNSPEC);
/* We are now done the operation, unlock the semaphore */
@ -510,30 +513,32 @@ void mac802154_txdone_assocreq(FAR struct ieee802154_privmac_s *priv,
if (priv->sfspec.beaconorder < 15)
{
/* We are tracking the beacon, so we should see our address in the
* beacon frame within macResponseWaitTime if the coordinator is going
* to respond. Setup a timeout for macResponseWaitTime so that we
* can inform the next highest layer if the association attempt fails
* due to NO_DATA.
* beacon frame within macResponseWaitTime if the coordinator is
* going to respond. Setup a timeout for macResponseWaitTime so
* that we can inform the next highest layer if the association
* attempt fails due to NO_DATA.
*
* TODO: The standard defines macResponseWaitTime as:
* The maximum time, in multiples of aBaseSuperframeDuration, a device
* shall wait for a response command frame to be available following a
* request command frame.
* The maximum time, in multiples of aBaseSuperframeDuration, a
* device shall wait for a response command frame to be available
* following a request command frame.
*
* However, on beacon-enabled networks, it seems the maximum value
* isn't really that large of a value, AKA: assoc always fails from
* timeout even though everything is working as expected. The definition
* does say after we've sent a data request, which we, haven't sent
* yet, but we do need a timeout for association in general. Not sure
* what the correct answer is. For now, I am going to change the
* way macResponseWaitTime is used with beacon-enabled networks and
* make the timeout (BI * macResponseWaitTime) where BI is Beacon
* Interval = aBaseSuperframeDuration * 2^macBeaconOrder
* isn't really that large of a value, AKA: assoc always fails
* from timeout even though everything is working as expected.
* The definition does say after we've sent a data request, which
* we, haven't sent yet, but we do need a timeout for association
* in general. Not sure what the correct answer is. For now, I am
* going to change the way macResponseWaitTime is used with beacon-
* enabled networks and make the timeout (BI * macResponseWaitTime)
* where BI is Beacon Interval = aBaseSuperframeDuration *
* 2^macBeaconOrder
*/
wlinfo("Starting timeout timer\n");
mac802154_timerstart(priv, (priv->resp_waittime *
(IEEE802154_BASE_SUPERFRAME_DURATION * (1 << priv->sfspec.beaconorder))),
(IEEE802154_BASE_SUPERFRAME_DURATION *
(1 << priv->sfspec.beaconorder))),
mac802154_assoctimeout);
}
else
@ -543,7 +548,8 @@ void mac802154_txdone_assocreq(FAR struct ieee802154_privmac_s *priv,
* the mode to short or extended
*/
DEBUGASSERT(priv->pandesc.coordaddr.mode != IEEE802154_ADDRMODE_NONE);
DEBUGASSERT(priv->pandesc.coordaddr.mode !=
IEEE802154_ADDRMODE_NONE);
/* Send the Data Request MAC command after macResponseWaitTime to
* extract the data from the coordinator.
@ -621,7 +627,8 @@ void mac802154_txdone_datareq_assoc(FAR struct ieee802154_privmac_s *priv,
* if the association attempt was unsuccessful. [1] pg. 81
*/
IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr, &IEEE802154_SADDR_UNSPEC);
IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr,
&IEEE802154_SADDR_UNSPEC);
/* We are now done the operation, and can release the command */
@ -641,9 +648,9 @@ void mac802154_txdone_datareq_assoc(FAR struct ieee802154_privmac_s *priv,
mac802154_rxenable(priv);
/* If we are on a beacon-enabled network, we already have the association
* timeout timer scheduled. So we only need to start the timeout timer
* if we are operating on a non-beacon enabled network.
/* If we are on a beacon-enabled network, we already have the
* association timeout timer scheduled. So we only need to start the
* timeout timer if we are operating on a non-beacon enabled network.
*
* NOTE: This may create a bad side-effect where the receiver is on
* for longer than it needs to be during association. Revisit if power
@ -667,7 +674,6 @@ void mac802154_txdone_datareq_assoc(FAR struct ieee802154_privmac_s *priv,
/* Deallocate the data conf notification as it is no longer needed. */
ieee802154_primitive_free(primitive);
}
}
@ -721,7 +727,7 @@ void mac802154_rx_assocreq(FAR struct ieee802154_privmac_s *priv,
(cap >> IEEE802154_CAPABILITY_SHIFT_ALLOCADDR) & 0x01;
#ifdef CONFIG_IEEE802154_SECURITY
#error Missing security logic
# error Missing security logic
#endif
/* Get exclusive access to the MAC */
@ -749,21 +755,21 @@ void mac802154_rx_assocresp(FAR struct ieee802154_privmac_s *priv,
FAR struct iob_s *iob = ind->frame;
FAR struct ieee802154_primitive_s *primitive;
/* Check if we are performing an Association operation, if not, we will just
* ignore the frame.
/* Check if we are performing an Association operation, if not, we will
* just ignore the frame.
*/
if (priv->curr_op != MAC802154_OP_ASSOC)
{
/* This situation can occur in a beacon-enabled network if the association
* request has timed out, but the Coordinator has already queued the
* response. Which means the beacon would contain our address, causing us
* to extract the response.
/* This situation can occur in a beacon-enabled network if the
* association request has timed out, but the Coordinator has already
* queued the response. Which means the beacon would contain our
* address, causing us to extract the response.
*
* TODO: What is supposed to happen in this situation. Are we supposed to
* accept the request? Are we supposed to Disassociate with the network
* as a convienience to the PAN Coordinator. So that it does not need
* to waste space holding our information?
* TODO: What is supposed to happen in this situation. Are we supposed
* to accept the request? Are we supposed to Disassociate with the
* network as a convienience to the PAN Coordinator. So that it does
* not need to waste space holding our information?
*/
wlinfo("Ignoring association response frame\n");
@ -793,10 +799,10 @@ void mac802154_rx_assocresp(FAR struct ieee802154_privmac_s *priv,
priv->radio->setattr(priv->radio, IEEE802154_ATTR_MAC_SADDR,
(FAR union ieee802154_attr_u *)priv->addr.saddr);
/* A Short Address field value equal to 0xfffe shall indicate that the device
* has been successfully associated with a PAN but has not been allocated a
* short address. In this case, the device shall communicate on the PAN using
* only its extended address. [1] pg. 70
/* A Short Address field value equal to 0xfffe shall indicate that the
* device has been successfully associated with a PAN but has not been
* allocated a short address. In this case, the device shall communicate
* on the PAN using only its extended address. [1] pg. 70
*/
if (IEEE802154_SADDRCMP(priv->addr.saddr, &IEEE802154_SADDR_BCAST))
@ -842,14 +848,16 @@ void mac802154_rx_assocresp(FAR struct ieee802154_privmac_s *priv,
* Name: mac802154_assoctimeout
*
* Description:
* Function registered with MAC timer that gets called via the work queue to
* handle a timeout for extracting the Association Response from the Coordinator.
* Function registered with MAC timer that gets called via the work queue
* to handle a timeout for extracting the Association Response from the
* Coordinator.
*
****************************************************************************/
static void mac802154_assoctimeout(FAR void *arg)
{
FAR struct ieee802154_privmac_s *priv = (FAR struct ieee802154_privmac_s *)arg;
FAR struct ieee802154_privmac_s *priv =
(FAR struct ieee802154_privmac_s *)arg;
FAR struct ieee802154_primitive_s *primitive;
/* If there is work scheduled for the rxframe_worker, we want to reschedule
@ -880,7 +888,8 @@ static void mac802154_assoctimeout(FAR void *arg)
primitive->type = IEEE802154_PRIMITIVE_CONF_ASSOC;
primitive->u.assocconf.status = IEEE802154_STATUS_NO_DATA;
IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr, &IEEE802154_SADDR_UNSPEC);
IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr,
&IEEE802154_SADDR_UNSPEC);
/* We are no longer performing the association operation */

22
wireless/ieee802154/mac802154_rxenable.c
View file

@ -70,15 +70,17 @@ static void mac802154_rxenabletimeout(FAR void *arg);
*
* Description:
* Function registered with MAC timer that gets called via the work queue to
* handle a timeout for extracting the Association Response from the Coordinator.
* handle a timeout for extracting the Association Response from the
* Coordinator.
*
****************************************************************************/
static void mac802154_rxenabletimeout(FAR void *arg)
{
FAR struct ieee802154_privmac_s *priv = (FAR struct ieee802154_privmac_s *)arg;
FAR struct ieee802154_privmac_s *priv =
(FAR struct ieee802154_privmac_s *)arg;
while(mac802154_lock(priv, true) != 0);
while (mac802154_lock(priv, true) != 0);
if (priv->curr_op != MAC802154_OP_RXENABLE)
{
@ -130,10 +132,11 @@ int mac802154_req_rxenable(MACHANDLE mac,
{
if (req->rxon_dur > 0)
{
/* Get exlusive access to the operation sempaphore. This must happen before
* getting exclusive access to the MAC struct or else there could be a lockup
* condition. This would occur if another thread is using the cmdtrans but
* needs access to the MAC in order to unlock it.
/* Get exlusive access to the operation sempaphore. This must
* happen before getting exclusive access to the MAC struct or
* else there could be a lockup condition. This would occur if
* another thread is using the cmdtrans but needs access to the
* MAC in order to unlock it.
*/
ret = mac802154_takesem(&priv->opsem, true);
@ -161,7 +164,8 @@ int mac802154_req_rxenable(MACHANDLE mac,
if (req->rxon_dur != 0xFFFFFFFF)
{
mac802154_timerstart(priv, req->rxon_dur, mac802154_rxenabletimeout);
mac802154_timerstart(priv, req->rxon_dur,
mac802154_rxenabletimeout);
}
}
else
@ -195,4 +199,4 @@ int mac802154_req_rxenable(MACHANDLE mac,
errout_with_sem:
mac802154_unlock(priv)
return ret;
}
}

21
wireless/ieee802154/mac802154_start.c
View file

@ -82,10 +82,11 @@ int mac802154_req_start(MACHANDLE mac, FAR struct ieee802154_start_req_s *req)
* attempts to transmit a coordinator realignment command frame as described
* in 5.1.2.3.2. If the transmission of the coordinator realignment command
* fails due to a channel access failure, the MLME will not make any changes
* to the superframe configuration. (i.e., no PIB attributes will be changed).
* If the coordinator realignment command is successfully transmitted, the
* MLME updates the PIB attributes BeaconOrder, SuperframeOrder, PANId,
* ChannelPage, and ChannelNumber parameters. [1] pg. 106
* to the superframe configuration. (i.e., no PIB attributes will be
* changed). If the coordinator realignment command is successfully
* transmitted, the MLME updates the PIB attributes BeaconOrder,
* SuperframeOrder, PANId, ChannelPage, and ChannelNumber parameters.
* [1] pg. 106
*/
if (req->coordrealign)
@ -122,7 +123,7 @@ int mac802154_req_start(MACHANDLE mac, FAR struct ieee802154_start_req_s *req)
/* Set the beacon order */
if(req->beaconorder > 15)
if (req->beaconorder > 15)
{
ret = -EINVAL;
goto errout;
@ -136,7 +137,7 @@ int mac802154_req_start(MACHANDLE mac, FAR struct ieee802154_start_req_s *req)
{
/* Set the superframe order */
if(req->superframeorder > 15)
if (req->superframeorder > 15)
{
ret = -EINVAL;
goto errout;
@ -158,10 +159,10 @@ int mac802154_req_start(MACHANDLE mac, FAR struct ieee802154_start_req_s *req)
if (priv->sfspec.beaconorder < 15)
{
/* If the BeaconOrder parameter is less than 15, the MLME sets macBattLifeExt to
* the value of the BatteryLifeExtension parameter. If the BeaconOrder parameter
* equals 15, the value of the BatteryLifeExtension parameter is ignored.
* [1] pg. 106
/* If the BeaconOrder parameter is less than 15, the MLME sets
* macBattLifeExt to the value of the BatteryLifeExtension parameter.
* If the BeaconOrder parameter equals 15, the value of the
* BatteryLifeExtension parameter is ignored. [1] pg. 106
*/
priv->sfspec.ble = req->battlifeext;