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imx95: eDMA5 Allow sharing with Linux

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Allows to offset channels and thus sharing the controller with A-core
This commit is contained in:
Peter van der Perk 2025-07-15 16:52:16 +02:00 • committed by Xiang Xiao
parent 3ff603fc52
commit def76c90d5
3 changed files with 34 additions and 3 deletions
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20
arch/arm/src/imx9/Kconfig
View file

@ -652,6 +652,26 @@ config IMX9_EDMA_NTCD
which case only the TCD channel registers will be used and scatter- which case only the TCD channel registers will be used and scatter-
will not be supported. will not be supported.
config IMX9_EDMA5_CHAN_OFFSET
int "Offset of 1st EDMA5 channel"
default 30
depends on ARCH_CHIP_IMX95_M7
---help---
The EDMA5 controller on the i.MX95 can be accessed by multiple cores.
However, TCD (Transfer Control Descriptor) mappings are not shareable
between instances. Instead, each instance must specify its usable TCD
channels using an offset and count to define a dedicated range.
config IMX9_EDMA5_CHAN_COUNT
int "Number of EDMA5 channels"
default 34
depends on ARCH_CHIP_IMX95_M7
---help---
The EDMA5 controller on the i.MX95 can be accessed by multiple cores.
However, TCD (Transfer Control Descriptor) mappings are not shareable
between instances. Instead, each instance must specify its usable TCD
channels using an offset and count to define a dedicated range.
config IMX9_EDMA_ELINK config IMX9_EDMA_ELINK
bool "Channeling Linking" bool "Channeling Linking"
default n default n

14
arch/arm/src/imx9/hardware/imx95/imx95_edma.h
View file

@ -345,8 +345,18 @@
/* Amount of channels */ /* Amount of channels */
#define DMA3_CHANNEL_COUNT (31) #define DMA3_CHANNEL_COUNT (31)
#define DMA4_CHANNEL_COUNT (64) #ifdef IMX9_DMA4_BASE
#define IMX9_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT) # define DMA4_CHANNEL_COUNT (64)
#else
# define DMA4_CHANNEL_COUNT (0)
#endif
#ifdef IMX9_EDMA5_2_BASE
#define DMA5_CHANNEL_COUNT (64 - CONFIG_IMX9_EDMA5_CHAN_COUNT)
#else
# define DMA5_CHANNEL_COUNT (0)
#endif
#define IMX9_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT + DMA5_CHANNEL_COUNT)
/* Amount of interrupt sources */ /* Amount of interrupt sources */
#ifdef CONFIG_ARCH_CHIP_IMX95_M7 #ifdef CONFIG_ARCH_CHIP_IMX95_M7

3
arch/arm/src/imx9/imx9_edma.c
View file

@ -909,7 +909,8 @@ void weak_function arm_dma_initialize(void)
/* Initialize the channel */ /* Initialize the channel */
for (i = 0; i < DMA4_CHANNEL_COUNT; i++, dmach++) for (i = CONFIG_IMX9_EDMA5_CHAN_OFFSET;
i < CONFIG_IMX9_EDMA5_CHAN_COUNT; i++, dmach++)
{ {
dmach->base = IMX9_EDMA5_2_BASE; dmach->base = IMX9_EDMA5_2_BASE;
dmach->chan = i; dmach->chan = i;