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arch/arm: Move FPU initialization to common place

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2022-04-12 03:18:46 +08:00 • committed by Petro Karashchenko
parent 7660b3b1c4
commit df5a8a53ae
57 changed files with 290 additions and 2368 deletions
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3
arch/arm/src/a1x/a1x_boot.c
View file

@ -34,7 +34,6 @@
#include "chip.h"
#include "arm.h"
#include "mmu.h"
#include "fpu.h"
#include "arm_internal.h"
#include "a1x_lowputc.h"
#include "a1x_boot.h"
@ -300,11 +299,9 @@ void arm_boot(void)
a1x_copyvectorblock();
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
#endif
#ifdef CONFIG_BOOT_SDRAM_DATA
/* This setting is inappropriate for the A1x because the code is *always*

3
arch/arm/src/am335x/am335x_boot.c
View file

@ -38,7 +38,6 @@
#include "chip.h"
#include "arm.h"
#include "mmu.h"
#include "fpu.h"
#include "arm_internal.h"
#include "am335x_clockconfig.h"
#include "am335x_wdog.h"
@ -402,11 +401,9 @@ void arm_boot(void)
am335x_clockconfig();
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
#endif
/* Disable CPU Watchdog */

77
arch/arm/src/armv7-a/fpu.h
View file

@ -1,77 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-a/fpu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_A_FPU_H
#define __ARCH_ARM_SRC_ARMV7_A_FPU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: arm_fpuconfig
*
* Description:
* Configure the FPU. Enables access to CP10 and CP11
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
void arm_fpuconfig(void);
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7_A_FPU_H */

117
arch/arm/src/armv7-m/arm_fpuconfig.c Normal file
View file

@ -0,0 +1,117 @@
/****************************************************************************
* arch/arm/src/armv7-m/arm_fpuconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "nvic.h"
#include "arm_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
*
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifndef CONFIG_ARMV7M_LAZYFPU
void arm_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
void arm_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif

77
arch/arm/src/armv7-r/fpu.h
View file

@ -1,77 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-r/fpu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_R_FPU_H
#define __ARCH_ARM_SRC_ARMV7_R_FPU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: arm_fpuconfig
*
* Description:
* Configure the FPU. Enables access to CP10 and CP11
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
void arm_fpuconfig(void);
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7_R_FPU_H */

117
arch/arm/src/armv8-m/arm_fpuconfig.c Normal file
View file

@ -0,0 +1,117 @@
/****************************************************************************
* arch/arm/src/armv8-m/arm_fpuconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "nvic.h"
#include "arm_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
*
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifndef CONFIG_ARMV8M_LAZYFPU
void arm_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
void arm_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif

2
arch/arm/src/common/arm_internal.h
View file

@ -440,9 +440,11 @@ void arm_vectorfiq(void);
/* Floating point unit ******************************************************/
#ifdef CONFIG_ARCH_FPU
void arm_fpuconfig(void);
void arm_savefpu(uint32_t *regs);
void arm_restorefpu(const uint32_t *regs);
#else
# define arm_fpuconfig()
# define arm_savefpu(regs)
# define arm_restorefpu(regs)
#endif

1
arch/arm/src/cxd56xx/Make.defs
View file

@ -62,6 +62,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)

3
arch/arm/src/cxd56xx/cxd56_cpustart.c
View file

@ -73,7 +73,6 @@
volatile static spinlock_t g_appdsp_boot;
extern int arm_pause_handler(int irq, void *c, FAR void *arg);
extern void fpuconfig(void);
/****************************************************************************
* Private Functions
@ -104,7 +103,7 @@ static void appdsp_boot(void)
/* Setup FPU */
fpuconfig();
arm_fpuconfig();
/* Clear SW_INT for APP_DSP(cpu) */

93
arch/arm/src/cxd56xx/cxd56_start.c
View file

@ -110,97 +110,6 @@ extern uint32_t _vectors[];
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
# ifndef CONFIG_ARMV7M_LAZYFPU
void fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
# else
void fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
# endif
#else
# define fpuconfig()
#endif
/****************************************************************************
* Name: _start
*
@ -269,7 +178,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
fpuconfig();
arm_fpuconfig();
#ifdef CONFIG_ARMV7M_ITMSYSLOG
/* Perform ARMv7-M ITM SYSLOG initialization */

1
arch/arm/src/efm32/Make.defs
View file

@ -58,6 +58,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)

100
arch/arm/src/efm32/efm32_start.c
View file

@ -70,14 +70,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void efm32_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -102,96 +94,6 @@ static inline void efm32_fpuconfig(void);
# define showprogress(c)
#endif
/****************************************************************************
* Name: efm32_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void efm32_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void efm32_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define efm32_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -212,7 +114,7 @@ void __start(void)
/* Configure the uart so that we can get debug output as soon as possible */
efm32_clockconfig();
efm32_fpuconfig();
arm_fpuconfig();
efm32_lowsetup();
showprogress('A');

4
arch/arm/src/eoss3/Make.defs
View file

@ -56,6 +56,10 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
endif
CHIP_CSRCS = eoss3_start.c eoss3_gpio.c eoss3_lowputc.c eoss3_clockconfig.c
CHIP_CSRCS += eoss3_irq.c
CHIP_CSRCS += eoss3_serial.c

104
arch/arm/src/eoss3/eoss3_start.c
View file

@ -64,14 +64,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void eoss3_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -100,97 +92,6 @@ static inline void eoss3_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: eoss3_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void eoss3_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void eoss3_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define eoss3_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -219,10 +120,7 @@ void __start(void)
eoss3_clockconfig();
/* Unclear what needs to happen here to make RENODE happy. */
#if 1
eoss3_fpuconfig();
#endif
arm_fpuconfig();
eoss3_lowsetup();

3
arch/arm/src/imx6/imx_boot.c
View file

@ -39,7 +39,6 @@
#include "arm.h"
#include "mmu.h"
#include "scu.h"
#include "fpu.h"
#include "arm_internal.h"
#include "imx_config.h"
#include "imx_clockconfig.h"
@ -443,12 +442,10 @@ void arm_boot(void)
imx_clockconfig();
PROGRESS('I');
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
PROGRESS('J');
#endif
/* Perform board-specific memory initialization, This must include
* initialization of board-specific memory resources (e.g., SDRAM)

3
arch/arm/src/imx6/imx_cpuboot.c
View file

@ -35,7 +35,6 @@
#include "sctlr.h"
#include "smp.h"
#include "scu.h"
#include "fpu.h"
#include "gic.h"
#ifdef CONFIG_SMP
@ -247,11 +246,9 @@ void arm_cpu_boot(int cpu)
arm_enable_smp(cpu);
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
#endif
/* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */

1
arch/arm/src/imxrt/Make.defs
View file

@ -72,6 +72,7 @@ CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
# Required i.MX RT files

102
arch/arm/src/imxrt/imxrt_start.c
View file

@ -65,14 +65,6 @@
* here.
*/
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void imxrt_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -83,98 +75,6 @@ static inline void imxrt_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: imxrt_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
*
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void imxrt_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void imxrt_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define imxrt_fpuconfig()
#endif
/****************************************************************************
* Name: imxrt_tcmenable
*
@ -286,7 +186,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
imxrt_clockconfig();
imxrt_fpuconfig();
arm_fpuconfig();
imxrt_lowsetup();
/* Enable/disable tightly coupled memories */

1
arch/arm/src/kinetis/Make.defs
View file

@ -76,6 +76,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)

100
arch/arm/src/kinetis/kinetis_start.c
View file

@ -40,14 +40,6 @@
#include "kinetis_start.h"
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void kinetis_fpuconfig(void);
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -96,96 +88,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: kinetis_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void kinetis_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void kinetis_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define kinetis_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -258,7 +160,7 @@ void __start(void)
* configuration).
*/
kinetis_fpuconfig();
arm_fpuconfig();
kinetis_lowsetup();
#ifdef USE_EARLYSERIALINIT
kinetis_earlyserialinit();

1
arch/arm/src/lpc17xx_40xx/Make.defs
View file

@ -74,6 +74,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
# Required LPC17xx files

92
arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
View file

@ -86,96 +86,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
# define showprogress(c)
#endif
/****************************************************************************
* Name: lpc17_40_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void lpc17_40_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void lpc17_40_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define lpc17_40_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -213,7 +123,7 @@ void __start(void)
/* Configure the uart so that we can get debug output as soon as possible */
lpc17_40_clockconfig();
lpc17_40_fpuconfig();
arm_fpuconfig();
lpc17_40_lowsetup();
showprogress('A');

1
arch/arm/src/lpc43xx/Make.defs
View file

@ -62,6 +62,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
CHIP_CSRCS = lpc43_allocateheap.c lpc43_cgu.c lpc43_clrpend.c lpc43_gpio.c

95
arch/arm/src/lpc43xx/lpc43_start.c
View file

@ -83,7 +83,7 @@
#endif
/****************************************************************************
* Public Functions
* Private Functions
****************************************************************************/
/****************************************************************************
@ -153,97 +153,6 @@ static inline void lpc43_enabuffering(void)
# define lpc43_enabuffering()
#endif
/****************************************************************************
* Name: lpc43_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void lpc43_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void lpc43_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define lpc43_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -316,7 +225,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
lpc43_fpuconfig();
arm_fpuconfig();
showprogress('D');
/* Perform early serial initialization */

1
arch/arm/src/lpc54xx/Make.defs
View file

@ -62,6 +62,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c

93
arch/arm/src/lpc54xx/lpc54_start.c
View file

@ -80,97 +80,6 @@ static const struct pll_setup_s g_initial_pll_setup =
.ahbdiv = SYSCON_AHBCLKDIV_DIV(BOARD_AHBCLKDIV)
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: lpc54_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void lpc54_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void lpc54_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define lpc54_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -234,7 +143,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
lpc54_fpuconfig();
arm_fpuconfig();
showprogress('D');
/* Perform early serial initialization */

1
arch/arm/src/max326xx/Make.defs
View file

@ -60,6 +60,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
# Common MAX326XX Source Files

93
arch/arm/src/max326xx/common/max326_start.c
View file

@ -80,97 +80,6 @@
const uintptr_t g_idle_topstack = IDLE_STACK;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: max326_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void max326_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void max326_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define max326_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -239,7 +148,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
max326_fpuconfig();
arm_fpuconfig();
showprogress('E');
/* Perform early serial initialization */

1
arch/arm/src/nrf52/Make.defs
View file

@ -70,6 +70,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
CHIP_CSRCS = nrf52_start.c nrf52_clockconfig.c nrf52_irq.c nrf52_utils.c

89
arch/arm/src/nrf52/nrf52_start.c
View file

@ -71,93 +71,6 @@
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: nrf52_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void nrf52_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void nrf52_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define nrf52_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -227,7 +140,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
nrf52_fpuconfig();
arm_fpuconfig();
#ifdef CONFIG_NRF52_FLASH_PREFETCH
nrf_nvmc_enable_icache(true);

4
arch/arm/src/s32k1xx/Make.defs
View file

@ -38,6 +38,10 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_pthread_start.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
endif
# Source files common to all S32K1xx chip families.
CHIP_CSRCS = s32k1xx_start.c s32k1xx_lowputc.c s32k1xx_clockconfig.c

89
arch/arm/src/s32k1xx/s32k1xx_start.c
View file

@ -124,93 +124,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: s32k1xx_fpu_config
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void s32k1xx_fpu_config(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void s32k1xx_fpu_config(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define s32k1xx_fpu_config()
#endif
/****************************************************************************
* Name: s32k1xx_cache_config
*
@ -339,7 +252,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
s32k1xx_fpu_config();
arm_fpuconfig();
showprogress('C');
#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET)

1
arch/arm/src/sam34/Make.defs
View file

@ -66,6 +66,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)

96
arch/arm/src/sam34/sam_start.c
View file

@ -71,10 +71,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void sam_fpuconfig(void);
#endif
#ifdef CONFIG_ARMV7M_STACKCHECK
/* We need to get r10 set before we can allow instrumentation calls */
@ -99,96 +95,6 @@ void __start(void) noinstrument_function;
# define showprogress(c)
#endif
/****************************************************************************
* Name: sam_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void sam_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void sam_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define sam_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -257,7 +163,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
sam_clockconfig();
sam_fpuconfig();
arm_fpuconfig();
sam_lowsetup();
showprogress('A');

3
arch/arm/src/sama5/sam_boot.c
View file

@ -38,7 +38,6 @@
#include "chip.h"
#include "arm.h"
#include "mmu.h"
#include "fpu.h"
#include "arm_internal.h"
#include "hardware/sam_wdt.h"
#include "hardware/sam_aximx.h"
@ -445,11 +444,9 @@ void arm_boot(void)
sam_clockconfig();
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
#endif
/* Perform board-specific initialization, This must include:
*

1
arch/arm/src/samd5e5/Make.defs
View file

@ -56,6 +56,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)

92
arch/arm/src/samd5e5/sam_start.c
View file

@ -101,96 +101,6 @@ void __start(void) noinstrument_function;
# define showprogress(c)
#endif
/****************************************************************************
* Name: sam_fpu_configure
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void sam_fpu_configure(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void sam_fpu_configure(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define sam_fpu_configure()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -258,7 +168,7 @@ void __start(void)
*/
sam_clock_initialize();
sam_fpu_configure();
arm_fpuconfig();
sam_lowsetup();
showprogress('A');

1
arch/arm/src/samv7/Make.defs
View file

@ -61,6 +61,7 @@ CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)

100
arch/arm/src/samv7/sam_start.c
View file

@ -78,14 +78,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void sam_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -96,96 +88,6 @@ static inline void sam_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: sam_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void sam_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void sam_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define sam_fpuconfig()
#endif
/****************************************************************************
* Name: sam_tcmenable
*
@ -296,7 +198,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
sam_clockconfig();
sam_fpuconfig();
arm_fpuconfig();
sam_gpioinit();
sam_lowsetup();

1
arch/arm/src/stm32/Make.defs
View file

@ -70,6 +70,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)

100
arch/arm/src/stm32/stm32_start.c
View file

@ -67,14 +67,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void stm32_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -103,96 +95,6 @@ static inline void stm32_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: stm32_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define stm32_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -224,7 +126,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32_clockconfig();
stm32_fpuconfig();
arm_fpuconfig();
stm32_lowsetup();
stm32_gpioinit();
showprogress('A');

1
arch/arm/src/stm32f7/Make.defs
View file

@ -61,6 +61,7 @@ CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)

100
arch/arm/src/stm32f7/stm32_start.c
View file

@ -79,14 +79,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void stm32_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -97,96 +89,6 @@ static inline void stm32_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: stm32_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define stm32_fpuconfig()
#endif
/****************************************************************************
* Name: stm32_tcmenable
*
@ -302,7 +204,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32_clockconfig();
stm32_fpuconfig();
arm_fpuconfig();
stm32_lowsetup();
/* Enable/disable tightly coupled memories */

2
arch/arm/src/stm32h7/Make.defs
View file

@ -58,8 +58,10 @@ endif
CMN_CSRCS += arm_vectors.c
CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)

96
arch/arm/src/stm32h7/stm32_start.c
View file

@ -84,10 +84,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void stm32_fpuconfig(void);
#endif
/****************************************************************************
* Name: showprogress
*
@ -112,96 +108,6 @@ static inline void stm32_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: stm32_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define stm32_fpuconfig()
#endif
/****************************************************************************
* Name: stm32_tcmenable
*
@ -317,7 +223,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32_clockconfig();
stm32_fpuconfig();
arm_fpuconfig();
stm32_lowsetup();
showprogress('A');

1
arch/arm/src/stm32l4/Make.defs
View file

@ -55,6 +55,7 @@ CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)

100
arch/arm/src/stm32l4/stm32l4_start.c
View file

@ -75,14 +75,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void stm32l4_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -111,96 +103,6 @@ static inline void stm32l4_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: stm32l4_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void stm32l4_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void stm32l4_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define stm32l4_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -246,7 +148,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32l4_clockconfig();
stm32l4_fpuconfig();
arm_fpuconfig();
stm32l4_lowsetup();
stm32l4_gpioinit();
showprogress('A');

1
arch/arm/src/stm32l5/Make.defs
View file

@ -60,6 +60,7 @@ CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)

101
arch/arm/src/stm32l5/stm32l5_start.c
View file

@ -77,14 +77,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void stm32l5_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -113,97 +105,6 @@ static inline void stm32l5_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: stm32l5_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV8M_LAZYFPU
static inline void stm32l5_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void stm32l5_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define stm32l5_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -249,7 +150,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32l5_clockconfig();
stm32l5_fpuconfig();
arm_fpuconfig();
stm32l5_lowsetup();
stm32l5_gpioinit();
showprogress('A');

1
arch/arm/src/stm32u5/Make.defs
View file

@ -60,6 +60,7 @@ CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)

101
arch/arm/src/stm32u5/stm32_start.c
View file

@ -77,14 +77,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void stm32_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -113,97 +105,6 @@ static inline void stm32_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: stm32_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV8M_LAZYFPU
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define stm32_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -249,7 +150,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32_clockconfig();
stm32_fpuconfig();
arm_fpuconfig();
stm32_lowsetup();
stm32_gpioinit();
showprogress('A');

1
arch/arm/src/tiva/Make.defs
View file

@ -49,6 +49,7 @@ CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)

93
arch/arm/src/tiva/cc13xx/cc13xx_start.c
View file

@ -96,97 +96,6 @@ void cc13xx_trim_device(void);
# define showprogress(c)
#endif
/****************************************************************************
* Name: tiva_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void tiva_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void tiva_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define tiva_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -231,7 +140,7 @@ void __start(void)
*/
tiva_lowsetup();
tiva_fpuconfig();
arm_fpuconfig();
showprogress('A');
#ifdef CONFIG_BOOT_RUNFROMFLASH

93
arch/arm/src/tiva/common/lmxx_tm4c_start.c
View file

@ -87,97 +87,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
# define showprogress(c)
#endif
/****************************************************************************
* Name: tiva_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void tiva_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void tiva_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define tiva_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -201,7 +110,7 @@ void __start(void)
tiva_clock_configure();
tiva_lowsetup();
tiva_fpuconfig();
arm_fpuconfig();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be

3
arch/arm/src/tms570/tms570_boot.c
View file

@ -54,7 +54,6 @@
#include "chip.h"
#include "arm.h"
#include "fpu.h"
#include "sctlr.h"
#include "arm_internal.h"
@ -375,11 +374,9 @@ void arm_boot(void)
tms570_esm_initialize();
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
#endif
#ifdef CONFIG_ARMV7R_MEMINIT
/* Initialize the .bss and .data sections as well as RAM functions

1
arch/arm/src/xmc4/Make.defs
View file

@ -75,6 +75,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)

96
arch/arm/src/xmc4/xmc4_start.c
View file

@ -44,9 +44,6 @@
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void xmc4_fpu_config(void);
#endif
static inline void xmc4_unaligned(void);
static inline void xmc4_flash_waitstates(void);
@ -119,97 +116,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: xmc4_fpu_config
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void xmc4_fpu_config(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void xmc4_fpu_config(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define xmc4_fpu_config()
#endif
/****************************************************************************
* Name: xmc4_unaligned
*
@ -330,7 +236,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
xmc4_fpu_config();
arm_fpuconfig();
showprogress('B');
#ifdef USE_EARLYSERIALINIT