From e9617583bc089aa080e3940b7604b1c6bdb5a555 Mon Sep 17 00:00:00 2001 From: ligd Date: Mon, 25 Mar 2024 13:29:46 +0800 Subject: [PATCH] arm64-r/mpu: add TBI setting to r82 when use SW_TAG Signed-off-by: ligd --- arch/arm64/src/common/arm64_mpu.c | 6 ++++++ arch/arm64/src/common/arm64_mpu.h | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/src/common/arm64_mpu.c b/arch/arm64/src/common/arm64_mpu.c index db2920d3eb..075ca2e7fe 100644 --- a/arch/arm64/src/common/arm64_mpu.c +++ b/arch/arm64/src/common/arm64_mpu.c @@ -387,6 +387,12 @@ void arm64_mpu_init(bool is_primary_core) uint64_t val; uint32_t r_index; +#ifdef CONFIG_MM_KASAN_SW_TAGS + val = read_sysreg(tcr_el1); + val |= (TCR_TBI0 | TCR_TBI1 | TCR_ASID_8); + write_sysreg(val, tcr_el1); +#endif + /* Current MPU code supports only EL1 */ __asm__ volatile ("mrs %0, CurrentEL" : "=r" (val)); diff --git a/arch/arm64/src/common/arm64_mpu.h b/arch/arm64/src/common/arm64_mpu.h index 76857c2d60..6f6373b96e 100644 --- a/arch/arm64/src/common/arm64_mpu.h +++ b/arch/arm64/src/common/arm64_mpu.h @@ -50,6 +50,14 @@ #define MPU_RBAR_AP_POS 2U #define MPU_RBAR_AP_MSK (0x3UL << MPU_RBAR_AP_POS) +/* TCR_EL1 */ + +#define TCR_AS_SHIFT 36U +#define TCR_ASID_8 (0ULL << TCR_AS_SHIFT) +#define TCR_ASID_16 (1ULL << TCR_AS_SHIFT) +#define TCR_TBI0 (1ULL << 37) +#define TCR_TBI1 (1ULL << 38) + /* RBAR_EL1 XN */ #define MPU_RBAR_XN_POS 1U