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arm: armv7-a/r and armv8-r up_cpu_index inline

Browse source 
reason:
inline small code to improve performance

Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5 2024-03-25 10:18:44 +08:00 • committed by Xiang Xiao
parent da6ddea8d4
commit ea181e2621
18 changed files with 270 additions and 239 deletions
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23
arch/arm/include/arm/irq.h
View file

@ -219,6 +219,29 @@ static inline irqstate_t up_irq_enable(void)
: "cc", "memory");
return flags;
}
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void) noinstrument_function;
#else
# define up_cpu_index() 0
#endif /* CONFIG_SMP */
#endif /* __ASSEMBLY__ */
/****************************************************************************

22
arch/arm/include/armv6-m/irq.h
View file

@ -331,6 +331,28 @@ static inline void setcontrol(uint32_t control)
: "memory");
}
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void) noinstrument_function;
#else
# define up_cpu_index() 0
#endif /* CONFIG_SMP */
static inline_function uint32_t up_getsp(void)
{
register uint32_t sp;

52
arch/arm/include/armv7-a/irq.h
View file

@ -198,6 +198,20 @@
#define REG_PIC REG_R10
/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */
#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */
#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT)
/* Bits 2-7: Reserved */
#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */
#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT)
/* Bits 12-29: Reserved */
#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */
/****************************************************************************
* Public Types
****************************************************************************/
@ -425,6 +439,44 @@ noinstrument_function static inline void up_irq_restore(irqstate_t flags)
);
}
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
noinstrument_function
static inline_function int up_cpu_index(void)
{
unsigned int mpidr;
/* Read the Multiprocessor Affinity Register (MPIDR) */
__asm__ __volatile__
(
"mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
: "=r"(mpidr)
);
/* And return the CPU ID field */
return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT;
}
#else
# define up_cpu_index() 0
#endif /* CONFIG_SMP */
static inline_function uint32_t up_getsp(void)
{
register uint32_t sp;

22
arch/arm/include/armv7-m/irq.h
View file

@ -536,6 +536,28 @@ static inline void setcontrol(uint32_t control)
: "memory");
}
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void) noinstrument_function;
#else
# define up_cpu_index() 0
#endif /* CONFIG_SMP */
static inline_function uint32_t up_getsp(void)
{
register uint32_t sp;

52
arch/arm/include/armv7-r/irq.h
View file

@ -198,6 +198,20 @@
#define REG_PIC REG_R10
/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */
#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */
#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT)
/* Bits 2-7: Reserved */
#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */
#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT)
/* Bits 12-29: Reserved */
#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */
/****************************************************************************
* Public Types
****************************************************************************/
@ -420,6 +434,44 @@ static inline void up_irq_restore(irqstate_t flags)
);
}
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
noinstrument_function
static inline_function int up_cpu_index(void)
{
uint32_t mpidr;
/* Read the Multiprocessor Affinity Register (MPIDR) */
__asm__ __volatile__
(
"mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
: "=r"(mpidr)
);
/* And return the CPU ID field */
return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT;
}
#else
# define up_cpu_index() 0
#endif /* CONFIG_SMP */
static inline_function uint32_t up_getsp(void)
{
register uint32_t sp;

22
arch/arm/include/armv8-m/irq.h
View file

@ -509,6 +509,28 @@ static inline void setcontrol(uint32_t control)
: "memory");
}
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void) noinstrument_function;
#else
# define up_cpu_index() 0
#endif /* CONFIG_SMP */
static inline_function uint32_t up_getsp(void)
{
uint32_t sp;

52
arch/arm/include/armv8-r/irq.h
View file

@ -198,6 +198,20 @@
#define REG_PIC REG_R10
/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */
#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */
#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT)
/* Bits 2-7: Reserved */
#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */
#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT)
/* Bits 12-29: Reserved */
#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */
/****************************************************************************
* Public Types
****************************************************************************/
@ -420,6 +434,44 @@ static inline void up_irq_restore(irqstate_t flags)
);
}
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
noinstrument_function
static inline_function int up_cpu_index(void)
{
uint32_t mpidr;
/* Read the Multiprocessor Affinity Register (MPIDR) */
__asm__ __volatile__
(
"mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
: "=r"(mpidr)
);
/* And return the CPU ID field */
return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT;
}
#else
# define up_cpu_index() 0
#endif /* CONFIG_SMP */
static inline_function uint32_t up_getsp(void)
{
register uint32_t sp;

22
arch/arm/include/irq.h
View file

@ -105,28 +105,6 @@ EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void) noinstrument_function;
#else
# define up_cpu_index() (0)
#endif
/****************************************************************************
* Inline functions
****************************************************************************/

22
arch/arm/include/tlsr82/irq.h
View file

@ -236,6 +236,28 @@ static inline uint32_t getcontrol(void)
return 0;
}
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void) noinstrument_function;
#else
# define up_cpu_index() 0
#endif /* CONFIG_SMP */
static inline_function uint32_t up_getsp(void)
{
register uint32_t sp;

9
arch/arm/src/armv7-a/CMakeLists.txt
View file

@ -105,14 +105,7 @@ if(CONFIG_ARCH_FPU)
endif()
if(CONFIG_SMP)
list(
APPEND
SRCS
arm_cpuindex.c
arm_cpustart.c
arm_cpupause.c
arm_cpuidlestack.c
arm_scu.c)
list(APPEND SRCS arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c arm_scu.c)
endif()
if(CONFIG_ARCH_HAVE_PSCI)

2
arch/arm/src/armv7-a/Make.defs
View file

@ -90,7 +90,7 @@ ifeq ($(CONFIG_ARCH_FPU),y)
endif
ifeq ($(CONFIG_SMP),y)
CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
CMN_CSRCS += arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
CMN_CSRCS += arm_scu.c
endif

71
arch/arm/src/armv7-a/arm_cpuindex.c
View file

@ -1,71 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_cpuindex.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/arch.h>
#include "cp15.h"
#include "sctlr.h"
#ifdef CONFIG_SMP
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* If TLS is enabled, then the RTOS can get this information from the TLS
* info structure. Otherwise, the MCU-specific logic must provide some
* mechanism to provide the CPU index.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
int up_cpu_index(void)
{
/* Read the Multiprocessor Affinity Register (MPIDR) */
uint32_t mpidr = cp15_rdmpidr();
/* And return the CPU ID field */
return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT;
}
#endif /* CONFIG_SMP */

22
arch/arm/src/armv7-a/sctlr.h
View file

@ -62,20 +62,6 @@
* Tightly CoupledMemory (TCM), so this register always Reads-As-Zero (RAZ).
*/
/* Multiprocessor Affinity Register (MPIDR) */
#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */
#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT)
/* Bits 2-7: Reserved */
#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */
#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT)
/* Bits 12-29: Reserved */
#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */
/* Processor Feature Register 0 (ID_PFR0) */
/* TODO: To be provided */
@ -461,14 +447,6 @@ static inline unsigned int cp15_rdid(void)
return CP15_GET(MIDR);
}
/* Get the Multiprocessor Affinity Register (MPIDR) */
noinstrument_function
static inline unsigned int cp15_rdmpidr(void)
{
return CP15_GET(MPIDR);
}
/* Read/write the system control register (SCTLR) */
static inline unsigned int cp15_rdsctlr(void)

1
arch/arm/src/armv7-r/CMakeLists.txt
View file

@ -70,7 +70,6 @@ if(CONFIG_SMP)
APPEND
SRCS
arm_cpuhead.S
arm_cpuindex.c
arm_cpustart.c
arm_cpupause.c
arm_cpuidlestack.c

2
arch/arm/src/armv7-r/Make.defs
View file

@ -59,6 +59,6 @@ endif
ifeq ($(CONFIG_SMP),y)
CMN_ASRCS += arm_cpuhead.S
CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c
CMN_CSRCS += arm_cpustart.c arm_cpupause.c
CMN_CSRCS += arm_cpuidlestack.c arm_scu.c
endif

71
arch/arm/src/armv7-r/arm_cpuindex.c
View file

@ -1,71 +0,0 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_cpuindex.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/arch.h>
#include "cp15.h"
#include "sctlr.h"
#ifdef CONFIG_SMP
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* If TLS is enabled, then the RTOS can get this information from the TLS
* info structure. Otherwise, the MCU-specific logic must provide some
* mechanism to provide the CPU index.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
int up_cpu_index(void)
{
/* Read the Multiprocessor Affinity Register (MPIDR) */
uint32_t mpidr = cp15_rdmpidr();
/* And return the CPU ID field */
return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT;
}
#endif /* CONFIG_SMP */

21
arch/arm/src/armv7-r/sctlr.h
View file

@ -61,20 +61,6 @@
* TODO: To be provided
*/
/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */
#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */
#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT)
/* Bits 2-7: Reserved */
#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */
#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT)
/* Bits 12-29: Reserved */
#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */
/* Revision ID Register (REVIDR): CRn=c0, opc1=0, CRm=c0, opc2=6
* TODO: To be provided
*/
@ -521,13 +507,6 @@ static inline unsigned int cp15_rdid(void)
return CP15_GET(MIDR);
}
/* Get the Multiprocessor Affinity Register (MPIDR) */
static inline unsigned int cp15_rdmpidr(void)
{
return CP15_GET(MPIDR);
}
/* Read/write the system control register (SCTLR) */
static inline unsigned int cp15_rdsctlr(void)

21
arch/arm/src/armv8-r/sctlr.h
View file

@ -61,20 +61,6 @@
* TODO: To be provided
*/
/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */
#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */
#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT)
# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT)
/* Bits 2-7: Reserved */
#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */
#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT)
/* Bits 12-29: Reserved */
#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */
/* Revision ID Register (REVIDR): CRn=c0, opc1=0, CRm=c0, opc2=6
* TODO: To be provided
*/
@ -521,13 +507,6 @@ static inline unsigned int cp15_rdid(void)
return CP15_GET(MIDR);
}
/* Get the Multiprocessor Affinity Register (MPIDR) */
static inline unsigned int cp15_rdmpidr(void)
{
return CP15_GET(MPIDR);
}
/* Read/write the system control register (SCTLR) */
static inline unsigned int cp15_rdsctlr(void)