STM32F7 and STM32H7 SDMMC internal pull up usage fixed
Code was flawed in that the Pins are defined with the
pullups in the definition. Since there are no alterntes pins
there is no way to remove them. So not enabling the CONFIG
pull up did nothing as did enabling them.
Code also ignored the use of D0 for ready detection causing
3X+ the chatter.
This is now a compile time feature as there was no reason for
it to be a run time. It wasted both flash and ram.
This commit is contained in:
David Sidrane
Gregory Nutt
parent
8dd4b27973
commit
eba8eec74b
2 changed files with 56 additions and 48 deletions
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@ -171,6 +171,18 @@
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# undef CONFIG_CONFIG_STM32F7_SDMMC_XFRDEBUG
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#endif
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#ifdef CONFIG_SDMMC1_SDIO_PULLUP
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# define SDMMC1_SDIO_PULL(g) (((g) & ~GPIO_PUPD_MASK) | GPIO_PULLUP)
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#else
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# define SDMMC1_SDIO_PULL(g) (((g) & ~GPIO_PUPD_MASK) | GPIO_FLOAT)
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#endif
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#ifdef CONFIG_SDMMC2_SDIO_PULLUP
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# define SDMMC2_SDIO_PULL(g) (((g) & ~GPIO_PUPD_MASK) | GPIO_PULLUP)
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#else
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# define SDMMC2_SDIO_PULL(g) (((g) & ~GPIO_PUPD_MASK) | GPIO_FLOAT)
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#endif
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/* Friendly CLKCR bit re-definitions ****************************************/
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#define STM32_CLKCR_RISINGEDGE (0)
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@ -423,7 +435,6 @@ struct stm32_dev_s
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/* Misc */
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uint32_t pullup; /* GPIO pull-up option */
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uint32_t blocksize; /* Current block size */
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};
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@ -640,7 +651,7 @@ struct stm32_dev_s g_sdmmcdev1 =
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.base = STM32_SDMMC1_BASE,
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.nirq = STM32_IRQ_SDMMC1,
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#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
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.d0_gpio = GPIO_SDMMC1_D0,
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.d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0),
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#endif
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#ifdef CONFIG_STM32F7_SDMMC1_DMAPRIO
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.dmapri = CONFIG_STM32F7_SDMMC1_DMAPRIO,
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@ -654,12 +665,6 @@ struct stm32_dev_s g_sdmmcdev1 =
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#endif
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.do_sdio_card = NULL,
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#endif
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#ifdef CONFIG_SDMMC1_SDIO_PULLUP
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.pullup = GPIO_PULLUP,
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#else
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.pullup = 0,
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#endif
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};
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#endif
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@ -708,7 +713,7 @@ struct stm32_dev_s g_sdmmcdev2 =
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.base = STM32_SDMMC2_BASE,
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.nirq = STM32_IRQ_SDMMC2,
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#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
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.d0_gpio = GPIO_SDMMC2_D0,
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.d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0),
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#endif
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#ifdef CONFIG_STM32F7_SDMMC2_DMAPRIO
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.dmapri = CONFIG_STM32F7_SDMMC2_DMAPRIO,
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@ -722,12 +727,6 @@ struct stm32_dev_s g_sdmmcdev2 =
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#endif
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.do_sdio_card = NULL,
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#endif
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#ifdef CONFIG_SDMMC2_SDIO_PULLUP
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.pullup = GPIO_PULLUP,
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#else
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.pullup = 0,
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#endif
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};
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#endif
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/* Register logging support */
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@ -899,8 +898,9 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
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waitmask &= ~SDIOWAIT_WRCOMPLETE;
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pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK);
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pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI);
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pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK | \
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GPIO_PUPD_MASK);
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pinset |= (GPIO_INPUT | GPIO_EXTI);
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/* Arm the SDMMC_D Ready and install Isr */
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@ -3425,14 +3425,14 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
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*/
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# ifndef CONFIG_SDIO_MUXBUS
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stm32_configgpio(GPIO_SDMMC1_D0 | priv->pullup);
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0));
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# ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY
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stm32_configgpio(GPIO_SDMMC1_D1 | priv->pullup);
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stm32_configgpio(GPIO_SDMMC1_D2 | priv->pullup);
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stm32_configgpio(GPIO_SDMMC1_D3 | priv->pullup);
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D1));
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D2));
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D3));
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# endif
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stm32_configgpio(GPIO_SDMMC1_CK);
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stm32_configgpio(GPIO_SDMMC1_CMD | priv->pullup);
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_CMD));
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# endif
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}
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else
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@ -3462,14 +3462,14 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
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*/
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# ifndef CONFIG_SDIO_MUXBUS
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stm32_configgpio(GPIO_SDMMC2_D0 | priv->pullup);
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0));
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# ifndef CONFIG_SDMMC2_WIDTH_D1_ONLY
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stm32_configgpio(GPIO_SDMMC2_D1 | priv->pullup);
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stm32_configgpio(GPIO_SDMMC2_D2 | priv->pullup);
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stm32_configgpio(GPIO_SDMMC2_D3 | priv->pullup);
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_D1));
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_D2));
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_D3));
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# endif
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stm32_configgpio(GPIO_SDMMC2_CK);
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stm32_configgpio(GPIO_SDMMC2_CMD | priv->pullup);
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_CMD));
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# endif
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}
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else
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@ -157,6 +157,18 @@
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# undef CONFIG_CONFIG_STM32H7_SDMMC_XFRDEBUG
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#endif
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#ifdef CONFIG_SDMMC1_SDIO_PULLUP
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# define SDMMC1_SDIO_PULL(g) (((g) & ~GPIO_PUPD_MASK) | GPIO_PULLUP)
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#else
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# define SDMMC1_SDIO_PULL(g) (((g) & ~GPIO_PUPD_MASK) | GPIO_FLOAT)
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#endif
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#ifdef CONFIG_SDMMC2_SDIO_PULLUP
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# define SDMMC2_SDIO_PULL(g) (((g) & ~GPIO_PUPD_MASK) | GPIO_PULLUP)
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#else
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# define SDMMC2_SDIO_PULL(g) (((g) & ~GPIO_PUPD_MASK) | GPIO_FLOAT)
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#endif
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/* Define the Hardware FIFO size */
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#define FIFO_SIZE_IN_BYTES 64
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@ -342,7 +354,6 @@ struct stm32_dev_s
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/* Misc */
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uint32_t pullup; /* GPIO pull-up option */
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uint32_t blocksize; /* Current block size */
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uint32_t receivecnt; /* Real count to receive */
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#if !defined(CONFIG_STM32H7_SDMMC_IDMA)
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@ -552,14 +563,11 @@ struct stm32_dev_s g_sdmmcdev1 =
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.base = STM32_SDMMC1_BASE,
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.nirq = STM32_IRQ_SDMMC1,
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#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
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.d0_gpio = GPIO_SDMMC1_D0,
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.d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0),
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#endif
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#if defined(HAVE_SDMMC_SDIO_MODE) && defined(CONFIG_SDMMC1_SDIO_MODE)
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.sdiomode = true,
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#endif
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#if defined(CONFIG_SDMMC1_SDIO_PULLUP)
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.pullup = GPIO_PULLUP,
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#endif
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};
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#endif
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#if defined(CONFIG_STM32H7_SDMMC2)
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@ -607,14 +615,11 @@ struct stm32_dev_s g_sdmmcdev2 =
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.base = STM32_SDMMC2_BASE,
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.nirq = STM32_IRQ_SDMMC2,
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#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
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.d0_gpio = GPIO_SDMMC2_D0,
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.d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0),
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#endif
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#if defined(HAVE_SDMMC_SDIO_MODE) && defined(CONFIG_SDMMC2_SDIO_MODE)
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.sdiomode = true,
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#endif
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#if defined(CONFIG_SDMMC2_SDIO_PULLUP)
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.pullup = GPIO_PULLUP,
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#endif
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};
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#endif
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/* Register logging support */
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@ -775,6 +780,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
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/* Save all of the data and set the new interrupt mask in one, atomic
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* operation.
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*/
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flags = enter_critical_section();
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#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
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@ -784,8 +790,9 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
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waitmask &= ~SDIOWAIT_WRCOMPLETE;
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pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK);
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pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI);
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pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK | \
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GPIO_PUPD_MASK);
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pinset |= (GPIO_INPUT | GPIO_EXTI);
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/* Arm the SDMMC_D Ready and install Isr */
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@ -1424,6 +1431,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv,
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* None
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*
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****************************************************************************/
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#if !defined(CONFIG_STM32H7_SDMMC_IDMA)
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static void stm32_sdmmc_fifo_monitor(FAR void *arg)
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{
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@ -3295,14 +3303,14 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
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*/
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# ifndef CONFIG_SDIO_MUXBUS
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stm32_configgpio(GPIO_SDMMC1_D0 | priv->pullup);
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0));
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# ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY
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stm32_configgpio(GPIO_SDMMC1_D1 | priv->pullup);
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stm32_configgpio(GPIO_SDMMC1_D2 | priv->pullup);
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stm32_configgpio(GPIO_SDMMC1_D3 | priv->pullup);
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D1));
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D2));
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D3));
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# endif
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stm32_configgpio(GPIO_SDMMC1_CK);
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stm32_configgpio(GPIO_SDMMC1_CMD | priv->pullup);
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stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_CMD));
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# endif
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}
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else
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@ -3328,14 +3336,14 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
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*/
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# ifndef CONFIG_SDIO_MUXBUS
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stm32_configgpio(GPIO_SDMMC2_D0 | priv->pullup);
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0));
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# ifndef CONFIG_SDMMC2_WIDTH_D1_ONLY
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stm32_configgpio(GPIO_SDMMC2_D1 | priv->pullup);
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stm32_configgpio(GPIO_SDMMC2_D2 | priv->pullup);
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stm32_configgpio(GPIO_SDMMC2_D3 | priv->pullup);
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_D1));
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_D2));
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_D3));
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# endif
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stm32_configgpio(GPIO_SDMMC2_CK);
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stm32_configgpio(GPIO_SDMMC2_CMD | priv->pullup);
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stm32_configgpio(SDMMC2_SDIO_PULL(GPIO_SDMMC2_CMD));
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# endif
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}
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else
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