From fa0e5da18e109da1a674a69b406f523f948fc980 Mon Sep 17 00:00:00 2001 From: Abdelatif Guettouche Date: Thu, 3 Mar 2022 19:44:58 +0100 Subject: [PATCH] xtensa/xtensa_user_handler.S: Store EXCCAUSE and EXCVADDR into the user frame. The user frame is passed them to xtensa_user that actually uses EXCVADDR. Signed-off-by: Abdelatif Guettouche --- arch/xtensa/src/common/xtensa_user_handler.S | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index fd04c6fbd7..9677ec7d12 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -219,6 +219,13 @@ _xtensa_user_handler: rsr a0, EXCSAVE_1 /* Save interruptee's a0 */ s32i a0, sp, (4 * REG_A0) + /* Save EXCCAUSE and EXCVADDR into the user frame */ + + rsr a0, EXCCAUSE + s32i a0, sp, (4 * REG_EXCCAUSE) + rsr a0, EXCVADDR + s32i a0, sp, (4 * REG_EXCVADDR) + /* Save rest of interrupt context. */ s32i a2, sp, (4 * REG_A2) @@ -227,8 +234,8 @@ _xtensa_user_handler: call0 _xtensa_context_save /* Save full register state */ /* Save current SP before (possibly) overwriting it, - * it's the register save area. - */ + * it's the register save area. + */ mov a12, sp @@ -238,13 +245,6 @@ _xtensa_user_handler: setintstack a13 a14 #endif - /* Save exc cause and vaddr into exception frame */ - - rsr a0, EXCCAUSE - s32i a0, sp, (4 * REG_EXCCAUSE) - rsr a0, EXCVADDR - s32i a0, sp, (4 * REG_EXCVADDR) - /* Set up PS for C, re-enable hi-pri interrupts, and clear EXCM. */ #ifdef __XTENSA_CALL0_ABI__