arch/arm/src/stm32h7: Fix Kconfig style
Remove spaces from Kconfig Add TABs Add comments Signed-off-by: simbit18 <simbit18@gmail.com>
This commit is contained in:
simbit18
Filipe do Ó Cavalcanti
parent
fc15bf87a2
commit
fafbbfe337
1 changed files with 29 additions and 29 deletions
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@ -587,7 +587,7 @@ config STM32H7_CORTEXM7_BOOTM4
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default y if STM32H7_CORTEXM4_ENABLED
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default n
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endif
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endif # ARCH_CHIP_STM32H7_CORTEXM7
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config STM32H7_CORTEXM7_FLASH_SIZE
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int "Flash reserved for M7 core"
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@ -605,7 +605,7 @@ config STM32H7_SHMEM_SRAM3
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depends on STM32H7_CORTEXM7_SHMEM
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default y
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endif
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endif # ARCH_STM32H7_DUALCORE
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config STM32_HAVE_OTA_PARTITION
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bool
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@ -1126,7 +1126,7 @@ config STM32H7_LPTIM5
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default n
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select STM32H7_LPTIM
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endmenu # STM32H7 Timer Selection
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endmenu # STM32H7 Low-power Timer Selection
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menu "STM32H7 U[S]ART Selection"
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@ -1322,7 +1322,7 @@ config STM32H7_OTGHS_USBDEV
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endchoice # "STM32H7 OTGHS role"
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endmenu
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endmenu # OTG Configuration
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menu "SPI Configuration"
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depends on STM32H7_SPI
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@ -1953,7 +1953,7 @@ config STM32H7_ADC3_DMA_BATCH
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By default, this value is 1, which means that data is transferred after
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each group conversion.
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endmenu
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endmenu # ADC Configuration
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menu "SD/MMC Configuration"
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depends on STM32H7_SDMMC
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@ -2209,7 +2209,7 @@ config STM32H7_QSPI_DMA
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---help---
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Use DMA to improve QSPI transfer performance.
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endchoice
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endchoice # Transfer technique
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choice
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prompt "Bank selection"
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@ -2227,7 +2227,7 @@ config STM32H7_QSPI_MODE_BANK2
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config STM32H7_QSPI_MODE_DUAL
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bool "Dual Bank"
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endchoice
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endchoice # Bank selection
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choice
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prompt "DMA Priority"
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@ -2263,7 +2263,7 @@ config STM32H7_QSPI_DMAPRIORITY_LOW
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---help---
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'Low' priority.
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endchoice
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endchoice # DMA Priority
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config STM32H7_QSPI_DMATHRESHOLD
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int "QSPI DMA threshold"
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@ -2292,7 +2292,7 @@ config STM32H7_QSPI_REGDEBUG
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Output detailed register-level QSPI device debug information.
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Requires also CONFIG_DEBUG_SPI_INFO.
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endmenu
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endmenu # QuadSPI Configuration
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config STM32H7_BYPASS_CLOCKCONFIG
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bool "Bypass clock configuration"
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@ -4317,7 +4317,7 @@ config STM32H7_TIM1_ADC3
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---help---
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Reserve TIM1 to trigger ADC3
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endchoice
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endchoice # Select ADC for use with TIM1
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config STM32H7_TIM2_ADC
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bool "TIM2 ADC"
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@ -4359,7 +4359,7 @@ config STM32H7_TIM2_ADC3
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---help---
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Reserve TIM2 to trigger ADC3
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endchoice
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endchoice # Select ADC for use with TIM2
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config STM32H7_TIM3_ADC
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bool "TIM3 ADC"
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@ -4401,7 +4401,7 @@ config STM32H7_TIM3_ADC3
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---help---
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Reserve TIM3 to trigger ADC3
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endchoice
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endchoice # Select ADC for use with TIM3
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config STM32H7_TIM4_ADC
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bool "TIM4 ADC"
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@ -4443,7 +4443,7 @@ config STM32H7_TIM4_ADC3
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---help---
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Reserve TIM4 to trigger ADC3
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endchoice
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endchoice # Select ADC for use with TIM4
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config STM32H7_TIM6_ADC
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bool "TIM6 ADC"
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@ -4485,7 +4485,7 @@ config STM32H7_TIM6_ADC3
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---help---
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Reserve TIM6 to trigger ADC3
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endchoice
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endchoice # Select ADC for use with TIM6
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config STM32H7_TIM8_ADC
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bool "TIM8 ADC"
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@ -4527,7 +4527,7 @@ config STM32H7_TIM8_ADC3
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---help---
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Reserve TIM8 to trigger ADC3
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endchoice
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endchoice # Select ADC for use with TIM8
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config STM32H7_TIM15_ADC
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bool "TIM15 ADC"
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@ -4569,7 +4569,7 @@ config STM32H7_TIM15_ADC3
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---help---
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Reserve TIM15 to trigger ADC3
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endchoice
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endchoice # Select ADC for use with TIM15
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config STM32H7_HAVE_ADC1_TIMER
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bool
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@ -5023,7 +5023,7 @@ endif # STM32H7_LPTIM3_CAP
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config STM32H7_LPTIM4_CAP
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bool "LPTIM4 Capture"
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default n
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select STM32H7_TIMX_CAP
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select STM32H7_TIMX_CAP
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depends on STM32H7_LPTIM4
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---help---
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Reserve low-power timer 4 for use by the capture driver.
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@ -5835,7 +5835,7 @@ config STM32H7_MII_EXTCLK
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---help---
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Clocking is provided by external logic.
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endchoice
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endchoice # MII clock configuration
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config STM32H7_AUTONEG
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bool "Use autonegotiation"
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@ -6212,7 +6212,7 @@ config STM32H7_LTDC_REGDEBUG
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Additionally, you have to select "Low-level LCD Debug Features"
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to enable the debug messages.
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endmenu
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endmenu # LTDC Configuration
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endif # STM32H7_LTDC
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@ -6236,7 +6236,7 @@ config STM32H7_TIM1_QEPSC
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This prescaler divides the number of recorded encoder pulses,
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limiting the count rate at the expense of resolution.
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endif
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endif # STM32H7_TIM1_QE
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config STM32H7_TIM2_QE
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bool "TIM2"
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@ -6254,7 +6254,7 @@ config STM32H7_TIM2_QEPSC
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This prescaler divides the number of recorded encoder pulses,
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limiting the count rate at the expense of resolution.
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endif
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endif # STM32H7_TIM2_QE
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config STM32H7_TIM3_QE
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bool "TIM3"
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@ -6272,7 +6272,7 @@ config STM32H7_TIM3_QEPSC
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This prescaler divides the number of recorded encoder pulses,
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limiting the count rate at the expense of resolution.
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endif
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endif # STM32H7_TIM3_QE
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config STM32H7_TIM4_QE
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bool "TIM4"
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@ -6290,7 +6290,7 @@ config STM32H7_TIM4_QEPSC
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This prescaler divides the number of recorded encoder pulses,
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limiting the count rate at the expense of resolution.
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endif
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endif # STM32H7_TIM4_QE
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config STM32H7_TIM5_QE
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bool "TIM5"
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@ -6308,7 +6308,7 @@ config STM32H7_TIM5_QEPSC
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This prescaler divides the number of recorded encoder pulses,
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limiting the count rate at the expense of resolution.
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endif
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endif # STM32H7_TIM5_QE
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config STM32H7_TIM8_QE
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bool "TIM8"
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@ -6326,7 +6326,7 @@ config STM32H7_TIM8_QEPSC
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This prescaler divides the number of recorded encoder pulses,
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limiting the count rate at the expense of resolution.
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endif
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endif # STM32H7_TIM8_QE
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config STM32H7_QENCODER_FILTER
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bool "Enable filtering on STM32 QEncoder input"
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@ -6358,7 +6358,7 @@ config STM32H7_QENCODER_SAMPLE_FDTS_16
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config STM32H7_QENCODER_SAMPLE_FDTS_32
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bool "fDTS/32"
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endchoice
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endchoice # Input channel sampling frequency
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choice
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depends on STM32H7_QENCODER_FILTER
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@ -6389,7 +6389,7 @@ config STM32H7_QENCODER_SAMPLE_EVENT_8
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depends on !STM32H7_QENCODER_SAMPLE_FDTS
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bool "8"
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endchoice
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endchoice # Input channel event count
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endmenu # QEncoder Driver
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@ -6477,7 +6477,7 @@ config STM32H7_FDCAN_LOOPBACK_EXTERNAL
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All transmitted frames are treated as received frames and processed
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accordingly.
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endchoice # CAN Loopback Mode
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endchoice # FDCAN Loopback Mode
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choice
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prompt "FDCAN WorkQueue Selection"
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@ -6495,7 +6495,7 @@ config STM32H7_FDCAN_HPWORK
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Use the high-priority (HP) work queue for reception and transmission
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of new frames and for processing of transmission timeouts.
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endchoice
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endchoice # FDCAN WorkQueue Selection
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endmenu # FDCAN Driver
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