From fdf4e40b6a5adce1e7d5f27f844c19cb2755052c Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Sat, 13 Jan 2018 08:34:58 -0600
Subject: [PATCH] configs/lpcxpresso-lpc54628:  Correct SRAM base address in
 all configurations.

---
 configs/lpcxpresso-lpc54628/fb/defconfig     | 2 +-
 configs/lpcxpresso-lpc54628/netnsh/defconfig | 2 +-
 configs/lpcxpresso-lpc54628/nsh/defconfig    | 2 +-
 configs/lpcxpresso-lpc54628/nxwm/defconfig   | 2 +-
 configs/lpcxpresso-lpc54628/scripts/flash.ld | 2 +-
 sched/init/os_start.c                        | 4 ++--
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/configs/lpcxpresso-lpc54628/fb/defconfig b/configs/lpcxpresso-lpc54628/fb/defconfig
index 2234418cfc..2dc326a079 100644
--- a/configs/lpcxpresso-lpc54628/fb/defconfig
+++ b/configs/lpcxpresso-lpc54628/fb/defconfig
@@ -64,7 +64,7 @@ CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
 CONFIG_PREALLOC_WDOGS=4
 CONFIG_RAM_SIZE=163840
-CONFIG_RAM_START=0x10000000
+CONFIG_RAM_START=0x20000000
 CONFIG_RAW_BINARY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_HPWORK=y
diff --git a/configs/lpcxpresso-lpc54628/netnsh/defconfig b/configs/lpcxpresso-lpc54628/netnsh/defconfig
index 89836e6010..b84ff13d81 100644
--- a/configs/lpcxpresso-lpc54628/netnsh/defconfig
+++ b/configs/lpcxpresso-lpc54628/netnsh/defconfig
@@ -55,7 +55,7 @@ CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
 CONFIG_PREALLOC_WDOGS=4
 CONFIG_RAM_SIZE=163840
-CONFIG_RAM_START=0x10000000
+CONFIG_RAM_START=0x20000000
 CONFIG_RAW_BINARY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_HPWORK=y
diff --git a/configs/lpcxpresso-lpc54628/nsh/defconfig b/configs/lpcxpresso-lpc54628/nsh/defconfig
index 70d2e78068..bdcaa769d3 100644
--- a/configs/lpcxpresso-lpc54628/nsh/defconfig
+++ b/configs/lpcxpresso-lpc54628/nsh/defconfig
@@ -42,7 +42,7 @@ CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
 CONFIG_PREALLOC_WDOGS=4
 CONFIG_RAM_SIZE=163840
-CONFIG_RAM_START=0x10000000
+CONFIG_RAM_START=0x20000000
 CONFIG_RAW_BINARY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_RTC_ALARM=y
diff --git a/configs/lpcxpresso-lpc54628/nxwm/defconfig b/configs/lpcxpresso-lpc54628/nxwm/defconfig
index 4c2f839ee1..5bc987dbb5 100644
--- a/configs/lpcxpresso-lpc54628/nxwm/defconfig
+++ b/configs/lpcxpresso-lpc54628/nxwm/defconfig
@@ -87,7 +87,7 @@ CONFIG_NXWM=y
 CONFIG_PREALLOC_TIMERS=4
 CONFIG_PREALLOC_WDOGS=8
 CONFIG_RAM_SIZE=163840
-CONFIG_RAM_START=0x10000000
+CONFIG_RAM_START=0x20000000
 CONFIG_RAW_BINARY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_HPWORK=y
diff --git a/configs/lpcxpresso-lpc54628/scripts/flash.ld b/configs/lpcxpresso-lpc54628/scripts/flash.ld
index fc09e2fffc..42a0396af8 100644
--- a/configs/lpcxpresso-lpc54628/scripts/flash.ld
+++ b/configs/lpcxpresso-lpc54628/scripts/flash.ld
@@ -33,7 +33,7 @@
  *
  ****************************************************************************/
 
-/* The LPC54628 on the LPCXPressio has 512Kb of FLASH at address 0x0000:0000.
+/* The LPC54628 on the LPCXPresso has 512Kb of FLASH at address 0x0000:0000.
  * The Main SRAM is comprised of up to a total 160 KB of contiguous, on-chip
  * static RAM memory beginning at address 0x2000:0000 (this is in addition
  * to SRAMX aso the total device SRAM can be up to 200 KB).
diff --git a/sched/init/os_start.c b/sched/init/os_start.c
index 80fc944956..93f5cf0f1e 100644
--- a/sched/init/os_start.c
+++ b/sched/init/os_start.c
@@ -229,7 +229,7 @@ struct pidhash_s g_pidhash[CONFIG_MAX_TASKS];
 /* This is a table of task lists.  This table is indexed by the task stat
  * enumeration type (tstate_t) and provides a pointer to the associated
  * static task list (if there is one) as well as a a set of attribute flags
- * indicating properities of the list, for example, if the list is an
+ * indicating properties of the list, for example, if the list is an
  * ordered list or not.
  */
 
@@ -311,7 +311,7 @@ uint8_t g_os_initstate;  /* See enum os_initstate_e */
 /****************************************************************************
  * Private Data
  ****************************************************************************/
-/* This is an arry of task control block (TCB) for the IDLE thread of each
+/* This is an array of task control block (TCB) for the IDLE thread of each
  * CPU.  For the non-SMP case, this is a a single TCB; For the SMP case,
  * there is one TCB per CPU.  NOTE: The system boots on CPU0 into the IDLE
  * task.  The IDLE task later starts the other CPUs and spawns the user