From ffab2dc6280d9b643d0a2ebcbf14fe8303f443ca Mon Sep 17 00:00:00 2001 From: Gustavo Henrique Nihei Date: Wed, 27 Apr 2022 09:42:42 -0300 Subject: [PATCH] risc-v: Restrict Fence instruction for chips that support S-mode Signed-off-by: Gustavo Henrique Nihei --- arch/risc-v/src/common/riscv_pmp.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/risc-v/src/common/riscv_pmp.c b/arch/risc-v/src/common/riscv_pmp.c index cf7dc028de..e9786aa9c4 100644 --- a/arch/risc-v/src/common/riscv_pmp.c +++ b/arch/risc-v/src/common/riscv_pmp.c @@ -600,9 +600,14 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr, # error "XLEN of risc-v not supported" # endif - /* fence is needed when page-based virtual memory is implemented */ +#ifdef CONFIG_ARCH_USE_S_MODE + /* Fence is needed when page-based virtual memory is implemented. + * If page-based virtual memory is not implemented, memory accesses check + * the PMP settings synchronously, so no SFENCE.VMA is needed. + */ __asm volatile("sfence.vma x0, x0" : : : "memory"); +#endif return OK; }