error: unpredictable STXR instruction, status is also a source
99 | "stxr %w0, %1, [%2] \n"
| ^
<inline asm>:5:10: note: instantiated into assembly here
5 | stxr w10, x10, [x9]
Using w0 to pass the result can cause the "status register is also a source" problem, resulting in unpredictable behavior.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
common/arm64_cache.c:305:38: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
This implements an interrupt-based SPI driver for the BCM2711 SPI
interfaces (excluding auxiliary SPI interfaces). Only tested on SPI0
since proprietary firmware does not initialize any other SPI interfaces,
and doing so will require reverse engineering.
This adds support for the i.MX9 ROMAPI, allowing boot in a more
device agnostic and portable manner. The ROMAPI "natively" allows to:
- Query the boot device for information.
- Copy data from the boot device to RAM.
An extra functionality was added to ROMAPI to calculate
offsets of sequential AHAB containers.
The AHAB functionality is built on top of raw ELE primitives and allows to:
- Authenticate a container image.
- Release the authenticated container.
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
So far NuttX has supported OP-TEE interfacing over
local and RPMsg sockets. This commit introduces support
for direct invocation of OP-TEE through arm SMCs. The
SMC transport is enabled through CONFIG_DEV_OPTEE_SMC.
This SMC implementation has been tested only with arm64,
OP-TEE rev 4.4.
Note that it does not support reverse direction RPCs,
i.e. from the Secure World to the Normal World to
something like optee supplicant. A basic RPC handling
skeleton is provided with implementation for some
basic functions (alloc/free mem, and foreign interrupts)
but no supplicant command handling.
(+one minor change s/parm/param in arch/arm64/include/syscall
to satisfy the spellchecker during PR)
Signed-off-by: George Poulios <gpoulios@census-labs.com>
This PR adds support for the Allwinner A527 Arm64 SoC.
This will be used by the upcoming port of NuttX for
PINE64 Yuzuki Avaota-A1 SBC.
Most of the code was derived from NuttX for
QEMU Arm64 Kernel Build qemu-armv8a:knsh.
The modified code is explained here:
https://lupyuen.github.io/articles/avaota#appendix-port-nuttx-to-avaota-a1
Modified Files in arch/arm64:
Kconfig: Added ARCH_CHIP_SUNXI for Allwinner 64-bit SoCs.
Added ARCH_CHIP_SUNXI_A527 for A527 SoC.
New Files in arch/arm64:
include/a527/chip.h: A527 Definitions
include/a527/irq.h: External Interrupts
src/a527/chip.h: Memory Map
src/a527/a527_boot.c, a527_boot.h: Startup Code
src/a527/a527_initialize.c: Power Management
src/a527/a527_lowputc.S: UART Output
src/a527/a527_serial.c: Serial Driver
src/a527/a527_textheap.c: Text Heap
src/a527/a527_timer.c: A527 Timer
src/a527/Kconfig: A527 Config
src/a527/Make.defs, CMakeLists.txt: Makefiles
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
Make sure the registers context size is aligned to 16bytes as required by armv8-a.
This issue has been reported earlier, thus make sense to make sure it won't happen in future.
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
zynq-mpsoc and zcu111 borad was broken by #15437, because #15437 changes
ARM64_CONTEXT_REGS from 36 to 37, resulting in the stack no longer being
16-byte aligned which appears to violate the ARMv8-A architecture's
requirement for 16-byte stack alignment. this commit changes ARM64_CONTEXT_REGS
to 38 to fix this issues.
The method is the same as the method of saving the current DAIF state of the thread
It will pave the way for the future implementation of hwasan's memory management
Allows each thread to independently control the mte switch function
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Inline & inline_function both used make confuze, let's modify all inline
in irq.h to inline_function, also clear the always_inline_funcion
declaration.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Includes a Mini-UART NSH console for the 4B, tested on the 4GB RAM
model. Part of an I2C driver which can only read, boiler-plate for a SPI
driver, and a GPIO driver with limited pins. Some tools are present for
automatically fetching the boot files and creating the `config.txt` file
based on selected Kconfig options.
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
reason:
up_set_current_regs initially had two functions:
1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to
a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).
Currently, we record the context in other ways, so the second function is obsolete. Therefore,
we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
time/lib_localtime.c: In function 'tz_lock':
time/lib_localtime.c:396:7: error: 'tpidr_el1' undeclared (first use in this function)
396 | if (up_interrupt_context() || (sched_idletask() && OSINIT_IDLELOOP()))
| ^~~~~~~~~~~~~~~~~~~~
Signed-off-by: ligd <liguiding1@xiaomi.com>
when we build mbedtls in vela with ghs compiler, the mbedtls need to
access __ARM_ARCH and __ARM_FEATURE_DSP, and to construct the inline asm
code based on these two macros.
With ghs compiler, these two macros are not defined, and will be
evaluated as 0 by default, and thus will using to wrong inline asm code,
in order to handle this issue, we need to add conversion between the ghs
and gcc with __ARM_ARCH, __ARM_FEATURE_DSP
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
If the core id needs to be included in the hardware register
calculation, up_cpu_index() should be used instead of this_cpu().
Signed-off-by: chao an <anchao@lixiang.com>
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
Since FPU is now always saved into the current process stack location
upon exception entry, there is no need to keep fpu_regs (or saved_fpu_regs)
in the TCB.
reason:
when a context switch occurs, up_switch_context is executed.
In order to reduce the time taken for context switching,
we inline the up_switch_context function.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
The VMSAv8-64 translation system has 4 page table levels in total, ranging
from 0-3. The address environment code assumes only 3 levels, from 1-3 but
this is wrong; the amount of levels _utilized_ depends on the configured
VA size CONFIG_ARM64_VA_BITS. With <= 39 bits 3 levels is enough, while
if the va range is larger, the 4th translation table level is taken into
use dynamically by shifting the base translation table level.
From arm64_mmu.c, where va_bits is the amount of va bits used in address
translations:
(va_bits <= 21) - base level 3
(22 <= va_bits <= 30) - base level 2
(31 <= va_bits <= 39) - base level 1
(40 <= va_bits <= 48) - base level 0
The base level is what is configured as the page directory root. This also
affects the performance of address translations i.e. if the VA range is
smaller, address translations are also faster as the page table walk is
shorter.
reason:
1 On different architectures, we can utilize more optimized strategies
to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.
code size
before
text data bss dec hex filename
262848 49985 63893 376726 5bf96 nuttx
after
text data bss dec hex filename
262844 49985 63893 376722 5bf92 nuttx
size change -4
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
There is a tiny possibility that when a process is started a trap is
taken which causes a context switch. This moves the kernel stack
unexpectedly and the task start logic no longer works.
Fix this by recording the initial context location, and use that to
trampoline into the user process with interrupts disabled. This ensures
the context stays intact AND the kernel stack is fully unwound before
the user process starts.
