Serg Podtynnyi
2e7f75f6e0
arch/risc-v/rp23xx-riscv: Add rp23xx RISC-V cores support (Hazard3)
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Chip name : rp23xx-rv
Board name : raspberrypi-pico-2-rv
Arch : risc-v
Changes from ARM rp23xx impl
- Linker script update
- ASM head start
- Update chip start
- New Hazard3 registers
- Remove rp23xx chip hw spinlocks/testset
- New irq handling (external IRQ interrupt Hazard3)
- New timerisr based on RISC-V std MTIME and alarm arch
- No SMP yet
- Tickless option
- Double size for idle, irq and main stacks
- Board reset via watchdog trigger
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-08-11 08:56:27 +08:00
Lars Kruse
3ce85ca54e
style: fix spelling in code comments and strings
2025-05-23 10:48:41 +08:00
raiden00pl
0ecaeb7efe
.codespellrc: ignore IST
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Ignore IST for codespell.
IST is the name of company but also register name used in x86
Signed-off-by: raiden00pl <raiden00@railab.me>
2025-05-17 12:16:54 +08:00
Theodore Karatapanis
0011f165ff
style: fix typos required by ci-cd
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- Added "infor" to .codespellrc ignore-words-list.
This term is used by NXP's ROMAPI naming conventions and is not a typo
in this context.
- This prevents CI/CD codespell checks from failing due to false positives.
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
2025-05-09 19:21:17 +08:00
Alan Carvalho de Assis
5acfb995e0
codespell: Add RCALL
2025-05-08 15:58:18 +08:00
Lars Kruse
1efeb39da0
style: add codespell configuration for common spelling exceptions
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This file can be extended in order to cover all spelling check
exceptions (perceived as misspellings).
2025-05-05 12:34:39 +08:00
