Use the flag CONFIG_ARCH_HAVE_PERF_EVENTS to detect whether the architecture specific code
provides the up_perf_* functions. Now it is mixed with CONFIG_ARCH_PERF_EVENTS, which should
select just whether the perf events (perf_*) are enabled for the configuration.
- drivers/timers/arch_alarm.c: Don't compile the up_perf_* functions here if the
CONFIG_ARCH_HAVE_PERF_EVENTS is defined
- arch/*/*_perf.c: Change CONFIG_ARCH_PERF_EVENTS -> CONFIG_ARCH_HAVE_PERF_EVENTS to
select whether architecture specific up_perf_* functions are provided
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Bitfield CPHA has to be set to run SPI in mode 0. This is a default mode,
therefore it should be set during the peripheral initialization.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds a LPI2C driver for the mcx-nxxx chip, and the necessary board
definitions for the frdm-mcxn236 evaluation kit.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
FlexRAM peripheral was incorrectly clocked and turned during
M7 sleep. This patch fixes clock setting and ensure that clock
stays on during M7 for backdoor access from for example eDMA
On rt10xx chips the MPU didn't got reset, which is needed for use
with bootloaders. Furthermore the TCM sizes where fixed now we use
kconfig symbol to set the size respectively. Also we mark ITCM as
RO/RO so we can't change data we executed from.
Interrupts should be disabled during the access to the user signature
area in internal flash memory, otherwise the system might be halted.
This applies also for read operation as this is performed with a
special flash commands on a special part of memory.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Fix some misspelled field names.
These field names seem to be used only in private contexts.
Thus, the probability of external code accessing these fields is very
low.
In the rare case of external usage, compile time errors will easily
direct users to the new field name.
Properly select physical bank for block erase based on block number.
Previously, it would configure flash erase bank select based on the logical bank. If banks were swapped, and user application
tried to erase the first block of logical bank 2 (expecting to erase starting at 0x08100000), it would actually erase starting
at 0x0800000. This is fixed in this commit.
Signed-off-by: Tyler Bennett <tbennett@2g-eng.com>
Add ability to use arv8m systick lowerhalf driver
Fix wrong macro for systick current register in initialize
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
The watchdog auto-monitor sets up during the register phase,
so we should be prepared before calling register.
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
The l1entry replace cause huge time when text/data is big,
Need 16KB per task to hold l1table.
Also critical_section no longer required, as table per-task maintained.
For complex goldfish emulator scarios can speed up:
enter_nsh/application_init_done,
from 23.517300/05:07.067500
to 01.501500/00:06.587300
at least 10 times faster.
As we don't have do x_NPAGES swap out etc.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Or will be catch by codespell, when do checkpatch.sh
Also fix the relative comment file changed.
include/nuttx/scsi.h
drivers/syslog/ramlog.c
excluded as we have to modify field name in struct
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Notice: the up_addrenv_pa_to_va is not correct, it will be complex if we
search all address to lookup all virtual address according to physical
address.
Use up_addrenv_x method as common interface across va & pa
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
BUILD CMD: ./tools/configure.sh -l sama5d3x-ek/nx; make -j`nproc`
chip/sam_memories.c:705:17: note: each undeclared identifier is reported only once for each function it appears in
chip/sam_memories.c:706:27: error: 'CONFIG_SAMA5_DDRCS_PGHEAP_SIZE' undeclared (first use in this function); did you mean 'CONFIG_SAMA5_DDRCS_HEAP_SIZE'?
706 | poolend = poolstart + CONFIG_SAMA5_DDRCS_PGHEAP_SIZE;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| CONFIG_SAMA5_DDRCS_HEAP_SIZE
make[1]: *** [Makefile:168: sam_memories.o] Error 1
make[1]: Target 'libarch.a' not remade because of errors.
make: *** [tools/LibTargets.mk:170: arch/arm/src/libarch.a] Error 2
make[1]: Target 'libsched.a' not remade because of errors.
make: *** [tools/LibTargets.mk:71: sched/libsched.a] Error 2
make: Target 'all' not remade because of errors.
~/nuttx/tools/testbuild.sh: line 385: ~/nuttx/../nuttx/nuttx.manifest: No such file or directory
Signed-off-by: wangzhi16 <wangzhi16@xiaomi.com>
- Corrected the typo in the comment of the arch/arm/src/arm/arm_cache.S file.
- Standardized the cache terminology, changing "D-cache" and "I-cache" to "Dcache" and "Icache" for consistency with existing code style.
Signed-off-by: EmomaxD <emreleno@gmail.com>
The previous interrupt implementation allowed only one single interrupt
mode to be selected. The debug assertion is now updated to allow the
entire range of possible interrupt combinations (a 4-bit field), up to
0xf.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
On SMP systems we should enable FPU on each core
FPU extenstion support must be enabled on each core as stated on 4.6.5
arm m33 devices generic user guide
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
RP2350 datasheet and upstream pico-sdk suggests higher VCO freq to
better output stability.
Increase the VCO and update PLL divs according to specs and calculation.
Higher VCO freq is more stable, lower VCO freq is more power friendly.
Also it's possible to use 120/6/5 with VCO 1440MHz for USB PLL to even
higher output stability.
USB setup changes from rp2040
Must clear the MAIN_CTRL.PHY_ISO bit at startup and after power down
events.
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
This adds the necessary code and function to allow a board to determine the reason for a reset. This is useful in NXboot, for example.
Signed-off-by: Tim Hardisty <timh@jti.uk.com>
On the RP2350, the watchdog receives its tick input from the
system-level ticks block, unlike the RP2040, where the watchdog includes
its own tick generator. Enable the TICK blocks, update the watchdog
routines.
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
The RP2040 chip supports 4 different GPIO interrupt modes. They can be
configured to be used simultaneously, although previously the NuttX
support only allowed one type of interrupt to be enabled per GPIO pin.
This allows up to all four to be selected without changing previous
behaviour.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Fix a bug that I2C driver can not transfer after TX abort error.
It caused by remaining NO_STOP flag status.
same as done in commit 0df0a10 for cxd56xx
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
fix PGTABLE_SIZE not defined in sama5d4-ek/knsh
Error: common/arm_allocateheap.c:177:11: error: 'PGTABLE_SIZE' undeclared (first use in this function); did you mean 'PGTABLE_L2_SIZE'?
177 | size -= PGTABLE_SIZE * CONFIG_SMP_NCPUS;
| ^~~~~~~~~~~~
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
If smp enabled, mmu default disabled in arm_head.S,
We have to re-enable it in arm_boot per-chip.
Causing knsh-smp failed with user-space memory access
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
