Summary:
- Updated `Rust.defs` to use `gnu` as the target for Linux systems and `darwin` for macOS systems
- This change aligns with Rust toolchain conventions, where `gnu` is used to declare the system environment rather than the actual ABI name (e.g., `sysv`)
Impact:
- No functional changes - the Rust toolchain interprets `gnu` correctly for Linux targets
- Improves consistency with Rust toolchain conventions and reduces potential confusion
- Maintains compatibility with existing Rust builds on Linux and macOS systems
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This PR fixes the build for Rust Apps and D Apps on QEMU RISC-V. Previously the Rust Build selected the [incorrect Rust Target riscv64i-unknown-none-elf](https://lupyuen.github.io/articles/rust5#rust-target-is-incorrect). Now the Rust Build selects the correct Rust Target: riscv64gc-unknown-none-elf.
This PR also fixes the 32-bit RISC-V Target for D Apps. D Targets ("riscv32") are named differently from Rust Targets ("riscv32gc"), this PR restores the correct Target Names.
Note that Rust Apps won't build correctly for QEMU RISC-V 32-bit. This requires a [Rust Custom Target for riscv32gc](https://lupyuen.github.io/articles/rust4#custom-target-for-rust), which will make the NuttX Makefiles much more complicated.
Also note that `hello_d` won't build correctly for 64-bit `rv-virt:nsh64`. To date, NuttX has never supported 64-bit RISC-V for D Apps.
Modified Files:
`tools/Rust.defs`: Rename the RISC-V ISA `imafdc` to `gc` for Rust Targets
`tools/D.defs`: Exclude the RISC-V ISA for D Targets
Rust/D support for RISC-V is broken after https://github.com/apache/nuttx/pull/11549,
since the target triple is quite different bewteen Rust/D toolchain and GCC,
only few RISC-V targets are supported by Rust toolchain now, so it's better to
construct target triple in Rust.defs/D.defs for RISC-V.
