If the interface is UP, and no packets are received in 30s, re-initialize the interface by calling the
already implemented mpfs_txtimeout_expiry.
This is a workaround for a bug where IF might be UP and working but packets can only
be transmitted. Receive side just doesn't work at all. The bug manifests at least in
older LAN8742A (rev A and B), for which also a silicon errata exists.
The original issue can be re-produced easily by disconnecting and reconnecting the ethernet cable while
the IF is up.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Use LPWORK by default if CONFIG_MPFS_ETHMAC_HPWORK is not defined
- Always use LPWORK for timeouts; this makes very lengthy operations such as re-initializing PHY.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Fix I2C Slave driver write bug when multiple write operation existed for risc-v based Espressif devices
Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
Fix I2C Slave driver write bug when multiple write operation existed for Xtensa based Espressif devices
Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
Add missing files which are causing I2C Slave driver build error for Xtensa based Espressif devices
Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
add missing itm_syslog.h include for archs that use itm_syslog_initialize()
to fix compiler errors:
error: implicit declaration of function 'itm_syslog_initialize'
Issue reported by rentzboy in https://github.com/apache/nuttx/issues/16017
Signed-off-by: raiden00pl <raiden00@railab.me>
AIA releted source files in the Make.defs are not right.
Replace them with the right source.
Fixes: 5f70307111 ("arch/risc-v: introduce AIA support")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Moved imx9 edgelock enclave (ELE) handling from imx9_trdc.c to own imx9_ele.c file.
Add some new messages to ele API.
Updated ele fw version to 1.3.0.
Fix channel bug on imx9_ele_sendmsg() and imx9_ele_receivemsg()
Signed-off-by: Ari Kimari <ari.kimari@tii.ae>
The current default number of IRQ state lists for PHY initialization is 3 (i.e. NR_IRQSTATE_FLAGS).
When calling in a nested manner, the number of times the concurrent behavior enters the critical section exceeds 3, which will trigger an assert crash.
Therefore, the size of NR_IRQSTATE_FLAGS needs to be increased, this PR makes NR_IRQSTATE_FLAGS configurable.
Please refer to the changes of esp-hal-3rdparty: 5d4868f08b
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
Modify addressing to allow only 2 byte node address.
Allow modifying the node address by modifying the ipv6 address
(the ipv6 address has a direct relation with the node address)
Introduce the option to add a 4 byte random number to the mac header
as a preparation for ciphered data exchange.
Introduce a FCB (frame control byte) as a replacement for the INFO
field in the mac header.
Update esp32-devkitc:espnow config to reflect address size change.
Update the documentation to reflect address size changes.
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
This PR adds support for the Allwinner A527 Arm64 SoC.
This will be used by the upcoming port of NuttX for
PINE64 Yuzuki Avaota-A1 SBC.
Most of the code was derived from NuttX for
QEMU Arm64 Kernel Build qemu-armv8a:knsh.
The modified code is explained here:
https://lupyuen.github.io/articles/avaota#appendix-port-nuttx-to-avaota-a1
Modified Files in arch/arm64:
Kconfig: Added ARCH_CHIP_SUNXI for Allwinner 64-bit SoCs.
Added ARCH_CHIP_SUNXI_A527 for A527 SoC.
New Files in arch/arm64:
include/a527/chip.h: A527 Definitions
include/a527/irq.h: External Interrupts
src/a527/chip.h: Memory Map
src/a527/a527_boot.c, a527_boot.h: Startup Code
src/a527/a527_initialize.c: Power Management
src/a527/a527_lowputc.S: UART Output
src/a527/a527_serial.c: Serial Driver
src/a527/a527_textheap.c: Text Heap
src/a527/a527_timer.c: A527 Timer
src/a527/Kconfig: A527 Config
src/a527/Make.defs, CMakeLists.txt: Makefiles
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
This commit introduces support for querying TSC frequency using CPUID 0x40000010. This function can be tested with the following command: `sudo qemu-system-x86_64 -enable-kvm -cpu host,+invtsc,+vmware-cpuid-freq -m 2G -kernel nuttx -nographic -serial mon:stdio -s`
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
To avoid level-1 interrupt break retrieve PC/A0/SP/A2 register,
PS.EXCM set to 1 by CPU HW while handling exception/interrupt.
But if context switching happens and new thread created,
the thread initial value of PS.EXCM is used.
Same behevior as ESP-IDF code:
https://github.com/espressif/esp-idf/blob/master/
components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c#L366
Signed-off-by: Gao Feng <Feng.Gao@sony.com>
Fix build and initialization issues on EFuses using MCUBoot for RISC-V based Espressif devices
Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
Add the mtimer _tick operations for use when tickless mode is not used.
This corrects the tick-based timing calculations, removing tick timer drift
and rounding errors causing early wdog expirations.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add support for the STM32H5 ICACHE peripheral. The CortexM33 does not have typical embedded icache and dcache. Instead STM32H5 provides the ICACHE as a separate peripheral that needs to be configured. This commit adds the stm32h5 specific icache driver. This driver named functions like those in <nuttx/cache.h>. However since the CortexM33 does not have cache itself, ARCH_ICACHE is not enabled. Therefore these stm32h5 specific functions were developed.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
I found an issue when using SPI with nbits=8: SPI reads return unreliable
results because SPI ignores nbits value and always performs 16-bit reads.
Signed-off-by: Daniel Martín Gómez <danielmartingomez@geotab.com>
ifdelay description (delay between frames) matches the DLYBCT field
(delay between consecutive transfers without removing chip select)
much better compared to stopdelay (delay between last CLK and CS
innactive). The option for stopdelay does not seem to be configurable
in SAMv7 peripheral.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This fixes a crash at boot on 64-bit risc-v systems which need to store
64-bit registers to the stack aligned to 8 byte boundary.
Specifically, this uses 8 bytes to store ra and s0 on rv32 and 16 bytes on
rv64, and does the register stores and loads properly aligned acc. to the
register size.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit includes a change to the esp_txint function in the arch/risc-v/src/common/espressif/esp_usbserial.c file. The change primarily involves removing an optimization workaround and adding a call to flush the transmit FIFO.
After this change the usbserial config is able to work using all optimization levels.
Changes in esp_txint function:
Removed the __attribute__((optimize("O0"))) workaround.
Added a call to usb_serial_jtag_ll_txfifo_flush() at the beginning of the function.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
This PR adds support for the ESWIN EIC7700X RISC-V SoC.
This will be used by the upcoming port of NuttX for PINE64 StarPro64 SBC.
Most of the code was derived from NuttX for SOPHGO SG2000 SoC.
The modified code is explained here:
https://lupyuen.github.io/articles/starpro64#appendix-port-nuttx-to-starpro64
Modified Files in arch/risc-v:
Kconfig: Added ARCH_CHIP_EIC7700X for EIC7700X SoC
New Files in arch/risc-v:
include/eic7700x/chip.h: EIC7700X Definitions
include/eic7700x/irq.h: External Interrupts
src/eic7700x/chip.h: Interrupt Stack Macro
src/eic7700x/eic7700x_allocateheap.c: Kernel Heap
src/eic7700x/eic7700x_head.S: Linux Header and Boot Code
src/eic7700x/eic7700x_irq.c: Configure Interrupts
src/eic7700x/eic7700x_irq_dispatch.c: Dispatch Interrupts
src/eic7700x/eic7700x_memorymap.h: Memory Map
src/eic7700x/eic7700x_mm_init.c, eic7700x_mm_init.h: Memory Mgmt
src/eic7700x/eic7700x_pgalloc.c: Page Allocator
src/eic7700x/eic7700x_start.c: Startup Code
src/eic7700x/eic7700x_timerisr.c: Timer Interrupt
src/eic7700x/hardware/eic7700x_memorymap.h: PLIC and UART Base Address
src/eic7700x/hardware/eic7700x_plic.h: PLIC Register Addresses
src/eic7700x/Kconfig: EIC7700X Config
src/eic7700x/Make.defs: Makefile
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
This PR fixes the typos in the Code Comments of chip.h, allocateheap.c
and start.c. The typos were discovered here:
- https://github.com/apache/nuttx/pull/15921
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
This commit improves the configuration of complementary PWM mode for
Tiva C-Series microcontrollers by moving the complementary flag
definition directly into each channel structure.
Changes made:
- Renamed 'complementary_generation' to 'complementary' for clarity.
- Moved complementary mode configuration into the static PWM
channel structures.
- Replaced runtime conditional checks with compile-time configuration
using '#ifdef CONFIG_TIVA_PWM_COMPLEMENTARY_Gx'.
- Improved readability and maintainability of the PWM driver.
These modifications ensure a more efficient initialization process,
reduce runtime conditionals, and align better with NuttX coding practices.
Signed-off-by: Sydeney Araujo <sydney.wagner39@gmail.com>
`boot_stage_puts` used by early asm calls arm64_lowputc() for each
character in a loop. During that loop it uses x1 as the pointer to
the next character to be printed. However, x1 is clobbered by
arm64_lowputc(), resulting in undefined behaviour (only the first
character of the string is guaranteed to be printed).
Fix this by using x19 instead.
Signed-off-by: George Poulios <gpoulios@census-labs.com>
Following the https://github.com/apache/nuttx/pull/14741, add the
`ARCH_HAVE_RAMFUNCS` config to ESP32-C6 and ESP32-H2 to suppress
the RWX memory region warning.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Add basic support for RA4M1.
The following perpheral are added:
* GPIO
* SCI (UART)
* Clock (Just internal clock - HOCO)
Signed-off-by: leocafonso <leocafonso@gmail.com>
Update the wireless symbols from ESP32_* to ESPRESSIF_* for using common layer.
Remove ESP32 specific WiFi files and edit build system to use common layer.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, switch the pin mode to I2C at the end of the i2c
initialization function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, add clock gating process and disable GPIO input
to the I2C reset function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
This commit disables optimization that alters ESP32C6 interrupt registers.
Without this optimization, the USB serial driver does not work properly.
This is a temporary workaround until a proper fix is found.
Signed-off-by: Felipe Moura de Oliveira <moura.fmo@gmail.com>
DTE (dead time enable) is the 17th bit in CMRx (channel mode) register.
Function pwm_set_polarity did however read and write this register as
16 bit large, therefore dead time generation was always disabled.
This fixes the issue, pwm_set_polarity now reads the register as 32
large.
Also set the initial value of CMRx correctly in pwm_setup().
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
