234 lines
8.7 KiB
C
234 lines
8.7 KiB
C
/****************************************************************************
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* arch/arm/src/lpc17xx_40xx/lpc178x_40xx_clockconfig.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "lpc17_40_clockconfig.h"
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#include "hardware/lpc17_40_syscon.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef LPC178x_40xx
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# error "The logic in this file applies only to the LPC178x/40xx family"
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc17_40_clockconfig
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*
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* Description:
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* Called to initialize the LPC17xx/LPC40xx.
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* This does whatever setup is needed to put the SoC in a usable state.
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* This includes the initialization of clocking using the settings in
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* board.h.
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*
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* The LPC176x and LPC178x/40xx system control block is *nearly* identical
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* but we have found that the LPC178x/40xx is more sensitive to the
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* ordering of certain operations. So, although the hardware seems very
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* similar, the safer thing to do is to separate the LPC176x and
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* LPC178x/40xx into separate files.
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*
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****************************************************************************/
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void lpc17_40_clockconfig(void)
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{
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uint32_t regval;
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/* TODO:
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*
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* (1) "Make sure that the PLL output is not already being used. The
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* CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers must not select the
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* PLL being set up. Clock dividers included in these registers may
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* also be set up at this time if writing to any of the noted
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* registers."
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*
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* (2) "If the main PLL is being set up, and the main clock source is being
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* changed (IRC versus main oscillator), change this first by writing
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* the correct value to the CLKSRCSEL register."
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*
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* This is not an issue now because we only setup the clocks on power up,
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* so the PLL cannot be the select source. However, this could be an issue
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* at some point later when, for example, we may want to implement reduced
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* power mode with other clocking.
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*/
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/* Enable the main oscillator (or not) and the frequency range of the main
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* oscillator
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*/
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putreg32(BOARD_SCS_VALUE, LPC17_40_SYSCON_SCS);
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/* Wait for the main oscillator to be ready. */
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#ifdef CONFIG_LPC17_40_MAINOSC
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while ((getreg32(LPC17_40_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0);
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#endif
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/* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
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#ifdef CONFIG_LPC17_40_PLL0
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/* (3) "Write PLL new setup values to the PLLCFG register. Write a 1 to
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* the PLLE bit in the PLLCON register. Perform a PLL feed sequence
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* by writing first the value 0xAA, then the value 0x55 to the PLLFEED
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* register"
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*
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* Select the PLL0 source clock, multiplier, and pre-divider values.
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* NOTE that a special "feed" sequence must be written to the PLL0FEED
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* register in order for changes to the PLL0CFG register to take effect.
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*/
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putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_40_SYSCON_CLKSRCSEL);
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putreg32(BOARD_PLL0CFG_VALUE, LPC17_40_SYSCON_PLL0CFG);
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putreg32(SYSCON_PLLCON_PLLE, LPC17_40_SYSCON_PLL0CON);
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/* Enable the PLL.
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* NOTE that a special "feed" sequence must be written to the PLL0FEED
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* register in order for changes to the PLL0CON register to take effect.
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*/
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putreg32(0xaa, LPC17_40_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_40_SYSCON_PLL0FEED);
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/* (4) "Set up the necessary clock dividers. These may include the CCLKSEL,
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* PCLKSEL, EMCCLKSEL, USBCLKSEL, and the SPIFICLKSEL registers.
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*/
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putreg32(BOARD_CCLKSEL_VALUE, LPC17_40_SYSCON_CCLKSEL);
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putreg32(BOARD_PCLKDIV, LPC17_40_SYSCON_PCLKSEL);
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#ifdef CONFIG_LPC17_40_EMC
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putreg32(BOARD_EMCCLKSEL_VALUE, LPC17_40_SYSCON_EMCCLKSEL);
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#endif
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#if defined(CONFIG_LPC17_40_USBDEV) || defined(CONFIG_LPC17_40_USBHOST)
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putreg32(BOARD_USBCLKSEL_VALUE, LPC17_40_SYSCON_USBCLKSEL);
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#endif
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#ifdef CONFIG_LPC17_40_SPIFI
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putreg32(BOARD_SPIFICLKSEL_VALUE, LPC17_40_SPIFICLKSEL_CCLKSEL);
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#endif
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/* (5) "Wait for the PLL to lock. This may be accomplished by polling the
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* PLLSTAT register and testing for PLOCK = 1, or by using the PLL
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* lock interrupt.Wait for PLL0 to lock.
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*/
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while ((getreg32(LPC17_40_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0);
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/* (6) "Connect the PLL by selecting its output in the appropriate places.
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* This may include the CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers.
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*/
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#endif /* CONFIG_LPC17_40_PLL0 */
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/* PLL1 receives its clock input from the main oscillator only and can be
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* used to provide a fixed 48 MHz clock only to the USB subsystem (if that
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* clock cannot be obtained from PLL0).
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*/
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#ifdef CONFIG_LPC17_40_PLL1
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/* (3) "Write PLL new setup values to the PLLCFG register. Write a 1 to
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* the PLLE bit in the PLLCON register. Perform a PLL feed sequence by
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* writing first the value 0xAA, then the value 0x55 to the PLLFEED
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* register"
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*
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* Select the PLL1 multiplier, and pre-divider values.
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* NOTE that a special "feed" sequence must be written to the PLL1FEED
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* register in order for changes to the PLL1CFG register to take effect.
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*/
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putreg32(BOARD_PLL1CFG_VALUE, LPC17_40_SYSCON_PLL1CFG);
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putreg32(SYSCON_PLLCON_PLLE, LPC17_40_SYSCON_PLL1CON);
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/* Enable the PLL. NOTE that a special "feed" sequence must be written to
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* the PLL1FEED register in order for changes to the PLL1CON register to
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* take effect.
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*/
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putreg32(0xaa, LPC17_40_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_40_SYSCON_PLL1FEED);
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/* (4) "Set up the necessary clock dividers. These may include the CCLKSEL,
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* PCLKSEL, EMCCLKSEL, USBCLKSEL, and the SPIFICLKSEL registers.
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*/
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/* (5) "Wait for the PLL to lock. This may be accomplished by polling the
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* PLLSTAT register and testing for PLOCK = 1, or by using the PLL
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* lock interrupt.Wait for PLL0 to lock.
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*/
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while ((getreg32(LPC17_40_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0);
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/* (6) "Connect the PLL by selecting its output in the appropriate places.
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* This may include the CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers.
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*/
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#endif /* CONFIG_LPC17_40_PLL1 */
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/* Disable power to all peripherals (except GPIO and left EMC intact).
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* EMC is switched off after reset but if there is boot-loader,
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* it can left it on and if SDRAM is used for NuttX execution then
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* disabling blocks system. Other peripherals must be re-powered
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* one at a time by each device driver when the driver is initialized.
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*/
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regval = getreg32(LPC17_40_SYSCON_PCONP);
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regval &= SYSCON_PCONP_PCEMC;
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regval |= SYSCON_PCONP_PCGPIO;
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putreg32(regval, LPC17_40_SYSCON_PCONP);
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/* Disable CLKOUT */
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putreg32(0, LPC17_40_SYSCON_CLKOUTCFG);
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/* Configure FLASH */
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#ifdef CONFIG_LPC17_40_FLASH
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putreg32(BOARD_FLASHCFG_VALUE, LPC17_40_SYSCON_FLASHCFG);
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#endif
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}
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