262 lines
9.3 KiB
C
262 lines
9.3 KiB
C
/****************************************************************************
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* arch/arm/src/lpc17xx_40xx/lpc17_40_ohciram.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_OHCIRAM_H
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#define __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_OHCIRAM_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "hardware/lpc17_40_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Default, no-OHCI Case ****************************************************/
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/* Assume that all of AHB SRAM will be available for heap.
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* If this is not true, then LPC17_40_BANK1_HEAPSIZE will be undefined but
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* redefined below.
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*/
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#undef LPC17_40_BANK1_HEAPBASE
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#undef LPC17_40_BANK1_HEAPSIZE
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#ifdef LPC17_40_HAVE_BANK1
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# define LPC17_40_BANK1_HEAPBASE LPC17_40_SRAM_BANK1
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# define LPC17_40_BANK1_HEAPSIZE LPC17_40_BANK1_SIZE
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#endif
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/* Is networking enabled?
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* Is the LPC17xx/LPC40xx Ethernet device enabled? Does this chip have
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* and Ethernet controlloer?
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* Yes... then we will replace the above default definitions.
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*/
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#if defined(CONFIG_USBHOST) && defined(CONFIG_LPC17_40_USBHOST) && LPC17_40_NUSBHOST > 0
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/* OHCI RAM Configuration ***************************************************/
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/* Is AHB SRAM available? */
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#ifndef LPC17_40_HAVE_BANK1
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# error "AHB SRAM Bank1 is not available for OHCI RAM"
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#endif
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/* OHCI/Heap Memory Allocation **********************************************/
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/* Configured Size of the region at the end of AHB SRAM BANK1 set set aside
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* for the OHCI. This size must fit within AHB SRAM Bank 1 and also be a
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* multiple of 256 bytes.
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*/
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#ifndef CONFIG_LPC17_40_OHCIRAM_SIZE
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# define CONFIG_LPC17_40_OHCIRAM_SIZE LPC17_40_BANK1_SIZE
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#endif
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#if CONFIG_LPC17_40_OHCIRAM_SIZE > LPC17_40_BANK1_SIZE
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# error "OHCI RAM size cannot exceed the size of AHB SRAM Bank 1"
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#endif
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#if (CONFIG_LPC17_40_OHCIRAM_SIZE & 0xff) != 0
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# error "OHCI RAM size must be in multiples of 256 bytes"
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#endif
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/* Then position the OHCI RAM at the end of AHB SRAM Bank 1 */
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#define LPC17_40_OHCIRAM_END (LPC17_40_SRAM_BANK1 + LPC17_40_BANK1_SIZE)
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#define LPC17_40_OHCIRAM_BASE (LPC17_40_OHCIRAM_END - CONFIG_LPC17_40_OHCIRAM_SIZE)
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#define LPC17_40_OHCIRAM_SIZE CONFIG_LPC17_40_OHCIRAM_SIZE
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/* Determine is there is any meaningful space left at the beginning of
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* AHB Bank 1 that could be added to the heap.
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*/
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#undef LPC17_40_BANK1_HEAPBASE
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#undef LPC17_40_BANK1_HEAPSIZE
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#if LPC17_40_OHCIRAM_SIZE < (LPC17_40_BANK1_SIZE-128)
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# define LPC17_40_BANK1_HEAPBASE LPC17_40_SRAM_BANK1
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# define LPC17_40_BANK1_HEAPSIZE (LPC17_40_BANK1_SIZE - LPC17_40_OHCIRAM_SIZE)
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#endif
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/* Numbers and Sizes of Things **********************************************/
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/* Fixed size of the OHCI control area */
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#define LPC17_40_HCCA_SIZE 256
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/* Fixed endpoint descriptor size.
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* The actual size required by the hardware is only 16 bytes, however, we set
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* aside an additional 16 bytes for for internal use by the OHCI host driver.
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* 16-bytes is set aside because the EDs must still be aligned to 16-byte
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* boundaries.
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*/
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#define LPC17_40_ED_SIZE 32
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/* Configurable number of user endpoint descriptors (EDs).
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* This number excludes the control endpoint that is always allocated.
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*/
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#ifndef CONFIG_LP17_USBHOST_NEDS
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# define CONFIG_LP17_USBHOST_NEDS 2
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#endif
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/* Derived size of user endpoint descriptor (ED) memory. */
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#define LPC17_40_EDFREE_SIZE (CONFIG_LP17_USBHOST_NEDS * LPC17_40_ED_SIZE)
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/* Fixed transfer descriptor size.
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* The actual size required by the hardware is only 16 bytes, however, we set
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* aside an additional 16 bytes for for internal use bythe OHCI host driver.
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* 16-bytes is set aside because the TDs must still be aligned to 16-byte
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* boundaries.
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*/
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#define LPC17_40_TD_SIZE 32
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/* Configurable number of user transfer descriptors (TDs). */
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#ifndef CONFIG_LP17_USBHOST_NTDS
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# define CONFIG_LP17_USBHOST_NTDS 3
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#endif
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#if CONFIG_LP17_USBHOST_NTDS < 2
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# error "Insufficient TDs"
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#endif
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/* Derived size of user transfer descriptor (TD) memory. */
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#define LPC17_40_TDFREE_SIZE (CONFIG_LP17_USBHOST_NTDS * LPC17_40_TD_SIZE)
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/* Configurable number of request/descriptor buffers (TDBUFFER) */
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#ifndef CONFIG_LPC17_40_USBHOST_TDBUFFERS
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# define CONFIG_LPC17_40_USBHOST_TDBUFFERS 2
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#endif
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#if CONFIG_LPC17_40_USBHOST_TDBUFFERS < 2
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# error "At least two TD buffers are required"
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#endif
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/* Configurable size of a TD buffer */
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#if CONFIG_LPC17_40_USBHOST_TDBUFFERS > 0 && !defined(CONFIG_LPC17_40_USBHOST_TDBUFSIZE)
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# define CONFIG_LPC17_40_USBHOST_TDBUFSIZE 128
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#endif
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#if (CONFIG_LPC17_40_USBHOST_TDBUFSIZE & 3) != 0
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# error "TD buffer size must be an even number of 32-bit words"
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#endif
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#define LPC17_40_TBFREE_SIZE (CONFIG_LPC17_40_USBHOST_TDBUFFERS * CONFIG_LPC17_40_USBHOST_TDBUFSIZE)
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/* Configurable size of an IO buffer.
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* The number of IO buffers will be determined by what is left at the end
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* of the BANK1 memory setup aside of OHCI RAM.
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*/
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#ifndef CONFIG_LPC17_40_USBHOST_IOBUFSIZE
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# define CONFIG_LPC17_40_USBHOST_IOBUFSIZE 512
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#endif
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#if (CONFIG_LPC17_40_USBHOST_IOBUFSIZE & 3) != 0
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# error "IO buffer size must be an even number of 32-bit words"
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#endif
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/* OHCI Memory Layout *******************************************************/
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/* Example:
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* Hardware:
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* LPC17_40_SRAM_BANK1 0x20008000
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* LPC17_40_BANK1_SIZE 16384
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*
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* Configuration:
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* CONFIG_LPC17_40_OHCIRAM_SIZE 1536
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* CONFIG_LP17_USBHOST_NEDS 2
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* CONFIG_LP17_USBHOST_NTDS 3
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* CONFIG_LPC17_40_USBHOST_TDBUFFERS 3
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* CONFIG_LPC17_40_USBHOST_TDBUFSIZE 128
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* CONFIG_LPC17_40_USBHOST_IOBUFSIZE 512
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*
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* Sizes of things
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* LPC17_40_EDFREE_SIZE 64 0x00000040
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* LPC17_40_TDFREE_SIZE 96 0x00000060
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* LPC17_40_TBFREE_SIZE 384 0x00000100
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* LPC17_40_IOFREE_SIZE 512 0x00000200
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*
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* Memory Layout
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* LPC17_40_OHCIRAM_END (0x20008000 + 16384) = 0x20084000
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* LPC17_40_OHCIRAM_BASE (0x2000c000 - 1536) = 0x2000ba00
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* LPC17_40_OHCIRAM_SIZE 1280
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* LPC17_40_BANK1_HEAPBASE 0x20008000
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* LPC17_40_BANK1_HEAPSIZE (16384 - 1280) = 15104
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*
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* LPC17_40_HCCA_BASE 0x20083a00 -- Communications area
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* LPC17_40_TDTAIL_ADDR 0x20083b00 -- Common. pre-allocated tail TD
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* LPC17_40_EDCTRL_ADDR 0x20083b20 -- Pre-allocated ED for EP0
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* LPC17_40_EDFREE_BASE 0x20083b40 -- Free EDs
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* LPC17_40_TDFREE_BASE 0x20083b80 -- Free TDs
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* LPC17_40_TBFREE_BASE 0x20083be0 -- Free request/descriptor buffers
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* LPC17_40_IOFREE_BASE 0x20083d60 -- Free large I/O buffers
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* LPC17_40_IOBUFFERS (0x20084000 - 0x20083d60) / 512 = 672/512 = 1
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*
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* Wasted memory: 672-512 = 160 bytes
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*/
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#define LPC17_40_HCCA_BASE (LPC17_40_OHCIRAM_BASE)
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#define LPC17_40_TDTAIL_ADDR (LPC17_40_HCCA_BASE + LPC17_40_HCCA_SIZE)
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#define LPC17_40_EDCTRL_ADDR (LPC17_40_TDTAIL_ADDR + LPC17_40_TD_SIZE)
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#define LPC17_40_EDFREE_BASE (LPC17_40_EDCTRL_ADDR + LPC17_40_ED_SIZE)
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#define LPC17_40_TDFREE_BASE (LPC17_40_EDFREE_BASE + LPC17_40_EDFREE_SIZE)
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#define LPC17_40_TBFREE_BASE (LPC17_40_TDFREE_BASE + LPC17_40_TDFREE_SIZE)
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#define LPC17_40_IOFREE_BASE (LPC17_40_TBFREE_BASE + LPC17_40_TBFREE_SIZE)
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#if LPC17_40_IOFREE_BASE > LPC17_40_OHCIRAM_END
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# error "Insufficient OHCI RAM allocated"
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#endif
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/* Finally, use the remainder of the allocated OHCI for IO buffers */
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#if CONFIG_LPC17_40_USBHOST_IOBUFSIZE > 0
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# define LPC17_40_IOBUFFERS ((LPC17_40_OHCIRAM_END - LPC17_40_IOFREE_BASE) / CONFIG_LPC17_40_USBHOST_IOBUFSIZE)
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#else
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# define LPC17_40_IOBUFFERS 0
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* CONFIG_USBHOST && CONFIG_LPC17_40_USBHOST && LPC17_40_NUSBHOST > 0*/
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#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_OHCIRAM_H */
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