805 lines
23 KiB
C
805 lines
23 KiB
C
/****************************************************************************
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* arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/timers/pwm.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "chip.h"
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#include "hardware/lpc17_40_syscon.h"
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#include "lpc17_40_pwm.h"
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#include "hardware/lpc176x_pinconfig.h"
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#include "lpc17_40_gpio.h"
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#include "lpc176x_gpio.h"
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/* This module then only compiles if there is at least one enabled timer
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* intended for use with the PWM upper half driver.
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*/
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#if defined(CONFIG_LPC17_40_PWM1)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* PWM/Timer Definitions ****************************************************/
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/* The following definitions are used to identify the various time types */
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#define TIMTYPE_BASIC 0 /* Basic timers: TIM6-7 */
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#define TIMTYPE_GENERAL16 1 /* General 16-bit timers: TIM2-5 on F1 */
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#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM9-14 on F4 */
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#define TIMTYPE_GENERAL32 3 /* General 32-bit timers: TIM2-5 on F4 */
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#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1-8 */
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#define TIMTYPE_TIM1 TIMTYPE_ADVANCED
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#define LER0_EN (1 << 0)
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#define LER1_EN (1 << 1)
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#define LER2_EN (1 << 2)
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#define LER3_EN (1 << 3)
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#define LER4_EN (1 << 4)
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#define LER5_EN (1 << 5)
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#define LER6_EN (1 << 6)
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#define PWMENA1 (1 << 9)
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#define PWMENA2 (1 << 10)
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#define PWMENA3 (1 << 11)
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#define PWMENA4 (1 << 12)
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#define PWMENA5 (1 << 13)
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#define PWMENA6 (1 << 14)
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#define TCR_CNT_EN (0x00000001)
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#define TCR_RESET (0x00000002)
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#define TCR_PWM_EN (0x00000008)
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/* Debug ********************************************************************/
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#ifdef CONFIG_DEBUG_PWM_INFO
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# define pwm_dumpgpio(p,m) lpc17_40_dumpgpio(p,m)
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#else
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# define pwm_dumpgpio(p,m)
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure represents the state of one PWM timer */
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struct lpc17_40_pwmchan_s
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{
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uint8_t channel; /* Timer output channel */
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uint32_t pincfg; /* Output pin configuration */
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};
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struct lpc17_40_pwmtimer_s
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{
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const struct pwm_ops_s *ops; /* PWM operations */
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struct lpc17_40_pwmchan_s *channels; /* Channels configuration */
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uint8_t timid; /* Timer ID {0,...,7} */
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uint8_t chan_num; /* Number of configured channels */
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uint8_t timtype; /* See the TIMTYPE_* definitions */
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uint32_t base; /* The base address of the timer */
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uint32_t pclk; /* The frequency of the peripheral clock
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* that drives the timer module. */
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};
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/****************************************************************************
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* Static Function Prototypes
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****************************************************************************/
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/* Register access */
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static uint32_t pwm_getreg(struct lpc17_40_pwmtimer_s *priv, int offset);
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static void pwm_putreg(struct lpc17_40_pwmtimer_s *priv,
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int offset, uint32_t value);
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#ifdef CONFIG_DEBUG_PWM_INFO
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static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv,
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const char *msg);
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#else
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# define pwm_dumpregs(priv,msg)
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#endif
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/* Timer management */
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static int pwm_timer(struct lpc17_40_pwmtimer_s *priv,
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const struct pwm_info_s *info);
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/* PWM driver methods */
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static int pwm_setup(struct pwm_lowerhalf_s *dev);
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static int pwm_shutdown(struct pwm_lowerhalf_s *dev);
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static int pwm_start(struct pwm_lowerhalf_s *dev,
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const struct pwm_info_s *info);
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static int pwm_stop(struct pwm_lowerhalf_s *dev);
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static int pwm_ioctl(struct pwm_lowerhalf_s *dev,
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int cmd, unsigned long arg);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* This is the list of lower half PWM driver methods used by the upper half
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* driver
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*/
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static const struct pwm_ops_s g_pwmops =
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{
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.setup = pwm_setup,
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.shutdown = pwm_shutdown,
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.start = pwm_start,
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.stop = pwm_stop,
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.ioctl = pwm_ioctl,
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};
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#ifdef CONFIG_LPC17_40_PWM1
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static struct lpc17_40_pwmchan_s g_pwm1channels[] =
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{
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/* PWM1 has 6 channels */
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL1
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{
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.channel = 1,
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.pincfg = GPIO_PWM1p1,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL2
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{
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.channel = 2,
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.pincfg = GPIO_PWM1p2,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL3
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{
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.channel = 3,
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.pincfg = GPIO_PWM1p3,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL4
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{
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.channel = 4,
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.pincfg = GPIO_PWM1p5,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL5
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{
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.channel = 5,
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.pincfg = GPIO_PWM1p5,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL6
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{
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.channel = 6,
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.pincfg = GPIO_PWM1p6,
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},
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#endif
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};
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static struct lpc17_40_pwmtimer_s g_pwm1dev =
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{
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.ops = &g_pwmops,
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.timid = 1,
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.chan_num = LPC17_40_PWM1_NCHANNELS,
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.channels = g_pwm1channels,
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.timtype = TIMTYPE_TIM1,
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.base = LPC17_40_PWM1_BASE,
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.pclk = (0x1 << 12),
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};
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: pwm_getreg
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*
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* Description:
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* Read the value of an PWM timer register.
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*
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* Input Parameters:
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* priv - A reference to the PWM block status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* The current contents of the specified register
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*
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****************************************************************************/
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static uint32_t pwm_getreg(struct lpc17_40_pwmtimer_s *priv, int offset)
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{
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return getreg32(priv->base + offset);
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}
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/****************************************************************************
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* Name: pwm_putreg
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*
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* Description:
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* Read the value of an PWM timer register.
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*
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* Input Parameters:
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* priv - A reference to the PWM block status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void pwm_putreg(struct lpc17_40_pwmtimer_s *priv,
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int offset, uint32_t value)
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{
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putreg32(value, priv->base + offset);
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}
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/****************************************************************************
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* Name: pwm_dumpregs
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*
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* Description:
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* Dump all timer registers.
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*
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* Input Parameters:
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* priv - A reference to the PWM block status
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_PWM_INFO
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static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv,
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const char *msg)
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{
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pwminfo("%s:\n", msg);
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pwminfo(" IR: %04x TCR: %04x TC: %04x PR: %04x PC: %04x\n",
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pwm_getreg(priv, LPC17_40_PWM_IR_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_TCR_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_TC_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_PR_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_PC_OFFSET));
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pwminfo(" MCR: %04x\n",
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pwm_getreg(priv, LPC17_40_PWM_MCR_OFFSET));
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#ifdef CONFIG_PWM_MULTICHAN
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pwminfo(" 0: %08x 1: %08x 2: %08x 3: %08x\n",
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pwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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pwminfo(" 4: %08x 5: %08x 6: %08x\n",
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pwm_getreg(priv, LPC17_40_PWM_MR4_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR5_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR6_OFFSET));
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#endif
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}
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#endif
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/****************************************************************************
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* Name: pwm_timer
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*
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* Description:
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* (Re-)initialize the timer resources and start the pulsed output
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*
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* Input Parameters:
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* priv - A reference to the lower half PWM driver state structure
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* info - A reference to the characteristics of the pulsed output
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int pwm_timer(struct lpc17_40_pwmtimer_s *priv,
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const struct pwm_info_s *info)
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{
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irqstate_t flags;
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uint32_t i;
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int ret = OK;
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uint32_t lerval = LER0_EN;
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uint32_t pcrval = 0;
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uint32_t mr0_freq;
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flags = enter_critical_section();
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mr0_freq = 1.f / info->frequency * LPC17_40_PWM_CLOCK / 10;
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putreg32(mr0_freq, LPC17_40_PWM1_MR0); /* Set PWMMR0 = number of counts */
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#ifndef CONFIG_PWM_MULTICHAN
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putreg32(info->duty, LPC17_40_PWM1_MR1); /* Set PWM cycle */
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#else
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for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
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{
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switch (priv->channels[i].channel)
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{
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL1
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case 1:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR1); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL2
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case 2:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR2); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL3
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case 3:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR3); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL4
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case 4:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR4); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL5
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case 5:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR5); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL6
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case 6:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR6); /* Set PWM cycle */
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break;
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#endif
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default:
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{
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pwmerr("ERROR: Channel %d does not exist\n",
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priv->channels[i].channel);
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ret = -EINVAL;
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}
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}
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}
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL1
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pcrval |= PWMENA1;
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lerval |= LER1_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL2
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pcrval |= PWMENA2;
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lerval |= LER2_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL3
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pcrval |= PWMENA3;
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lerval |= LER3_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL4
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pcrval |= PWMENA4;
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lerval |= LER4_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL5
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pcrval |= PWMENA5;
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lerval |= LER5_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL6
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pcrval |= PWMENA6;
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lerval |= LER6_EN;
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#endif
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putreg32(lerval, LPC17_40_PWM1_LER); /* Load Shadow register contents */
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putreg32(pcrval, LPC17_40_PWM1_PCR); /* Enable PWM outputs */
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putreg32(TCR_CNT_EN | TCR_PWM_EN, LPC17_40_PWM1_TCR); /* Enable PWM Timer */
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leave_critical_section(flags);
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pwm_dumpregs(priv, "After starting");
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return ret;
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}
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#ifdef XXXXX
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/****************************************************************************
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* Name: pwm_interrupt
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*
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* Description:
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* Handle timer interrupts.
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*
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* Input Parameters:
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* priv - A reference to the lower half PWM driver state structure
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int pwm_interrupt(struct lpc17_40_pwmtimer_s *priv)
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{
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uint16_t regval;
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/* Verify that this is an update interrupt. Nothing else is expected. */
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regval = pwm_getreg(priv, STM32_ATIM_SR_OFFSET);
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DEBUGASSERT((regval & ATIM_SR_UIF) != 0);
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/* Clear the UIF interrupt bit */
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pwm_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF);
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/* Calculate the new count by subtracting the number of pulses
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* since the last interrupt.
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*/
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return OK;
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}
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/****************************************************************************
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* Name: pwm_tim1/8interrupt
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*
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* Description:
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* Handle timer 1 and 8 interrupts.
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*
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* Input Parameters:
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* Standard NuttX interrupt inputs
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int pwm_tim1interrupt(int irq, void *context, void *arg)
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{
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return pwm_interrupt(&g_pwm1dev);
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}
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/****************************************************************************
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* Name: pwm_set_apb_clock
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*
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* Description:
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* Enable or disable APB clock for the timer peripheral
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*
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* Input Parameters:
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* dev - A reference to the lower half PWM driver state structure
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* on - Enable clock if 'on' is 'true' and disable if 'false'
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*
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****************************************************************************/
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static void pwm_set_apb_clock(struct lpc17_40_pwmtimer_s *priv, bool on)
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{
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uint32_t en_bit;
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uint32_t regaddr;
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/* Determine which timer to configure */
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switch (priv->timid)
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{
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#ifdef CONFIG_LPC17_40_PWM1
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case 1:
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regaddr = STM32_RCC_APB2ENR;
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en_bit = RCC_APB2ENR_TIM1EN;
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break;
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#endif
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}
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/* Enable/disable APB 1/2 clock for timer */
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if (on)
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{
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modifyreg32(regaddr, 0, en_bit);
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}
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|
else
|
|
{
|
|
modifyreg32(regaddr, en_bit, 0);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: pwm_setup
|
|
*
|
|
* Description:
|
|
* This method is called when the driver is opened. The lower half driver
|
|
* should configure and initialize the device so that it is ready for use.
|
|
* It should not, however, output pulses until the start method is called.
|
|
*
|
|
* Input Parameters:
|
|
* dev - A reference to the lower half PWM driver state structure
|
|
*
|
|
* Returned Value:
|
|
* Zero on success; a negated errno value on failure
|
|
*
|
|
* Assumptions:
|
|
* APB1 or 2 clocking for the GPIOs has already been configured by the RCC
|
|
* logic at power up.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int pwm_setup(struct pwm_lowerhalf_s *dev)
|
|
{
|
|
struct lpc17_40_pwmtimer_s *priv =
|
|
(struct lpc17_40_pwmtimer_s *)dev;
|
|
irqstate_t flags;
|
|
uint32_t regval;
|
|
int i;
|
|
|
|
flags = enter_critical_section();
|
|
|
|
/* Power on the pwm peripheral */
|
|
|
|
regval = getreg32(LPC17_40_SYSCON_PCONP);
|
|
regval |= SYSCON_PCONP_PCPWM1;
|
|
putreg32(regval, LPC17_40_SYSCON_PCONP);
|
|
|
|
/* Select clock for the pwm peripheral */
|
|
|
|
regval = getreg32(LPC17_40_SYSCON_PCLKSEL0);
|
|
regval &= ~SYSCON_PCLKSEL0_PWM1_MASK; /* PCLK_MC peripheral clk = CCLK = LPC17_40_CCLK */
|
|
regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_PWM1_SHIFT); /* PCLK_MC peripheral clk = CCLK = LPC17_40_CCLK */
|
|
putreg32(regval, LPC17_40_SYSCON_PCLKSEL0);
|
|
priv->pclk = (0x1 << 12);
|
|
|
|
/* Configure the output pin */
|
|
|
|
for (i = 0; i < priv->chan_num; i++)
|
|
{
|
|
lpc17_40_configgpio(priv->channels[i].pincfg);
|
|
}
|
|
|
|
putreg32(1, LPC17_40_PWM1_PR); /* Prescaler count frequency: Fpclk/1 */
|
|
putreg32(1 << 1, LPC17_40_PWM1_MCR); /* Reset on match register MR0 */
|
|
|
|
leave_critical_section(flags);
|
|
pwm_dumpgpio(priv->pincfg, "PWM setup");
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: pwm_shutdown
|
|
*
|
|
* Description:
|
|
* This method is called when the driver is closed. The lower half driver
|
|
* stop pulsed output, free any resources, disable the timer hardware, and
|
|
* put the system into the lowest possible power usage state
|
|
*
|
|
* Input Parameters:
|
|
* dev - A reference to the lower half PWM driver state structure
|
|
*
|
|
* Returned Value:
|
|
* Zero on success; a negated errno value on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int pwm_shutdown(struct pwm_lowerhalf_s *dev)
|
|
{
|
|
struct lpc17_40_pwmtimer_s *priv =
|
|
(struct lpc17_40_pwmtimer_s *)dev;
|
|
uint32_t regval;
|
|
uint32_t i;
|
|
|
|
/* Configure the output pin to be output and low */
|
|
|
|
for (i = 0; i < priv->chan_num; i++)
|
|
{
|
|
regval = priv->channels[i].pincfg;
|
|
regval &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
|
|
regval |= (GPIO_OUTPUT | GPIO_VALUE_ZERO);
|
|
|
|
lpc17_40_configgpio(regval);
|
|
}
|
|
|
|
/* Power off the pwm peripheral */
|
|
|
|
regval = getreg32(LPC17_40_SYSCON_PCONP);
|
|
regval &= ~SYSCON_PCONP_PCPWM1;
|
|
putreg32(regval, LPC17_40_SYSCON_PCONP);
|
|
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: pwm_start
|
|
*
|
|
* Description:
|
|
* (Re-)initialize the timer resources and start the pulsed output
|
|
*
|
|
* Input Parameters:
|
|
* dev - A reference to the lower half PWM driver state structure
|
|
* info - A reference to the characteristics of the pulsed output
|
|
*
|
|
* Returned Value:
|
|
* Zero on success; a negated errno value on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int pwm_start(struct pwm_lowerhalf_s *dev,
|
|
const struct pwm_info_s *info)
|
|
{
|
|
struct lpc17_40_pwmtimer_s *priv =
|
|
(struct lpc17_40_pwmtimer_s *)dev;
|
|
return pwm_timer(priv, info);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: pwm_stop
|
|
*
|
|
* Description:
|
|
* Stop the pulsed output and reset the timer resources
|
|
*
|
|
* Input Parameters:
|
|
* dev - A reference to the lower half PWM driver state structure
|
|
*
|
|
* Returned Value:
|
|
* Zero on success; a negated errno value on failure
|
|
*
|
|
* Assumptions:
|
|
* This function is called to stop the pulsed output at anytime. This
|
|
* method is also called from the timer interrupt handler when a repetition
|
|
* count expires... automatically stopping the timer.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int pwm_stop(struct pwm_lowerhalf_s *dev)
|
|
{
|
|
struct lpc17_40_pwmtimer_s *priv =
|
|
(struct lpc17_40_pwmtimer_s *)dev;
|
|
uint32_t resetbit;
|
|
uint32_t regaddr;
|
|
irqstate_t flags;
|
|
|
|
pwminfo("TIM%d\n", priv->timid);
|
|
|
|
/* Disable interrupts momentary to stop any ongoing timer processing and
|
|
* to prevent any concurrent access to the reset register.
|
|
*/
|
|
|
|
flags = enter_critical_section();
|
|
|
|
/* Disable further interrupts and stop the timer */
|
|
|
|
/* Determine which timer to reset */
|
|
|
|
switch (priv->timid)
|
|
{
|
|
#ifdef CONFIG_LPC17_40_PWM1
|
|
case 1:
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
/* Reset the timer - stopping the output and putting the timer back
|
|
* into a state where pwm_start() can be called.
|
|
*/
|
|
|
|
leave_critical_section(flags);
|
|
|
|
pwminfo("regaddr: %08lx resetbit: %08lx\n", regaddr, resetbit);
|
|
pwm_dumpregs(priv, "After stop");
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: pwm_ioctl
|
|
*
|
|
* Description:
|
|
* Lower-half logic may support platform-specific ioctl commands
|
|
*
|
|
* Input Parameters:
|
|
* dev - A reference to the lower half PWM driver state structure
|
|
* cmd - The ioctl command
|
|
* arg - The argument accompanying the ioctl command
|
|
*
|
|
* Returned Value:
|
|
* Zero on success; a negated errno value on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int pwm_ioctl(struct pwm_lowerhalf_s *dev,
|
|
int cmd, unsigned long arg)
|
|
{
|
|
#ifdef CONFIG_DEBUG_PWM_INFO
|
|
struct lpc17_40_pwmtimer_s *priv =
|
|
(struct lpc17_40_pwmtimer_s *)dev;
|
|
|
|
/* There are no platform-specific ioctl commands */
|
|
|
|
pwminfo("TIM%d\n", priv->timid);
|
|
#endif
|
|
return -ENOTTY;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: lpc17_40_pwminitialize
|
|
*
|
|
* Description:
|
|
* Initialize one timer for use with the upper_level PWM driver.
|
|
*
|
|
* Input Parameters:
|
|
* timer - A number identifying the timer use. The number of valid timer
|
|
* IDs varies with the STM32 MCU and MCU family but is somewhere in
|
|
* the range of {1,..,14}.
|
|
*
|
|
* Returned Value:
|
|
* On success, a pointer to the STM32 lower half PWM driver is returned.
|
|
* NULL is returned on any failure.
|
|
*
|
|
****************************************************************************/
|
|
|
|
struct pwm_lowerhalf_s *lpc17_40_pwminitialize(int timer)
|
|
{
|
|
struct lpc17_40_pwmtimer_s *lower;
|
|
|
|
pwminfo("TIM%d\n", timer);
|
|
|
|
switch (timer)
|
|
{
|
|
#ifdef CONFIG_LPC17_40_PWM1
|
|
|
|
case 0:
|
|
lower = &g_pwm1dev;
|
|
|
|
/* Attach but disable the TIM1 update interrupt */
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
pwmerr("ERROR: No such timer configured or pin defined\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* Ensure PWM has been shutdown */
|
|
|
|
pwm_shutdown((struct pwm_lowerhalf_s *)lower);
|
|
|
|
return (struct pwm_lowerhalf_s *)lower;
|
|
}
|
|
|
|
#endif /* CONFIG_LPC17_40_TIMn_PWM, n = 1,...,14 */
|