232 lines
7.2 KiB
C
232 lines
7.2 KiB
C
/****************************************************************************
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* arch/arm/src/nuc1xx/nuc_timerisr.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <time.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "nvic.h"
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#include "clock/clock.h"
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#include "arm_internal.h"
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#include "chip.h"
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#include "hardware/nuc_clk.h"
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#include "hardware/nuc_gcr.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Get the frequency of the selected clock source */
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#if defined(CONFIG_NUC_SYSTICK_CORECLK)
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# define SYSTICK_CLOCK BOARD_HCLK_FREQUENCY /* Core clock */
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#elif defined(CONFIG_NUC_SYSTICK_XTALHI)
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# define SYSTICK_CLOCK BOARD_XTALHI_FREQUENCY /* High speed XTAL clock */
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#elif defined(CONFIG_NUC_SYSTICK_XTALLO)
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# define SYSTICK_CLOCK BOARD_XTALLO_FREQUENCY /* Low speed XTAL clock */
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#elif defined(CONFIG_NUC_SYSTICK_XTALHId2)
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# define SYSTICK_CLOCK (BOARD_XTALHI_FREQUENCY/2) /* High speed XTAL clock/2 */
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#elif defined(CONFIG_NUC_SYSTICK_HCLKd2)
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# define SYSTICK_CLOCK (BOARD_HCLK_FREQUENCY/2) /* HCLK/2 */
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#elif defined(CONFIG_NUC_SYSTICK_INTHId2)
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# define SYSTICK_CLOCK (NUC_INTHI_FREQUENCY/2) /* Internal high speed clock/2 */
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#endif
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/* The desired timer interrupt frequency is provided by the definition
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* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
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* system clock ticks per second. That value is a user configurable setting
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* that defaults to 100 (100 ticks per second = 10 MS interval).
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*
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* Then, for example, if the external high speed crystal is the SysTick
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* clock source and BOARD_XTALHI_FREQUENCY is 12MHz and CLK_TCK is 100, then
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* the reload value would be:
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*
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* SYSTICK_RELOAD = (12,000,000 / 100) - 1
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* = 119,999
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* = 0x1d4bf
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*
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* Which fits within the maximum 24-bit reload value.
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*/
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#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1)
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/* The size of the reload field is 24 bits. Verify that the reload value
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* will fit in the reload register.
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*/
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#if SYSTICK_RELOAD > 0x00ffffff
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# error SYSTICK_RELOAD exceeds the range of the RELOAD register
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: nuc_unlock
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*
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* Description:
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* Unlock registers
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifndef CONFIG_NUC_SYSTICK_CORECLK
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static inline void nuc_unlock(void)
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{
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putreg32(0x59, NUC_GCR_REGWRPROT);
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putreg32(0x16, NUC_GCR_REGWRPROT);
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putreg32(0x88, NUC_GCR_REGWRPROT);
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}
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#endif
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/****************************************************************************
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* Name: nuclock
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*
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* Description:
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* Lok registers
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifndef CONFIG_NUC_SYSTICK_CORECLK
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static inline void nuc_lock(void)
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{
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putreg32(0, NUC_GCR_REGWRPROT);
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}
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#endif
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/****************************************************************************
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* Function: nuc_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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static int nuc_timerisr(int irq, uint32_t *regs, void *arg)
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{
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/* Process timer interrupt */
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nxsched_process_timer();
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return 0;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_timer_initialize
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*
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* Description:
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* This function is called during start-up to initialize
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* the timer interrupt.
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*
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****************************************************************************/
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void up_timer_initialize(void)
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{
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uint32_t regval;
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/* Configure the SysTick clock source. This is only necessary if we are not
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* using the Cortex-M0 core clock as the frequency source.
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*/
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#ifndef CONFIG_NUC_SYSTICK_CORECLK
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/* This field is write protected and must be unlocked */
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nuc_unlock();
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/* Read the CLKSEL0 register and set the STCLK_S field appropriately */
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regval = getreg32(NUC_CLK_CLKSEL0);
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regval &= ~CLK_CLKSEL0_STCLK_S_MASK;
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#if defined(CONFIG_NUC_SYSTICK_XTALHI)
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regval |= CLK_CLKSEL0_STCLK_S_XTALHI; /* High speed XTAL clock */
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#elif defined(CONFIG_NUC_SYSTICK_XTALLO)
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regval |= CLK_CLKSEL0_STCLK_S_XTALLO; /* Low speed XTAL clock */
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#elif defined(CONFIG_NUC_SYSTICK_XTALHId2)
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regval |= CLK_CLKSEL0_STCLK_S_XTALDIV2; /* High speed XTAL clock/2 */
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#elif defined(CONFIG_NUC_SYSTICK_HCLKd2)
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regval |= CLK_CLKSEL0_STCLK_S_HCLKDIV2; /* HCLK/2 */
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#elif defined(CONFIG_NUC_SYSTICK_INTHId2)
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regval |= CLK_CLKSEL0_STCLK_S_INTDIV2; /* Internal high speed clock/2 */
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#endif
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putreg32(regval, NUC_CLK_CLKSEL0);
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/* Re-lock the register */
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nuc_lock();
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#endif
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/* Set the SysTick interrupt to the default priority */
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regval = getreg32(ARMV6M_SYSCON_SHPR3);
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regval &= ~SYSCON_SHPR3_PRI_15_MASK;
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regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT);
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putreg32(regval, ARMV6M_SYSCON_SHPR3);
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/* Configure SysTick to interrupt at the requested rate */
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putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR);
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/* Attach the timer interrupt vector */
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irq_attach(NUC_IRQ_SYSTICK, (xcpt_t)nuc_timerisr, NULL);
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/* Enable SysTick interrupts. We need to select the core clock here if
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* we are not using one of the alternative clock sources above.
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*/
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#ifdef CONFIG_NUC_SYSTICK_CORECLK
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putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT |
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SYSTICK_CSR_ENABLE),
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ARMV6M_SYSTICK_CSR);
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#else
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putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR);
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#endif
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/* And enable the timer interrupt */
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up_enable_irq(NUC_IRQ_SYSTICK);
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}
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