256 lines
7.3 KiB
ArmAsm
256 lines
7.3 KiB
ArmAsm
/****************************************************************************
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* arch/hc/src/m9s12/m9s12_start.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/board/board.h>
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#include "m9s12.h"
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#include "m9s12_mmc.h"
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#include "m9s12_crg.h"
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#include "m9s12_flash.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_HCS12_NONBANKED
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# define CALL jsr
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# define RETURN rts
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#else
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# define CALL call
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# define RETURN rtc
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#endif
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#define INITRG_REG (MMC_INITRG_REG(HCS12_REG_BASE))
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#define INITRM_MAP (MMC_INITRM_RAM(HCS12_SRAM_BASE)|MMC_INITRM_RAMHAL)
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#define INITEE_EE (MMC_INITEE_EE(HCS12_EEPROM_BASE)|MMC_INITEE_EEON)
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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.file "m9s12_start.S"
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.globl __start
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.globl nx_start
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.globl up_lowsetup
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.globl hcs12_boardinitialize
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/****************************************************************************
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* Macros
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****************************************************************************/
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/* Print a character on the UART to show boot status. This macro will
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* modify r0, r1, r2 and r14
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*/
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.macro showprogress, code
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#ifdef CONFIG_DEBUG_FEATURES
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ldab \code
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#ifdef CONFIG_HCS12_SERIALMON
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jsr #PutChar
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#else
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CALL up_lowputc
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#endif
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#endif
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.endm
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/* Memory map initialization.
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*
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* The MC9S12NE64 has 64K bytes of FLASH EEPROM and 8K bytes of RAM.
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*/
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.macro MMCINIT
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/* Registers are always positioned at address 0x0000 */
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movb #INITRG_REG, HCS12_MMC_INITRG /* Set the register map position to 0x0000*/
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nop
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/* Position SRAM so that is ends at address 0x3fff. This is required
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* because the Freescale serial monitor initializes its stack to the
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* end+1 of SRAM which it expects to be at address 0x4000
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*/
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movb #INITRM_MAP, HCS12_MMC_INITRM /* Set RAM position to 0x2000-0x3fff */
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movb #INITEE_EE, HCS12_MMC_INITEE /* Set EEPROM position to 0x0800 */
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/* In the non-banked mode, PPAGE is set to 0x3d to create a (non-contiguous),
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* fixed, 48Kb .text address space.
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*/
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#ifdef CONFIG_HCS12_NONBANKED
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movb #0x3d, HCS12_MMC_PPAGE
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#endif
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movb #MMC_MISC_ROMON, HCS12_MMC_MISC /* MISC: EXSTR1=0 EXSTR0=0 ROMHM=0 ROMON=1 */
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.endm
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/* System clock initialization. If the serial monitor is used, then clocking will have
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* already been configured at 24 MHz
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*/
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.macro PLLINIT
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#ifndef CONFIG_HCS12_SERIALMON
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/* Select the clock source from crystal */
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clr HCS12_CRG_CLKSEL
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/* Set the multipler and divider and enable the PLL */
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bclr *HCS12_CRG_PLLCTL #CRG_PLLCTL_PLLON
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ldab #HCS12_SYNR_VALUE
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stab HCS12_CRG_SYNR
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ldab #HCS12_REFDV_VALUE
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stab HCS12_CRG_REFDV
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bset *HCS12_CRG_PLLCTL #CRG_PLLCTL_PLLON
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/* Wait for the PLL to lock on */
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.Lpll_lock:
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brclr *HCS12_CRG_CRGFLG #CRG_CRGFLG_LOCK .Lpll_lock
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/* Then select the PLL clock source */
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bset *HCS12_CRG_CLKSEL #CRG_CLKSEL_PLLSEL
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#endif
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.endm
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/****************************************************************************
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* .text
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****************************************************************************/
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.section nonbanked, "x"
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/****************************************************************************
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* Name: __start
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*
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* Description:
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* Power-up reset entry point
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*
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****************************************************************************/
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__start:
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/* Hardware setup */
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MMCINIT /* Initialize the MMC */
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PLLINIT /* Initialize the PLL */
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/* Setup the stack pointer */
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lds .Lstackbase
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/* Perform early, low-level initialization */
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#ifndef CONFIG_HCS12_SERIALMON
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CALL up_lowsetup
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#endif
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showprogress 'A'
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/* Clear BSS */
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ldx .Lsbss /* Start of .BSS */
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ldd .Lebss /* End+1 of .BSS */
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.Lclearbss:
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pshd
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cpx 2,sp+ /* Check if all BSS has been cleared */
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beq .Lbsscleared /* If so, exit the loop */
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clr 0,x /* Clear this byte */
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inx /* Address the next byte */
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bra .Lclearbss /* And loop until all cleared */
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.Lbsscleared:
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showprogress 'B'
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/* Initialize the data section */
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ldx .Lsdata /* Start of .DATA (destination) */
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movw .Ledata, 0, sp /* End of .DATA (destination) */
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ldy .Leronly /* Start of .DATA (source) */
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.Linitdata:
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cpx 0, sp /* Check if all .DATA has been initialized */
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beq .Ldatainitialized /* If so, exit the loop */
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ldab 0, y /* Fetch the next byte from the source */
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iny /* Increment the source address */
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stab 0, x /* Store the byte to the destination */
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inx /* Increment the destination address */
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bra .Linitdata /* And loop until all of .DATA is initialized */
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.Ldatainitialized:
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showprogress 'C'
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/* Perform early board-level initialization */
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CALL hcs12_boardinitialize
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showprogress 'D'
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/* Now, start the OS */
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showprogress '\n'
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CALL nx_start
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bra __start
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/* Variables:
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* _sbss is the start of the BSS region (see ld.script)
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* _ebss is the end of the BSS region (see ld.script)
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* The idle task stack starts at the end of BSS and is
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* of size CONFIG_IDLETHREAD_STACKSIZE. The heap continues
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* from there until the end of memory. See g_idle_topstack
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* below.
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*/
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.Lsbss:
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.hword _sbss
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.Lebss:
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.hword _ebss
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.Lstackbase:
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.hword _ebss+CONFIG_IDLETHREAD_STACKSIZE
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.Leronly:
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.hword _eronly /* Where .data defaults are stored in FLASH */
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.Lsdata:
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.hword _sdata /* Where .data needs to reside in SDRAM */
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.Ledata:
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.hword _edata
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.size __start, .-__start
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/************************************************************************************
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* .rodata
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************************************************************************************/
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.section .rodata, "a"
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/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
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* of the BSS region (see ld.script). The idle task stack starts at the end of BSS
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* and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that
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* the system boots on and, eventually, becomes the idle, do nothing task that runs
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* only when there is nothing else to run. The heap continues from there until the
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* end of memory. See g_idle_topstack below.
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*/
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.globl g_idle_topstack
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.type g_idle_topstack, object
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g_idle_topstack:
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.hword _ebss+CONFIG_IDLETHREAD_STACKSIZE
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.size g_idle_topstack, .-g_idle_topstack
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.end
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