1f02c05c6d
This provides an alternate tickless scheduling method, which uses the riscv mtimer as a timebase, allowing the time and timeh registers to used throughout an application. The exiting tickless method, using Litex's timer0 has been left in place, as it is a more performant option, but currently has the potential issue identified in #11189. |
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| .. | ||
| arm | ||
| arm64 | ||
| avr | ||
| ceva | ||
| dummy | ||
| hc | ||
| mips | ||
| misoc | ||
| or1k | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| tricore | ||
| x86 | ||
| x86_64 | ||
| xtensa | ||
| z16 | ||
| z80 | ||
| CMakeLists.txt | ||
| Kconfig | ||