2e7f75f6e0
Chip name : rp23xx-rv Board name : raspberrypi-pico-2-rv Arch : risc-v Changes from ARM rp23xx impl - Linker script update - ASM head start - Update chip start - New Hazard3 registers - Remove rp23xx chip hw spinlocks/testset - New irq handling (external IRQ interrupt Hazard3) - New timerisr based on RISC-V std MTIME and alarm arch - No SMP yet - Tickless option - Double size for idle, irq and main stacks - Board reset via watchdog trigger Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
119 lines
9.8 KiB
C
119 lines
9.8 KiB
C
/****************************************************************************
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* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_io_bank0.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_BANK0_H
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#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_BANK0_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "hardware/rp23xx_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define RP23XX_IO_BANK0_GPIO_STATUS_OFFSET(n) ((n) * 8 + 0x000000)
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#define RP23XX_IO_BANK0_GPIO_CTRL_OFFSET(n) ((n) * 8 + 0x000004)
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#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_SECURE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x10) + 0x000200)
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#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_NONSECURE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x10) + 0x000208)
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#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET(n) (((n) >> 3) * 4 + 0x00000220)
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#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET(n) (((n) >> 3) * 4 + 0x00000228)
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#define RP23XX_IO_BANK0_INTR_OFFSET(n) (((n) >> 3) * 4 + 0x000230)
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#define RP23XX_IO_BANK0_PROC_INTE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x48) + 0x000248)
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#define RP23XX_IO_BANK0_PROC_INTF_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x48) + 0x000260)
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#define RP23XX_IO_BANK0_PROC_INTS_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x48) + 0x000278)
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#define RP23XX_IO_BANK0_DORMANT_WAKE_INTE_OFFSET(n) (((n) >> 3) * 4 + 0x0002d8)
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#define RP23XX_IO_BANK0_DORMANT_WAKE_INTF_OFFSET(n) (((n) >> 3) * 4 + 0x0002f0)
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#define RP23XX_IO_BANK0_DORMANT_WAKE_INTS_OFFSET(n) (((n) >> 3) * 4 + 0x000308)
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/* Register definitions *****************************************************/
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#define RP23XX_IO_BANK0_GPIO_STATUS(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_GPIO_STATUS_OFFSET(n))
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#define RP23XX_IO_BANK0_GPIO_CTRL(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_GPIO_CTRL_OFFSET(n))
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#define RP23XX_IO_BANK0_INTR(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_INTR_OFFSET(n))
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#define RP23XX_IO_BANK0_PROC_INTE(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_PROC_INTE_OFFSET(n, p))
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#define RP23XX_IO_BANK0_PROC_INTF(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_PROC_INTF_OFFSET(n, p))
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#define RP23XX_IO_BANK0_PROC_INTS(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_PROC_INTS_OFFSET(n, p))
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#define RP23XX_IO_BANK0_DORMANT_WAKE_INTE(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_DORMANT_WAKE_INTE_OFFSET(n))
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#define RP23XX_IO_BANK0_DORMANT_WAKE_INTF(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_DORMANT_WAKE_INTF_OFFSET(n))
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#define RP23XX_IO_BANK0_DORMANT_WAKE_INTS(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_DORMANT_WAKE_INTS_OFFSET(n))
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#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_SECURE(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_PROC_SECURE_OFFSET(n, p))
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#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_NONSECURE(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_PROC_NONSECURE_OFFSET(n, p))
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#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET(n))
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#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET(n))
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/* Register bit definitions *************************************************/
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#define RP23XX_IO_BANK0_GPIO_STATUS_IRQTOPROC (1 << 26) /* interrupt to processors, after override is applied */
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#define RP23XX_IO_BANK0_GPIO_STATUS_INFROMPAD (1 << 17) /* input signal from pad, before override is applied */
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#define RP23XX_IO_BANK0_GPIO_STATUS_OETOPAD (1 << 13) /* output enable to pad after register override is applied */
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#define RP23XX_IO_BANK0_GPIO_STATUS_OUTTOPAD (1 << 9) /* output signal to pad after register override is applied */
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#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_SHIFT (28)
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#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT)
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#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* don't invert the interrupt */
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#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* invert the interrupt */
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#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_LOW (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* drive interrupt low */
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#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_HIGH (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* drive interrupt high */
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#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_SHIFT (16)
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#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT)
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#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* don't invert the peri input */
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#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* invert the peri input */
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#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_LOW (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* drive peri input low */
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#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_HIGH (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* drive peri input high */
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#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_SHIFT (14)
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#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT)
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#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* drive output enable from peripheral signal selected by funcsel */
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#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* drive output enable from inverse of peripheral signal selected by funcsel */
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#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_DISABLE (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* disable output */
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#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_ENABLE (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* enable output */
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#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_SHIFT (12)
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#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT)
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#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output from peripheral signal selected by funcsel */
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#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output from inverse of peripheral signal selected by funcsel */
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#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_LOW (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output low */
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#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_HIGH (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output high */
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_MASK (0x1f)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_HSTX (0x0)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_SPI (0x1)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_UART (0x2)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_I2C (0x3)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PWM (0x4)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_SIO (0x5)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO0 (0x6)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO1 (0x7)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO2 (0x8)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_GPCK (0x9)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_USB (0xa)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_UART_AUX (0xb)
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#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_NULL (0x1f)
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#define RP23XX_IO_BANK0_INTR_GPIO_EDGE_HIGH(n) (1 << (((n) & 0x7) * 4 + 3))
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#define RP23XX_IO_BANK0_INTR_GPIO_EDGE_LOW(n) (1 << (((n) & 0x7) * 4 + 2))
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#define RP23XX_IO_BANK0_INTR_GPIO_LEVEL_HIGH(n) (1 << (((n) & 0x7) * 4 + 1))
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#define RP23XX_IO_BANK0_INTR_GPIO_LEVEL_LOW(n) (1 << (((n) & 0x7) * 4))
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#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_BANK0_H */
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