To avoid level-1 interrupt break retrieve PC/A0/SP/A2 register, PS.EXCM set to 1 by CPU HW while handling exception/interrupt. But if context switching happens and new thread created, the thread initial value of PS.EXCM is used. Same behevior as ESP-IDF code: https://github.com/espressif/esp-idf/blob/master/ components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c#L366 Signed-off-by: Gao Feng <Feng.Gao@sony.com> |
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| CMakeLists.txt | ||
| Kconfig | ||