Huang Qi 36ff081b1a risc-v: Support more than 2 cores in riscv_cpu_boot ... Signed-off-by: Huang Qi <huangqi3@xiaomi.com>		2022-02-18 13:25:01 +08:00
..
include	Extend the RISC-V PMP functionality	2022-01-25 20:22:34 +08:00
src	risc-v: Support more than 2 cores in riscv_cpu_boot	2022-02-18 13:25:01 +08:00
Kconfig	Extend the RISC-V PMP functionality	2022-01-25 20:22:34 +08:00